视频信号处理系统中运动估计加速器模块基于SystemVerilog语言的验证(硕士论文)

硕士研究生学位论文

题目：视频信号处理系统中运动估计加速器模块基于

SystemVerilog语言的验证

姓名：方芳

学号： 10548399

院系：信息科学技术学院

专业：电子与通信工程

研究方向： SoC设计

导师姓名：王新安副教授

二00八年六月

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摘要

本文对视频信号处理系统中运动估计加速器模块的功能实现算法进行了一定程度的分析与研究，通过分析当今业界主要应用的验证技术，结合公司的实际情况选用了先进的验证方法，在EDA工具的支持下对运动估计加速器模块进行了全面的功能性验证。文中还详细剖析了芯片验证环境，这是一个运用SystemVerilog语言的仿真环境，利用总线功能模型（BFM）实现总线操作，使得验证在事务级（transaction level）进行，大大提高了验证的效率及可复用性。

本文针对运动估计加速器模块设计了足够的验证case，覆盖了模块的各项功能，并运用SystemVerilog搭建了高效的验证平台，通过Perl脚本对整个验证架构中进行仿真管理与控制，实现了对C_model的实时调用、输入参数的随机生成以及输出数据的实时比对等自动化功能。此外还与其他验证工程师合作搭建了视频信号处理系统的联合仿真平台，该平台实现了视频信号处理中所有模块的系统级验证。此外，对视频信号处理系统还进行了FPGA 验证，作为对基于仿真的验证的有效补充。网表（netlist）设计完成以后还进行了post-layout simulation（后仿真），对芯片设计部门而言是流片前签发的最后一个环节。

本文还通过先进的EDA工具及芯片仿真环境的支持，对运动估计加速器模块代码覆盖率进行了统计分析。对运动估计加速器模块的验证通过了展讯公司模块验证的评审流程，被认为是充分的。实践表明，本文所采用的验证方法和结构是适合SC8800E芯片项目开发的，具有灵活性好、效率高、可复用性强等优点。

关键词：系统级芯片，SystemVerilog，SystemVerilog验证方法学

Abstract

SystemVerilog based verification of MEA module in video signal

processing system

Fang Fang (Electronic and communication)

Directed by Wang Xinan

In this paper, the MEA module algorithm is analyzed and researched to some extent. In addition，through studying the popular verification techniques in IC industry，the whole functional verification for MEA module in TD-SCDMA/GSM chip SC8800E is completed, with the use of advanced verification methodology and the support of EDA tools. The verification environment platform in the chip level for MEA is also detailed in this paper. This is a multi-language simulation environment using Verilog, SystemVerilog, etc. The bus function is implemented by using the reusable BFM (Bus Functional Model), so that the verification work can carry out at the higher level more efficiently.

Also, in this paper, there are enough test cases designed for MEA module verification, which aim at covering all the features of the design. The verification platform is described using SystemVerilog, and Perl script is used to control the whole simulation in the verification structure, so that reference model in C_model can be called on the fly, the input parameters can be generated randomly and the output data can compared with the expected data automatically. Besides, with the other verification engineers’team work, a simulation platform for image signal processing system has been built up. This platform implemented the system level verification of all ISP modules. Moreover, the verification of MEA module is also implemented with FPGA verification as an effective supplementary of simulation-based verification. After the design of netlist, post-layout simulation is also done, which is the last sign-off step before taping the chip out for chip design department.

With the support of advanced EDA tools and chip level verification environment, in this paper, the code coverage analysis and statistic job for MEA