CPU设计实验报告文档(英文版)

Southeast University Microprogra m med CPU Design -- COA experimentSchool of Information Science and Engineering04009XXX2012-4-25PurposeThe purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need consider the following items: Read/Write Registers, Read/Write Memory and Execute the instructions.At least four parts constitute a simple CPU: the control unit, the internal registers, the ALU and instruction set, which are the main aspects of our project design and will be studied.Instruction SetSingle-address instruction format is used in our simple CPU design. The instruction word contains two sections: the operation code (opcode), which defines the function of instructions (addition, subtraction, logic operations, etc.); the address part, in most instructions, the address part contains the memory location of the datum to be operated, we called it direct addressing. In some instructions, the address part is the operand, which is called immediate addressing.For simplicity, the size of memory is 256×16 in the computer. The instruction word has 16 bits. The opcode part has 8 bits and address part has 8 bits. The instruction word format can be expressed in Figure 1Figure 1 the instruction formatThe opcode of the relevant instructions are listed in Table 1.In Table 1, the notation [x] represents the contents of the location x in the memory. For example, the instruction word 00000011101110012 (03B916) means that the CPU adds word at location B916 in memory into the accumulator (ACC); the instruction word 00000101000001112 (050716) means if the sign bit of the ACC (ACC [15]) is 0, the CPU will use the address part of the instruction as the address of next instruction, if the sign bit is 1, the CPU will increase the program counter (PC) and use its content 7as the address of the next instruction.Table 1 List of instructions and relevant opcodesAll the instructions except the Division instruction are supported in my design. Internal Registers and MemoryMAR (Memory Address Register)MAR contains the memory location of the word to be read from the memory or written into the memory. Here, READ operation is denoted as the CPU reads from memory, and WRITE operation is denoted as the CPU writes to memory. In our design, MAR has 8 bits to access one of 256 addresses of the memory.MBR (Memory Buffer Register)MBR contains the value to be stored in memory or the last value read from memory. MBR is connected to the address lines of the system bus. In our design, MBR has 16 bits.PC (Program Counter)PC keeps track of the instructions to be used in the program. In our design, PC has 8 bits.IR (Instruction Register)IR contains the opcode part of an instruction. In our design, IR has 8 bits.BR (Buffer Register)BR is used as an input of ALU, it holds other operand for ALU. In our design, BR has 16 bits.ACC (Accumulator)A CC holds one operand for ALU, and generally ACC holds the calculation result of ALU. In my design, ACC has 16 bits.In this designment, ACC is set in ALU for simplification.MR (Multiplier Register)MR is used for implementing the MPY instruction, holding the multiplier at the beginning of the instruction. When the instruction is executed, it holds part of theproduct (the high part of the 32-bit product).LPM_RAM_DQLPM_RAM_DQ is a RAM with separate input and output ports, it works as memory, and its size is 256×16. Although it’s not an internal register of CPU, we need it to simulate and test the performance of CPU.LPM_ROMLPM_ROM is a ROM with separate input and output ports, it works as memory,and its size is 256×32. Although it’s not an internal register of CPU, we need it to simulate and test the performance of CPU.All the registers are positive-edge-triggered.All the reset signals for the registers are synchronized to the clock signal.ALUALU (Arithmetic Logic Unit) is a calculation unit which accomplishes basic arithmetic and logic operations. In our design, some operations must be supported which are listed as followsMicroprogrammed Control UnitWe have learnt the knowledge of Microprogrammed control unit. Here, we only review some terms and basic structures.In the Microprogrammed control, the microprogram consists of some microinstructions and the microprogram is stored in control memory that generates all the control signals required to execute the instruction set correctly. The microinstruction contains some micro-operations which are executed at the same time.Figure 2 Control Unit Micro-architectureFigure 2 shows the key elements of such an implementation. The set of microinstructions is stored in the control memory. The control address register contains the address of the next microinstructions to be read. When a microinstruction is read from the control memory, it is transferred to a control buffer register. The register connects to the control lines emanating from the control unit. Thus, reading a microinstruction from the control memory is the same as executing that microinstruction. The third element shown in the figure is a sequencing unit that loads the control address register and issues a read command.Figure 3 indicates a simple CPU architecture and its use of a variety of internal data paths and control signals. Our CPU design should be based on this architecture. Microprogrammed ControlFor each micro-operation, all that the control unit is allowed to do is generate a set of control signals. Each control line is either on or off, which can be represented by a binary digit for each control line. So we could construct a control word in which each bit represents one control line.The set of microinstructions is stored in the control memory. The control address register contains the address of the next microinstruction to be read. When a microinstruction is read from the control memory, it is transferred to a control buffer register, which register connects to the control lines emanating from the control unit. Thus reading a microinstruction from the control memory is the same as executing that microinstruction!Control signals：In my design,there are 32 bits of control signals,as the fallow table shows.Table 3 Control signalsTable 4 The Sequence of MicroinstructionsTable 5 The meaning of each bit of the 8-bit flag.The Design of MAR、MBR、PC、IR、BR、ACC、ALU、LPM_RAM_DQThe Design of CPU:The Design of romThe Simulation Input WaveformsTestTest of ADD, SUB, JMPGEZ, SHIFTR, AND and NOT. Calculate not( (1+2+3+…+10)/2 or “10011010”), and save the final answer.Table 6 Test Problem 2IR<=MBR(15..0) “02”represents “STORE”LOAD A0(0000) STORE B0(0000)LOAD B0(000A) ADD B1(0009)LOAD B1(0009)SUB A2(0001)ACC<=ACC-BR(09h-01h=08h) JMPGEZSHIFTROR A3(009A)RAMNOTACC<=NOT BR (NOT 009B=FF64h)APPENDIX------------------MAR------------------library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity MAR isport( clk,reset,c18,c19:in std_logic;PC_in: in std_logic_vector(7 downto 0);MBR_in :in std_logic_vector(15 downto 0);MAR_out : out std_logic_vector(7 downto 0));end;architecture behave of MAR isbeginprocess(clk)variable MAR_temp : std_logic_vector(7 downto 0);beginif (rising_edge(clk)) thenif reset='0' thenMAR_temp:=x"00";elsif c18='1' thenMAR_temp:=PC_in;elsif c19='1' thenMAR_temp:=MBR_in(7 downto 0);end if;MAR_out<=MAR_temp;end if;end process;end behave;-------------------------------MBR------------------------------------- library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity MBR isport(clk,reset,c12,c16,c20: in std_logic;MEM_in: in std_logic_vector(15 downto 0);ACC_in: in std_logic_vector(15 downto 0);MR_in: in std_logic_vector(15 downto 0);MBR_out: out std_logic_vector(15 downto 0));end MBR;architecture behave of MBR isbeginprocess(clk)variable MBR_temp: std_logic_vector(15 downto 0);beginif(rising_edge(clk)) thenif reset='0' thenMBR_temp:=x"0000";elsif(c12='1') thenMBR_temp:=ACC_in;elsif(c16='1') thenMBR_temp:=MR_in;elsif(c20='1') thenMBR_temp:=MEM_in;end if;MBR_out<=MBR_temp;end if;end process;end behave;--------------------------------------PC------------------------------------- library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity PC isport(clk,reset,c7,c17: in std_logic;MBR_in: in std_logic_vector(15 downto 0);PC_out: out std_logic_vector(7 downto 0));end PC;architecture behave of PC isbeginprocess(clk)variable PC_temp: std_logic_vector(7 downto 0);beginif(rising_edge(clk)) thenif(reset='0') thenPC_temp:="00000000";end if;if(c7='1') thenPC_temp:=PC_temp+1;elsif(c17='1') thenPC_temp:=MBR_in(7 downto 0);end if;PC_out<=PC_temp;end if;end process;end behave;-----------------------------------IR------------------------------------ library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity IR isport(clk,reset,c14: in std_logic;MBR_in: in std_logic_vector(15 downto 0);IR_out: out std_logic_vector(7 downto 0));end IR;architecture behave of IR isbeginprocess(clk)variable IR_temp:std_logic_vector(7 downto 0);beginif(rising_edge(clk)) thenif reset='0' thenIR_temp:=x"00";end if;if(c14='1') thenIR_temp:=MBR_in(15 downto 8);end if;IR_out<=IR_temp;end if;end process;end behave;-----------------------------------BR------------------------------------ library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity BR isport( clk,reset,c13 :in std_logic;MBR_in :in std_logic_vector(15 downto 0);BR_out :out std_logic_vector(15 downto 0)); end BR;architecture behave of BR isbeginprocess(clk)variable BR_temp :std_logic_vector(15 downto 0);beginif (rising_edge(clk)) thenif reset='0' thenBR_temp:=x"0000";elsif c13='1' thenBR_temp:=MBR_in;end if;BR_out<=BR_temp;end if;end process;end behave;------------------------------ALU-------------------------library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ALU isport(clk,reset: in std_logic;c:in std_logic_vector(31 downto 0);BR_in,MBR_in:in std_logic_vector(15 downto 0);flag:out std_logic_vector(7 downto 0);ACC_out:out std_logic_vector(15 downto 0);ALU_to_MR: out std_logic_vector(15 downto 0));end ALU;architecture behave of ALU isbeginprocess(clk)variable ACC_temp: std_logic_vector(15 downto 0); variable BR_temp:std_logic_vector(15 downto 0); variable flags: std_logic_vector(7 downto 0):="00000000"; variable COUNTER:integer:=0;variable MR:std_logic_vector(15 downto 0);beginif (rising_edge(clk)) thenif reset='0' thenACC_temp:=x"0000";MR:=x"0000";elsif c(8)='1' thenACC_temp:=x"0000";end if;if c(23)='1' then--------addACC_temp:=ACC_temp+BR_in;elsif c(24)='1' then---------subACC_temp:=ACC_temp-BR_in;elsif c(25)='1' then---------shiftrACC_temp:='0'&ACC_temp(15 downto 1);elsif c(26)='1' then-----------shiftlACC_temp:=ACC_temp(14 downto 0)&'0';elsif c(27)='1' then------------andACC_temp:=ACC_temp and BR_in;elsif c(28)='1' then -----------orACC_temp:=ACC_temp or BR_in;elsif c(29)='1' then------------notACC_temp:=not BR_in;elsif(c(21)='1') then------ ready for MPYif((ACC_temp(15) xor BR_in(15))='1') thenflags:=flags or "00000100";--------- flags(2) end if;if(ACC_temp(15)='1') thenACC_temp:=not (ACC_temp-1);end if;if(BR_in(15)='1') thenBR_temp:=not(BR_in-1);elseBR_temp:=BR_in;end if;MR:="0000000000000000";COUNTER:=0;flags:=flags and "11110111";----- flags(3)elsif(c(30)='1') thenif(ACC_temp(0)='1') thenMR:=MR+BR_temp;end if;ACC_temp:=MR(0)&ACC_temp(15 downto 1);-------ACC shift rightMR:='0'&MR(15 downto 1);-------MR shift right(store the high bits of the product)COUNTER:=COUNTER+1;if(COUNTER=15) then ----COUNTER=16 or 15flags:=flags or "00001000";---------set flags(3) means MPY finished end if;elsif(c(9)='1') then ---------------------finish MPYif(flags(2)='1') then------------------the product is negativeif(ACC_temp="0000000000000000") thenMR:=(not MR)+1;elseACC_temp:=(not ACC_temp)+1;MR:=not MR;end if;MR(15):='1';-------the first bit which is also the sign bit shouldn't be complemented.flags:=flags and "11110011";--------reset flags(2) and flag(3)end if;end if;if(ACC_temp(15)='0') then-------ACC>0flags:=flags and "11111101"; --if ACC>0,flag(1)=ACC_temp(15)=0 elseflags:=flags or "00000010"; --if ACC<0,flag(1)=ACC_temp(15)=1 end if;ALU_to_MR<=MR;flag<=flags;ACC_out<=ACC_temp;end if;end process;end behave;--------------------------CAR------------------------ library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity CAR isport(clk,reset:in std_logic;IR_in:in std_logic_vector(7 downto 0);c: in std_logic_vector(31 downto 0);flags: in std_logic_vector(7 downto 0);addr: out std_logic_vector(7 downto 0) );end CAR;architecture behave of CAR isbeginprocess(clk)variable addtemp: std_logic_vector(7 downto 0); variable opcode: std_logic_vector(7 downto 0); beginif(rising_edge(clk)) thenopcode:=IR_in;if(c(0)='1') thenaddtemp:=addtemp+1;end if;if(c(1)='1') then --clearaddtemp:="00000000";end if;if (c(3)='1') then-------------for JMPGEZaddtemp:=addtemp+1+flags(1);end if;if(c(30)='1') then-------for MPYaddtemp:=addtemp+flags(3);end if;if (c(2)='1') thencase opcode iswhen "00000001"=>------------storeaddtemp:="00001000";-----------------08hwhen "00000010"=>------------loadaddtemp:="00010000";-----------------10hwhen "00000011"=>------------addaddtemp:="00011000";-----------------18hwhen "00000100"=>------------subaddtemp:="00100000";-----------------20hwhen "00000101"=>------------andaddtemp:="00101000";-----------------28hwhen "00000110"=>------------oraddtemp:="00110000";-----------------30hwhen"00000111"=>-------------notaddtemp:="00111000";-----------------38hwhen"00001000"=>------------shiftraddtemp:="01000000";-----------------40hwhen"00001001"=>------------shiftladdtemp:="01000001";-----------------41hwhen"00001010"=>------------jmpgezaddtemp:="01001000";-----------------48hwhen"00001011"=>-------------jmpaddtemp:="01010000";-----------------50hwhen"00001100"=>-------------mpyaddtemp:="01011000";-----------------58hwhen"00001101"=>---------store MRaddtemp:="01100000";-----------------60hwhen"00001110"=>-------------haltaddtemp:="11111111";-----------------ffhwhen others=>NULL;end case;end if;if(flags(0)='1')then --------initaddtemp:="00000000";end if;if(reset='0') then ------addtemp:="00000000";end if;addr<=addtemp;end if;end process; end behave;。