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微小差分电容检测电路设计

微小差分电容检测电路设计摘要电容式传感器广泛应用于位移、振动、角度、加速度等物理量的精密测量中。

由于受结构限制，其输出电容信号很小，一般为几pF至几十pF，精密测量其值更小，因此其后续测量电路的选择与设计非常关键。

本文简要介绍了传统及现有小电容测量方法，重点设计了一种用于微小差分电容检测的交流放大电路，阐述了此方法的基本原理及参数的选取原则。

实验结果和理论分析具有良好的一致性，并仿真出了实验结果，该电路具有抗寄生电容能力强、容易实现、成本低等优点。

关键词：差分电容，高频信号，电容传感器，抗寄生电容Design of measured circuit about micro differential capacitiveAbstractThe capacitive sensor widely used in precision measuring physical quantity such as displacement, vibration, angle and acceleration. For the structure limit, the output of capacitance sensor is very small, about several pF to several dozens pF, and smaller in the precision measurement, so it is important to select and design the capacitance measurement circuit. Several techniques for measuring of small capacitance including methods with tradition are briefly overviewed. A kind of AC amplifier circuit for micro differential capacitance sense is introduced in the text.The experiment results show a good correspondence with the theoretical analysis. The basic principle of the method and the principle of choose the parameters in the circuit are provided and test conclusion is given. The measurement is free of stray immune capacity, low-cost and easy for realization.Key word: differential capacitance, high frequency signal, capacitive sensor,stray-immune capacitance目录1 绪论11.1 电子测量技术的发展 (1)1.1.1 电子测量的特点 (1)1.1.2 常用的几种电容测量方法 (2)1.2 课题研究的目的和意义 (3)1.3 本课题的任务和内容 (4)2 电容式传感器52.1 电容传感器的分类 (5)2.1.1 变极距型电容传感器 (6)2.1.2 变面积型电容传感器 (8)2.1.3 变介电常数型电容传感器 (9)2.2 电容传感器的特点 (10)2.2.1 优点 (10)2.2.2 缺点 (10)2.3 应用中存在的问题 (11)2.3.1 附加损耗 (11)2.3.2 边缘效应 (12)3 电容电压转换电路133.1 变压器电桥 (13)3.2 二极管T型网络 (13)3.3 谐振法 (14)3.4 差动脉冲调宽电路 (14)3.5 运算放大器电路 (16)4 两种微小电容检测的方法174.1 直流充放电法 (17)4.2 高压双边交流激励法 (18)5 消除寄生电容的屏蔽技术205.1 增加传感器原始电容值 (20)5.2 传感器的接地和屏蔽 (20)5.3 集成化 (20)5.4 “驱动电缆”技术 (20)5.5 运算放大器法 (21)5.6 整体屏蔽 (21)6 电路设计与Multisim2001仿真分析236.1 测量原理 (23)6.2 电路设计 (24)6.2.1 高频信号发生器 (24)6.2.2 C/V转换及放大电路 (24)6.2.3 全波整流 (29)6.2.4 低通滤波 (30)7 结论34附录微小差分电容检测电路图35参考文献36致谢38外文文献原文译文1 绪论1.1 电子测量技术的发展测量是人类对客观事物取得数量概念的认识过程，是人们认识和改造自然的一种不可缺少的手段。

一种微小电容的测量电路

一种微小电容的测量电路刘宝华(河北理工学院自动化系　063009) 摘　要　介绍了一种数字电路与模拟电路相结合的测量电路,可用于微小电容的测量。

关键词　电容测量　检测器　放大器　相敏解调器1　引言传统的测量技术已经难以满足当代对微小电容测量及检测技术的要求,而利用线性闭环运算放大器的高频测量电路,能较好地解决这个问题。

图1为利用闭环运算放大器测量微小电容的基本原理电路。

图1　用运放测量电容的基本原理电路图中C x 、G x 分别为被测电容的电容量和等效并联漏电导,R f 为反相端反馈电阻。

由于采用了高速、高精度、高增益、宽频带、低漂移的运算放大器,因此,同相端可直接接地,而不必串平衡电阻。

该电路输出、输入电压之间的复数关系为U o =-(j ωC x R f +G x R f )U i 式中　ω———激励信号的角频率由公式可知测量电路对被测电容C x 的灵敏度与信号源角频率成正比;测量电路对等效并联漏电导的灵敏度为常数,与ω无关。

可见,高频条件可大大提高对被测电容的灵敏度,并有效降低漏电导的影响。

实施测量时只要测量两次,分别测出U o 和U i ,便可求得C x 和G x 。

然而没有性能优良的高频信号发生器、高频放大器和解调器,要想高精度、高灵敏度、高线性度、高稳定度、高速度、高分辨率地测量出微小电容量,仍然只是纸上谈兵。

2　一种实用测量电路本文提出一种性能优良、成本低廉的微小电容测量电路。

其原理框图如图2所示。

由图2可见,高频正弦信号发生器输出的激励信号施加在被测电容C x 上;高频电容电流被检测器变换为交流电压,再通过交流放大器放大后,通过隔离变压器送到相敏解调器进行解调;解调器的对边臂被两个互补方波轮流触发,解调后的信号通过低通滤波器滤除高次谐波,得到的直流电压与被测电容C x 成正比。

图2　小电容测量电路原理框图211　高频信号发生器用数字电路和数模转换器产生的正弦波信号,虽然在波幅稳定性和频率稳定性方面都优于模拟电路产生的正弦波信号,但由于现有的EPROM 及DAC 速度不太高,故难以产生高于100kHz 以上的正弦波信号,除非是特殊设计的集成电路。

微小电容测试电路

目录第一章绪论 (2)1.1. 研究现状及意义 (2)课题背景2本论文研究的内容 (3)第二章微小电容检测电路设计方式 (3). 微电容检测原理 (3)微电容检测的经常使用方式 (3)第三章微小电容检测电路系统的设计 (9)3．1时序电路的设计设计 (12)两相不交叠时钟的产生 (13)二分频电路的设计 (14)脉宽不对称分频器的设计 (15)所有时序电路的实现 (15)C-V 转换电路的设计 (19)双端转单端电路设计 20第四章总结与展望 (22)参考文献 (23)致谢 (25)第一章绪论1．1研究现状及意义加速度计作为一种测量加速度的仪器，在民用、军用领域都有普遍的应用在民用方面，普遍应用于汽车平安气囊等平安爱惜装置中；军用方面，加速度计是飞机、火箭、导弹中不可缺少的一部份。

随着微电子技术的飞速进展，芯片的集成度不断加大，如何设计出体积小、精度高、抗干扰能力强、对工作环境的适应能力强的加速度计，已经成为一个重要的课题[1，23]。

MEMS(微机电系统)电容式加速度计检测ASIC是一个数模混合集成电路，要紧部份是模拟集成电路。

随着MEMS工艺的提高，MEMS电容传感器的信号检测加倍具有挑战性，设计出对寄生电容阻碍小、低噪声、低失调的电容检测ASIC 对提高加速度计的性能有着超级重要的作用。

MEMS(Micro Electromechanical System 1最近几年来进展最快的技术之一，随着.MEMS技术的快速进展，电容式加速度计的电容转变转变量愈来愈小，对检测技术提出了新的要求。

在电容式传感器中，经常使用电容检测电路是将其转换为电压、电流或频率信号。

目前的微型电容传感器的极板面积变得愈来愈小，电容总量只有几个pF，转变量就更小。

针对这种微小电容的检测，目前的方式要紧有震荡电路、持续时刻电流读出方式、持续时刻电压读出方式、差动脉冲调宽电路、开关电容电荷积分方式，这几种都是利用模拟器件实现，输出均为模拟量。

微小精密电子有限公司 2014年版双极性电流差分接收器说明书

1FeaturesInputs/Outputs •Accepts two differential or single-ended inputs •LVPECL, LVDS, CML, HCSL, LVCMOS •Glitch-free switching of references•Eight precision LVDS outputs •Operating frequency up to 750 MHzPower •Option for 2.5 V or 3.3 V power supply •Current consumption of 110 mA•On-chip Low Drop Out (LDO) Regulator for superior power supply rejectionPerformance •Ultra low additive jitter of 194 fs RMSApplications•General purpose clock distribution •Low jitter clock trees •Logic translation•Clock and data signal restoration •Redundant clock distribution•Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC•PCI Express generation 1/2/3 clock distribution •Wireless communications•High performance microprocessor clock distributionApril 2014Figure 1 - Functional Block DiagramZL40222Precision 2:8 LVDS Fanout Buffer with Glitch-free Input Reference SwitchingData SheetOrdering InformationZL40222LDG1 32 Pin QFN TraysZL40222LDF132 Pin QFNTape and ReelMatte TinPackage size: 5 x 5 mm-40o C to +85o CTable of ContentsFeatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Inputs/Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.0 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73.1 Clock Input Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73.2 Clock Input Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83.3 Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133.4 Device Additive Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173.5.1 Sensitivity to power supply noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173.5.2 Power supply filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173.5.3 PCB layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174.0 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185.0 Performance Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206.0 Typical Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217.0 Package Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228.0 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23List of FiguresFigure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3 - Output During Clock Switch - Both Clocks Running . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4 - LVPECL Input DC Coupled Thevenin Equivalent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5 - LVPECL Input DC Coupled Parallel Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6 - LVPECL Input AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7 - LVDS Input DC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8 - LVDS Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9 - CML Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 10 - HCSL Input AC Coupled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11 - CMOS Input DC Coupled Referenced to VDD/2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 12 - CMOS Input DC Coupled Referenced to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 13 - Simplified LVDS Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 14 - LVDS DC Coupled Termination (Internal Receiver Termination). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 15 - LVDS DC Coupled Termination (External Receiver Termination) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 16 - LVDS AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 17 - LVDS AC Output Termination for CML Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 18 - Additive Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 19 - Decoupling Connections for Power Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 20 - Differential Voltage Parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 21 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Change SummaryBelow are the changes from the February 2013 issue to the April 2014 issue:Page Item Change1Applications Added PCI Express clock distribution.6Pin Description Added exposed pad to Pin Description.8Figure 4 and Figure 5Removed 22 Ohm series resistors from Figure 4 and 5. Theseresistors are not required; however there is no impact toperformance if the resistors are included.19Figure 20Clarification of V ID and V OD.Below are the changes from the November 2012 issue to the February 2013 issue:Page Item Change8Figure 5Changed text to indicate the circuit is not recommended forVDD_driver=2.5V.9Figure 6Changed pull-up and pull-down resistors from 2kOhm to100 Ohm.13Figure 13Changed gate values to +/+ on the left and -/- on the right.1.0 Package DescriptionThe device is packaged in a 32 pin QFNFigure 2 - Pin Connections2.0 Pin DescriptionPin # Name Description1,3, 6, 8clk0_p, clk0_n,clk1_p, clk1_nDifferential Input (Analog Input). Differential (or singled ended) input signals. For allinput signal configuration see Section 3.2, “Clock Input Termination“.30, 29, 28, 27, 26, 25, 24, 23, 18, 17, 16, 15, 14, 13, 12, 11 out0_p, out0_nout1_p, out1_nout2_p, out2_nout3_p, out3_nout4_p, out4_nout5_p, out5_nout6_p, out6_nout7_p, out7_nDifferential Output (Analog Output). Differential outputs.9, 19,22, 32vdd Positive Supply Voltage. 2.5V DC or 3.3 V DC nominal.20, 21gnd Ground. 0 V.31sel Input Select (Input). Selects the reference input that is buffered;0: clk01: clk1This pin is internally pulled down to GND.2, 4,5, 7, 10NC No Connection. Leave unconnected.Exposed Pad Device GND.3.0 Functional DescriptionThe ZL40222 is an LVDS clock fanout buffer with eight identical output clock drivers capable of operating at frequencies up to 750MHz.The two Inputs to the ZL40222 are externally terminated to allow use of precision termination components and to allow full flexibility of input termination. The ZL40222 can accept DC coupled LVPECL or LVDS and AC coupled LVPECL, LVDS, CML or HCSL input signals; single ended input signals can also be accepted. A pin compatible device with internal termination is also available.The ZL40222 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40°C to +85°C.The device block diagram is shown in Figure 1; its operation is described in the following sections.3.1 Clock Input SelectionThe select line chooses which input clock is routed to the outputs.Sel Active Input0 clk01clk1Table 1 - Input SelectionThe following figure shows the expected clock switching performance. The output stops at the first falling edge of the initial clock after the select pin changes state. During switching there will be a short time when the output clock is not toggling. After this delay, the output will start toggling again with a rising edge of the newly selected clock. This behavior is independent of the frequencies of the input clocks. For instance, the two clocks could be at different frequencies and the behavior would still be consistent with this figure.Figure 3 - Output During Clock Switch - Both Clocks Running3.2 Clock Input TerminationThe ZL40222 is adaptable to support different types of differential and singled-ened input signals depending on the passive components used in the input termination. The application diagrams in the following figures allow the ZL40222 to accept LVPECL, LVDS, CML, HCSL and single-ended inputs.Figure 4 - LVPECL Input DC Coupled Thevenin EquivalentFigure 5 - LVPECL Input DC Coupled Parallel TerminationFigure 6 - LVPECL Input AC Coupled TerminationFigure 7 - LVDS Input DC CoupledFigure 8 - LVDS Input AC CoupledFigure 9 - CML Input AC CoupledFigure 10 - HCSL Input AC CoupledFigure 11 - CMOS Input DC Coupled Referenced to VDD/2Figure 12 - CMOS Input DC Coupled Referenced to GroundVDD_driver R1 (kΩ)R2 (kΩ)R3 (kΩ)RA (kΩ) C (pF) 1.5 1.25 3.075open10101.81 3.8open10102.50.33 4.2open10103.30.75open4.21010Table 2 - Component Values for Single Ended Input Reference to Ground* For frequencies below 100 MHz, increase C to avoid signal integrity issues.3.3 Clock OutputsLVDS has lower signal swing than LVPECL which results in a low power consumption. A simplified diagram for the LVDS output stage is shown in Figure 13.Figure 13 - Simplified LVDS Output DriverThe methods to terminate the ZL40222 drivers are shown in the following figures.Figure 16 - LVDS AC Coupled TerminationFigure 17 - LVDS AC Output Termination for CML Inputs3.4 Device Additive JitterThe ZL40222 clock fanout buffer is not intended to filter clock jitter. The jitter performance of this type of device is characterized by its additive jitter. Additive jitter is the jitter the device would add to a hypothetical jitter-free clock as it passes through the device. The additive jitter of the ZL40222 is random and as such it is not correlated to the jitter of the input clock signal.The square of the resultant random RMS jitter at the output of the ZL40222 is equal to the sum of the squares of the various random RMS jitter sources including: input clock jitter; additive jitter of the buffer; and additive jitter due to power supply noise. There may be additional deterministic jitter sources, but they are not shown in Figure 18.Figure 18 - Additive Jitter3.5 Power SupplyThis device operates with either a 2.5V supply or 3.3V supply.3.5.1 Sensitivity to power supply noisePower supply noise from sources such as switching power supplies and high-power digital components such as FPGAs can induce additive jitter on clock buffer outputs. The ZL40222 is equipped with a low drop out (LDO) power regulator and on-chip bulk capacitors to minimize additive jitter due to power supply noise. The on-chip regulation, recommended power supply filtering, and good PCB layout all work together to minimize the additive jitter from power supply noise.3.5.2 Power supply filteringFor optimal jitter performance, the ZL40222 should be isolated from the power planes connected to its power supply pins as shown in Figure 19.•10 µF capacitors should be size 0603 or size 0805 X5R or X7R ceramic, 6.3 V minimum rating•0.1 µF capacitors should be size 0402 X5R ceramic, 6.3 V minimum rating•Capacitors should be placed next to the connected device power pinsFigure 19 - Decoupling Connections for Power Pins3.5.3 PCB layout considerationsThe power supply filtering shown in Figure 19 can be implemented either as a plane island, or as a routed power topology with equal performance.4.0 AC and DC Electrical CharacteristicsAbsolute Maximum Ratings*Parameter Sym.Min.Max.Units 1Supply voltage V DD_R-0.5 4.6V 2Voltage on any digital pin V PIN-0.5V DD V 3Soldering temperature T260 °C 4Storage temperature T ST-55125 °C 5Junction temperature T j125 °C 6Voltage on input pin V input V DD V 7Input capacitance each pin C p500fF * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.* Voltages are with respect to ground (GND) unless otherwise statedRecommended Operating Conditions*Characteristics Sym.Min.Typ.Max.Units 1Supply voltage 2.5 V mode V DD25 2.375 2.5 2.625V 2Supply voltage 3.3 V mode V DD33 3.135 3.3 3.465V 3Operating temperature T A-402585°C* Voltages are with respect to ground (GND) unless otherwise statedDC Electrical Characteristics - Current ConsumptionCharacteristics Sym.Min.Typ.Max.Units Notes 1Supply current LVDS drivers - loadedI dd_load110mA(all outputs are active)DC Electrical Characteristics - Inputs and Outputs - for 2.5/3.3 V SupplyCharacteristics Sym.Min.Typ.Max.Units Notes1CMOS control logic high-level input V CIH0.7*V DD V2CMOS control logic low-level input V CIL0.3*V DD VI IL1µA V I = V DD or 0 V 3CMOS control logic Input leakagecurrent4Differential input voltage difference V ID0.251V5Differential input common modeV CM 1.1 1.6V for 2.5 V voltageV CM 1.1 2.0V for 3.3 V6Differential input common modevoltage7LVDS output differential voltage*V OD0.250.300.40V8LVDS output common mode V CM 1.1 1.25 1.375V* The VOD parameter was measured from 125 MHz to 750 MHz.AC Electrical Characteristics* - Inputs and Outputs (see Figure 21) - for 2.5/3.3 V supply.Characteristics Sym.Min.Typ.Max.Units Notes 1Maximum Operating Frequency1/t p750MHz2Input to output clock propagation delay t pd012ns3Output to output skew t out2out80150ps4Part to part output skew t part2part120300ps5Output clock Duty Cycle degradation t PWH/ t PWL-505Percent6LVDS Output slew rate r sl0.55V/ns7Reference transition time t switch23usFigure 20 - Differential Voltage Parameter* Supply voltage and operating temperature are as per Recommended Operating ConditionsInputt Pt PWL t pdt PWHOutputFigure 21 - Input To Output TimingAdditive Jitter at 2.5 V*Output Frequency (MHz)Jitter MeasurementFilterTypical RMS (fs)Notes112512 kHz - 20 MHz 2612212.512 kHz - 20 MHz 2493311.0412 kHz - 20 MHz 215442512 kHz - 20 MHz 189550012 kHz - 20 MHz 2016622.0812 kHz - 20 MHz 194775012 kHz - 20 MHz205Additive Jitter at 3.3 V*Output Frequency (MHz)Jitter MeasurementFilterTypical RMS (fs)Notes112512 kHz - 20 MHz 2682212.512 kHz - 20 MHz 2513311.0412 kHz - 20 MHz 229442512 kHz - 20 MHz 220550012 kHz - 20 MHz 1976622.0812 kHz - 20 MHz 194775012 kHz - 20 MHz2035.0 Performance Characterization*The values in this table were taken with an approximate slew rate of 0.8 V/ns.*The values in this table were taken with an approximate slew rate of 0.8 V/ns.Additive Jitter from a Power Supply Tone*Carrier frequencyParameterTypicalUnitsNotes125MHz 25 mV at 100 kHz 37fs RMS 750MHz25 mV at 100 kHz40fs RMS* The values in this table are the additive periodic jitter caused by an interfering tone typically caused by a switching power supply. For this test, measurements were taken over the full temperature and voltage range for V DD = 3.3 V. The magnitude of the interfering tone is measured at the DUT.6.0 Typical BehaviorTypical Waveform at 155.52 MHzV OD vs FrequencyPower Supply Tone Frequency versus PSRRPower Supply Tone Magnitude versus PSRRPropagation Delay versus TemperatureNote:This is for a single device. For more details, see thecharacterization section.7.0 Package CharacteristicsThermal DataParameter Symbol Test Condition Value UnitJunction to Ambient Thermal Resistance ΘJA Still Air1 m/s2 m/s 37.433.131.5o C/WJunction to Case Thermal Resistance ΘJC24.4o C/W Junction to Board Thermal Resistance ΘJB19.5o C/W Maximum Junction Temperature*T jmax125o C Maximum Ambient Temperature T A85o C8.0 Mechanical Drawing© 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense and security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world’s standard for time; voice processing devices; RF solutions; discrete components; security technologies and scalable anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif. and has approximately 3,400 employees globally. Learn more at .Microsemi Corporate Headquarters One One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (800) 713-4113Outside the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996E-mail: ***************************Information relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively “Microsemi”) is believed to be reliable. However, Microsemi assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Microsemi or licensed from third parties by Microsemi, whatsoever. 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基于开关电容放大器原理的微小电容检测电路

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文档下载后可定制修改，请根据实际需要进行调整和使用，谢谢!本店铺为大家提供各种类型的实用资料，如教育随笔、日记赏析、句子摘抄、古诗大全、经典美文、话题作文、工作总结、词语解析、文案摘录、其他资料等等，想了解不同资料格式和写法，敬请关注!Download tips: This document is carefully compiled by this editor. I hope that after you download it, it can help you solve practical problems. The document can be customized and modified after downloading, please adjust and use it according to actual needs, thank you! In addition, this shop provides you with various types of practical materials, such as educational essays, diary appreciation, sentence excerpts, ancient poems, classic articles, topic composition, work summary, word parsing, copy excerpts, other materials and so on, want to know different data formats and writing methods, please pay attention!基于开关电容放大器原理的微小电容检测电路在现代电子技术中，微小电容的检测和测量一直是一个重要的课题。

试述微小电容的测量方法及测量电路系统设计

的精确测量。这种方法是把被测电容（可有漏导）放在一个桥臂，可调的参考阻抗放在相邻的另一个桥臂，二桥臂分别接到频率相同、电压相同的两个信号源上。调节参考阻抗使桥路平衡，则被测桥臂中的阻抗与参考阻抗共轭相等。该方法的主要优点为：选用器件少，电路简单，易于小型化。其缺点主要为：由于远离平衡位置时非线性较大，输出阻抗很高，输出电压很小。２测量电路系统设计２１微电容测量电路设计要求．在ＥＴ电容测量中，电容传感器内充以两相介质时，两电极间互Ｃ电容的变化量是流体相含率及其空间分布的函数，而相含率变化所引起的互电容变化量一般为０１１皮法（ｆ．．～０ｐ）左右，且不同的电极对之间的电容量相差很大，相邻电极对问的电容比相对电极对问的电容要大数百倍，同时杂散电容远远大于待测电容，因此应用于ＥＴ的电容Ｃ检测电路应当具有以下特点：１）低漂移、能抑制杂散电容、消除损耗电导的影响；２）高分辨率，最小可分辨信号０ｆ；３＂Ｆ）线性度好，非．１线性误差 ≤ｌ）高信噪比，信噪比≥ｌ０Ｂ）测量范围足够宽，Ｏ；４０ｄ；５
能测量微小电容的变化。关键词：电容层析成像；小电容；量电路微测
电容式传感器是将被测量的变化转换成电容量变化的一种装置。电容式传感器具有结构简单、分辨力高、工作可靠、动态响应快、可非接触测量，并能在高温、辐射和强烈振动等恶劣条件下工作等优点已在工农业生产的各个领域得到广泛应用。其中微小电容测量是关键技术之一。这里介绍了最常用的四种微小电容检测方法，设计了基于交流激励的电容测量电路，分析了电路的工作原理，给出了实验结果；该电路的特点是动态测量范围宽，灵敏度高，可灵活应用于不同的应用场合。

基于高精度的微弱电容检测电路的设计

基于高精度的微弱电容检测电路的设计陈莉【摘要】针对球型电容位移传感器电容量变化微小,极板结构材质特殊,尺寸极其微小,通过电容传感器测量的变化量易受周围环境中寄生电容的干扰问题,提出了基于高精度的微弱电容检测电路系统的方法.该方法首先通过理论静电场出发,建立球型电容传感器在导体球内外表面的电容模型.然后在该模型基础上,对不同的待测目标进行电容信号的测量,并通过对测量结果的信号进行仿真分析.从仿真结果分析了微弱电容的大小,最后设计的微弱电容检测系统的检测范围可达0～1.5 pF,分辨率优于0.36 fF.从而使得电容传感器实现5 nm的位移分辨率,且通用性与稳定性均较好,实验也验证了该检测电路方案的有效性.【期刊名称】《电子设计工程》【年(卷),期】2018(026)015【总页数】5页(P131-135)【关键词】电容传感器;微弱电容检测;高精度【作者】陈莉【作者单位】陕西国防工业职业技术学院陕西西安710302【正文语种】中文【中图分类】TN721.5随着加工工艺以及新型材料不断地被开发，传统的电容位移传感器的缺点正在被逐步克服，新型的电容位移传感器的精度与稳定性也在逐步提高。

但我国电容位移传感器相比国际上的水平仍属于滞后状态，国际上的电容位移传感器具有分辨率高、测量范围广、频率响应快等优势[1]。

分析其原因可发现，电容位移传感器的主要组成部件为微弱电容检测系统和探测头组成。

目前，国内对于电容位移传感器的微弱电容检测系统的设计还处于滞后状态，这是导致位移传感器滞后的主要原因。

因此，目前国内需要更进一步的研究微弱电容检测系统的设计。

目前，电容位移传感器的检测系统设计正在向高精度[2]和小型化趋势发展。

尤其对于微弱电容测量领域，比如纳米级高精度电容位移传感器、电容层析成像等领域中，电容的值在零点几pF左右，属于微弱电容测量。

对于微弱电容测量的电路要求分辨率较高，故传统的电容检测技术根本无法实现该微弱电容的测量[3]。

微小电容测量电路

微小电容测量电路微小电容测量电路电容式传感器是将被测量的变化转换成电容量变化的一种装置。

电容式传感器具有结构简单、分辨力高、工作可靠、动态响应快、可非接触测量，并能在高温、辐射和强烈振动等恶劣条件下工作等优点已在工农业生产的各个领域得到广泛应用。

例如在气力输送系统中，可以用电容传感器来获得浓度信号和流动噪声信号，从而测量物料的质量流量；在电力系统中，采用电容传感器在线监测电缆沟的温度，确保使用的安全；由英国曼彻斯特科学与技术大学(UMIST)率先开发的电容层析成像(ECT)技术是解决火电厂煤粉输送风-粉在线监测等气固两相流成分和流量检测的有效途径，其中微小电容测量是关键技术之一。

电容传感器的电容变化量往往很小。

结果电容传感器电缆杂散电容的影响非常明显。

特别在电容层析成像系统中被测电容变化量可达0.01pF，属于微弱电容测量，系统中总的杂散电容(一般大于100 pF)远远大于系统的电容变化值，且杂散电容会随温度、结构、位置、内外电场分布及器件的选取等诸多因素的影响而变化，同时被测电容变化范围大。

因此微小电容测量电路必须满足动态范围大、测量灵敏度高、低噪声、抗杂散性等要求。

1 充/放电电容测量电路充/放电电容测量电路基本原理如图1所示。

由CMOS开关S1，将未知电容Cx充电至Ve，再由第二个CMOS 开关S2放电至电荷检测器。

在一个信号充/放电周期内从Cx传输到检波器的电荷量Q=Ve·Cx，在时钟脉冲控制下，充/放电过程以频率f=1/T重复进行，因而平均电流Im=Ve·Cx·f，该电流被转换成电压并被平滑，最后给出一个直流输出电压Vo=Rf·Im=Rf·Ve·Cx·f(Rf为检波器的反馈电阻) 。

充/放电电容测量电路典型的例子为差动式直流充放电C/V转换电路，如图2所示。

Cs1和Cs2分别为源极板和检测极板与地间的等效杂散电容(通过分析可知，它们不影响电容Cx的测量)。

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中北大学
毕业设计（论文）任务书
学院、系：信息与通信工程学院
专业：通信工程
学生姓名：学号：
设计(论文)题目：微小差分电容检测电路设计
电路设计
起迄日期: 2006年3月1日~2006年6月15日
设计(论文)地点:电子工程系
指导教师:
系主任:
发任务书日期: 2006年3月1日
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此任务书应在毕业设计（论文）开始前一周内填好并发给学生；
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如“2004年3月15日”或“2004-03-15”。

毕业设计（论文）任务书
毕业设计（论文）任务书。

微小差分电容检测电路设计-任务书