VHDL双向十进制加减法计数器(代码和截图)

Clk上升沿有效,we=0，dir=0 此时为加法操作

Clk上升沿有效，we=0,dir=1 此时为减法操作

We=1,需要置初值，上升沿有效，dir=1，减法操作

We=0,dir任意，保持

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.ALL;

entity vh is

port

(

clk : in std_logic;

dir : in std_logic;

we : in std_logic;

d : in std_logic_vector(3 downto 0);

co : out std_logic

);

end entity;

architecture rtl of vh is

SIGNAL temp:std_logic_vector(3 downto 0); begin

process (clk)

begin

if(we='1')then

temp<=d;

elsif(clk'event and clk='1')then

if(dir='0')then

if(temp<9)then

temp<=temp+'1';

co<='0';

else

temp<="0000";

co<='1';

end if;

elsif(dir='1')then

if(temp>0)then

temp<=temp-'1';

co<='0';

else

temp<="1001";

co<='1';

end if;

end if;

end if;

end process;

end rtl;