DRAM内存颗粒测试简介.pptx

• Speed & AC Timing Test
Speed • Full Speed (DDR3 @1600MHz and above), Advantest T5503 + 256DUT HiFix Test
• Marking Ball Scan Visual Inspection Baking Vacuum Pack
DRAM Advantest Test
1. DC Test
Open/Short test Leakage test IDD test
2. Functional Test (Core Test)
Different parameter & Pattern for each function To check DRAM can operate functionally
Basic Test Signal
Digital Waveform Elements
• Logic • Voltage • Timing
Typical DRAM Final Test Flow
• MBT (Monitor Burn in Test): Stress to screen out Early Failures • TBT (Test Burn in Test): Long time pattern test
3. Speed Test
Timing test @ different speed grade
DC Test
VCC
DC Test Method: a) ISVM:
I Source V Measure
VCC
b) VSIM V Source I Measure
DC Test – Open Short
Purpose:
• Check connection between pins and test fixture • Check if pin to pin is short in IC package • Check if pin to wafer pad has open in IC package • Check if protection diodes work on die • It is a quick electrical check to determine if it is safe to apply power • Also called Continuity Test
Introduction to DRAM Testing
--- DRAM inside team --- 2015.May
Agenda
Basis of Testing Typical DRAM Testing Flow Burn-in DC Test (Open/Short, Leakage, IDD) Functional Test & Test Pattern Speed Test
• Voltage guard band • Temperature guard band • Timing guard band • Complex test pattern
Collect data for design & process improvement
• Quality • Reliability • Cost • Efficiency
Burn-in • Very Low Speed(5-20MHz), High Parallel Test (10-20Kpcs/oven), Low Cost
Core Test
• DC Test • Functional Test • Low Speed (DDR3 @667MHz), Typical tester Advantest T5588 + 512DUT HiFix
Backend
DRAM Burn-in (MBT)
MBT is to stress IC and screen out early failures
High Temperature Stress (5degC) High Voltage Stress Stressful Pattern
New
BI
product
Mature product
Failure Rate
Infant Mortality
Operation Time Normal Life Worn out
Bath Curve
DRAM Burn-in (TBT)
TBT is for long time test patterns
Multiple temperature tested (e.g. 88’C, 25’C, -10’C) Long test time at low speed Patterns cover all cell arrays No Stressful condition High parallel test count, low cost Both MBT and TBT does NOT test DC (Ando Oven)
DRAM Manufacture
Wafer
Assembly
Final Testing
Final Product
Why Testing?
To screen out defect
• Wafer defect • Assembly defect
Make sure product meet spec of customer
IC Test Methodology
Power Supply PPS
IC Tester
Input DUT*
Driver
* DUT = Device Under Test
Comparator Output
Testing of a DUT: 1. To connect PPS, Driver, Comparator & GND. 2. To apply power to DUT. 3. To input data to DUT (Address, Control Command, Data) 4. To compare output with “expect value” and judge PASS/FAIL