半加器和全加器的设计

component or23
port (a,b :in std_logic;
c: out std_logic);
end component;
signal x:std_logic_vector(0 to 2);
begin
u1: h_adder1 port map(a,b,x(1),x(0));
u2: h_adder1 port map(x(1),cin,sum,x(2));
entity count10 is
port(clk,r,s :in std_logic;
data:in std_logic_vector(3 downto 0);
co :out std_logic;
q:buffer std_logic_vector(3 downto 0));
end count10;
u3: or23 port map(a=>x(0),b=>x(2),c=>cout);
end arch;
运行结果：
方法二：
运行结果：
实验二.四选一数据选择器的设计
1用case语句：
library ieee;
use ieee.std_logic_1164.all;
entity mux4_1ais
port(A,B,C,D :in std_logic_vector(3 downto 0);
entity dswq is
port(clk,dir : in std_logic;
q : buffer std_logic_vector(3 downto 0));
end;
architecture arch of dswq is
begin
process(clk,q,dir)
begin
if clk'event and clk ='1'
B when "01",
C when "10",
D when "11",
"ZZ"when others;
end arch;
运行结果：
4，用when语句设计：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
then if dir='0'
then q<=q+1;
else q<=q-1;
end if;
end if;
end process;
end arch;
运行结果：
异步清零，同步置数的同步8421BCD码计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
begin
s<=a xor b;c<=a and b;
end architecture one;
运行结果：
方法二：
运行结果：
2，全加器的设计
方法一：
library ieee;
use ieee.std_logic_1164.all;
entity f_adder1 is
port(a,b,cin :in std_logic;
end arch;
用with语句设计：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux4_1cis
port(A,B,C,D :in std_logic_vector(3 downto 0);
architecture arch of count10 is
begin
co<='1' when(q="1001")else '0';
process(clk,r)
begin
if(r='0')then q<="0000";
elsif (clk'event and clk='1') then
if(s='1')then q<=data;
sel :in std_logic_vector(1 downto 0);
q :out std_logic_vector(3 downto 0)
);
end mux4_1a;
architecture arch of mux4_1ais
begin
process(A,B,C,D,sel)
begin
case sel is
when "00"=> q<=A;
when "01"=> q<=B;
when "10"=> q<=C;
when "11"=> q<=D;
when others=> null;
end case;
end process;
end arch;
运行结果：
2，用if语句设计：
library ieee;
use ieee.std_logic_1164.all;
sum,cout :out std_logic);
end entity f_adder1;
architecture arch of f_adder1 is
component h_adder1
port( a,b :in std_logic;
s,c :out std_logic);
end component;
实验计，
方法一
library ieee ;
use ieee.std_logic_1164.all;
entity h_adder1 is
port(a,b :in std_logic;
c,s :out std_logic);
end entity h_adder1;
architecture one of h_adder1 is
entity mux4_1d is
port(A,B,C,D :in std_logic_vector(3 downto 0);
sel :in std_logic_vector(1 downto 0);
q :out std_logic_vector(3 downto 0)
);
end mux4_1d;
architecture arch of mux4_1d is
begin
process(A,B,C,D,sel)
begin
IF sel ="00" then q<=A;
elsif sel = "01" then q<=B;
elsif sel = "10" then q<=C;
elsif sel = "11" then q<=D;
end if
end process;
sel :in std_logic_vector(1 downto 0);
q :out std_logic_vector(3 downto 0)
);
end mux4_1c;
architecture arch of mux4_1cis
begin
with sel select
q<=A when "00",
elsif(q=9)then q<="0000";
else q<=q+1;
end if;
end if;
end process;
end arch;
运行结果：
entity mux4_1b is
port(A,B,C,D :in std_logic_vector(3 downto 0);
sel :in std_logic_vector(1 downto 0);
q :out std_logic_vector(3 downto 0)
);
end mux4_1b;
architecture arch of mux4_1b is
begin
q<=A when sel="00" else
B when sel="01" else
C when sel="10" else
D;
end arch;
运行结果：
实验三,可逆计数器的设计
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;