XST Synthesis

module, use the INST or NET keywords:
BEGIN MODEL entity_name INST instance_name constraint_name = constraint_value; NET signal_name constraint_name = constraint_value; END;
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Language Templates

Two methods to open templates:
– Language Icon – Edit -> Language Templates

Language Templates provide common templates for designs:
-uc -iuc
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XCF - MODEL
• To apply a constraint to the entire entity or module, use the following
syntax:
MODEL entity_name constraint_name = constraint_value;
Note: If a constraint is applied to an entity or module, the constraint will be applied to each instance of the entity/module
• To apply constraints to specific instances or signals within an entity or
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What are Constraints?

Writing constraints is a method of communicating your design and performance objectives to the synthesis tools and implementation tools
– Translates V, VHD, SCH files into an industry standard format EDIF file
Netlist Implement BIT File
• Step 3: Implement design (netlist)
– Translate, Map, Place & Route
– Optimization Goal (speed/area) – Optimization Effort (normal/high) – Synthesis Constraints File – – – – –
• Any text file Use Synthesis Constraints File Global Optimization Goal Generate RTL Schematic Write Timing Constraints Verilog 2001
To Implementation Tools
Synthesis Report File
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Main Synthesis Steps
HDL
HDL Parsing Identification of language syntax errors HDL Synthesis Macro recognition, FSM extraction, resource sharing Low Level Optimization Macro implementation, timing optimization, LUT mapping, register replication
.NGC .LOG
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ISE GUI

Synthesis options
– Global synthesis and optimization goal and effort

HDL options
– Family-specific inference and optimization opFPGA
– Download BIT file into FPGA
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XST Synthesis in Project Navigator


Module/entity selected in Sources window treated as “top” XST-specific processes
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Device Support
XST provides technology specific optimization for:

FPGAs
– – – – – –

CPLDs
– -
Virtex Virtex-E Virtex-II Virtex-II Pro Spartan-II Spartan-IIE
XST Synthesis
FPGA Design Workshop
Objectives
After completing this module, you will be able to…

List the synthesis options for XST Describe how to insert code from the Language Template Specify various methods for entering constraints
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XST Constraints
• XST will accept synthesis constraints through the Xilinx Constraints File (XCF)
– Do not confuse this with the User Constraints File (UCF), which contains implementation constraints for the Xilinx tools
• When using an XCF file, specify the file in the Synthesis Options tab
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XST Constraints
• To quickly enable or disable the use of a constraint file by XST, you can check or uncheck the Use Synthesis Constraint File menu
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XST: HDL Options
• Set family-specific inference and optimization options
– – – – – – – –
FSM Encoding Algorithm RAM/ROM/Multiplexer Extraction RAM/Multiplexer Style Decoder/Priority Encoder Extraction Shift Register/Logical Shifter Extraction XOR Collapsing Resource Sharing Complex Clock Enable Extraction
– Component instantiation – Language templates – Synthesis templates
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Language Templates




To use template, be sure that an HDL source file is already opened Place cursor at the location for the code to be entered In the Language Template GUI, rightclick on the template you wish to use Select “Use in…” Be sure the appropriate file name is listed

Xilinx Specific options
– Specific low-level implementation and optimization algorithms
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XST: Synthesis Options
• Set global synthesis, optimization goal, and effort
– Synthesize
• View Synthesis Report • Analyze Hierarchy • Check Syntax
AM2910 as top-level

XST-specific properties
– Synthesis Options – HDL Options – Xilinx Specific Options
-
XC9500 XC9500XL XC9500XV CoolRunner CoolRunner-II
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XST Flow
VHDL Verilog
Synthesis Technology Specific Optimization