AD精选高速数模转换器中文

合集下载

AD7520中文资料

数模(D/A)转换器基础知识在电子技术中，模拟量和数字量的相互转换非常重要。

例如，用电子计算机对生产过程进行控制时，必须先将模拟量转换成数字量，才能送到计算机中去进行运算和处理；然后又要将处理得出的数字量转换为模拟量，才能对被控制的模拟量进行控制。

另外，在数字仪表中，也必须将被测的模拟量转换为数字量才能实现数字显示。

能将模拟量转换为数字量的电路称为模数转换器，简称A/D转换器或ADC；能将数字量转换为模拟量的电路称为数模转换器，简称D/A转换器或DAC。

因此，模数转换器和数模转换器是沟通模拟电路和数字电路的桥梁，也可称之为两者之间的接口。

实际上，在数据传输系统、自动测试设备、医疗信息处理、电视信号的数字化、图像信号的处理和识别、数字通信和语音信息处理等方面都离不开模数转换器和数模转换器。

数模转换器是将一组输入的二进制数转换成相应数量的模拟电压或电流输出的电路。

因为数字量是用二进制代码按数位组合起来表示的，对于有权码，每位代码都有一定的权。

所以，为了将数字量转换成模拟量，必须将每一位的代码按其权的大小转换成相应的模拟量，然后将代表各位的模拟量相加，所得的总模拟量就与数字量成正比，这样便实现了从数字量到模拟量的转换。

这就是组成数模转换器的基本指导思想。

数模转换器根据工作原理基本上可以分为二进制权电阻网络数模转换器和T形电阻网络数模转换器(包括倒T形电阻网络数模转换器)两大类。

权电阻网络数模转换器的优点是电路结构简单，可适用于各种有权码。

缺点是电阻阻值范围太宽，品种较多。

要在很宽的阻值范围内保证每个电阻都有很高的精度是极其困难的。

因此，在集成数模转换器中很少采用权电阻网络。

一、倒T形电阻网络数模转换器图11-1所示的是一个四位二进制数倒T形电阻网络数模转换器的原理图。

由图11-1可以看出，这种数模转换器是由倒T形电阻转换网络、模拟电子开关及运算放大器组成。

倒T形电阻网络也是由R和2R两种阻值的电阻构成的。

AD介绍

积分非线性误差（DNL）：指的是实际步宽和 1LSB 理想值之间的差值。如果 DNL 超过了 1LSB，转换器可能是非单调的。这就意味着当输入幅度增加的情况下，输出幅度反而变小。也有可能丢失编码， 2n 个二进制编码中的一个或多个将永远不会输出。微分非线性误差（INL）：实际转换函数和理想直线的偏差。理想直线普遍采用的定义是增益和偏置误差被消除的前提下，连接函数端点之间的一条直线。偏离量是按照转换函数从一个步长到下一个步长来度量。动态误差：表征 ADC 参数表征 ADC 电路在动态环境下的性能，也就是说输入信号是时间的函数。动态特性比表征 ADC 静态特性复杂得多，其动态特性参数主要包括信噪比（SNR）、信噪谐波比（SINAD）、有效位数（ENOB）、总谐波失真（THD）、无杂散动态范围（SFDR）、满功率带宽（FPBW）、孔径误差等。在实际中，由于静态误差和动态误差的存在，即使 N 位的 ADC 的外围电路引入的误差可以忽略不计，其有效位数 ENOB 往往是小于 N ，且从芯片制作工艺的角度而言，同样为 N 位的 ADC，采样率不同，芯片类型（内部实现结构）不同，误差的影响也不同。在表 2 中比较了 ADI 公司的几款 16 位 ADC 的性能。
ADC 的误差：
静态误差：在转换直流信号时影响转换器精度的误差，可以由偏置误差、增益误差、积分非线性误差、微分非线性误差描述。偏置误差：标准偏置点与实际偏置点之间的差值。当数字输出是零时，偏置点是步长的中间值。这种误差是以同样的值影响所有的编码并通过修正处理过程来补偿，若不能修正，这种误差是指零尺度误差。增益误差：在偏置误差被修正为零后，转换函数标准增益点和实际增益点之间的误差。当数字输出是全标度时增益点是步长中间值。这种误差表示实际转换函数和理想转换函数斜率的差值以及每一步长中相应的同一百分比误差，可以通过修正的方法调整到零。

AD9248 中文资料

AD9248 概述AD9248是一款双核、3 V、14位、20/40/65 MSPS模数转换器（ADC），集成了两个高性能采样保持放大器和一个基准电压源。

AD9248采用多级差分流水线架构，内置输出纠错逻辑，在最高65 MSPS数据速率时可提供14位精度，并保证在整个工作温度范围内无失码。

AD9248采用先进的CMOS工艺制造，提供节省空间的64引脚LQFP封装，与AD9238引脚兼容，额定温度范围为-40°C至+85°C工业温度范围。

AD9248 特性集成式双核14位模数转换器3 V单电源供电（2.7 V至3.6 V）信噪比（SNR）：71.6 dBc（至Nyquist频率，AD9248-65）无杂散动态范围（SFDR）：80 dBc（至Nyquist频率，AD9248-65）低功耗：600 mW（65 MSPS）差分输入、500 MHz 3dB带宽出色的抗串扰特性：大于85 dB片内基准电压源和SHA灵活的模拟输入范围：1 Vp-p至2 Vp-p数据格式：偏移二进制或二进制补码时钟占空比稳定器与AD9238引脚兼容AD9248是一种基于流水线型的ADC，这种流水线型结构的特点是由一系列标志1级、2级等各级构成。

每级的结构是相同的,包含一个采样保持电路(S/H) 、一个子模数转换电路(ADC)和一个乘积数模转换器(MDAC)电路[1]。

AD9248的主要引脚的功能包括：VIN+、VIN-是模拟差分信号输入端；D0～D13是数据输出端；OEA、OEB分别是A、B两通道数据输出使能位；PDWN_A、PDWN_B分别是两通道的Power-Down功能选择位,为0 时, 使能通道, 为1时, 关闭通道；DFS是输出数据格式选择位，为0时, 数据输出格式为偏移的二进制,为1时，数据输出格式为二进制补码格式；OTR_A、OTR_B是两通道的溢出标志位；MUX_SELECT是数据复用模式选择位,该管脚接高电平时，则可保证两通道数据分别从各自通道输出,该管脚接时钟时,两通道数据将复用输出数据端口, 此时数据输出速率是采样速率的两倍。

(最新整理)AD转换器的介绍

AD转换器的介绍编辑整理：尊敬的读者朋友们：这里是精品文档编辑中心，本文档内容是由我和我的同事精心编辑整理后发布的，发布之前我们对文中内容进行仔细校对，但是难免会有疏漏的地方，但是任然希望（AD转换器的介绍）的内容能够给您的工作和学习带来便利。

同时也真诚的希望收到您的建议和反馈，这将是我们进步的源泉，前进的动力。

本文可编辑可修改，如果觉得对您有帮助请收藏以便随时查阅，最后祝您生活愉快业绩进步，以下为AD转换器的介绍的全部内容。

在仪器仪表系统中，常常需要将检测到的连续变化的模拟量如：温度、压力、流量、速度、光强等转变成离散的数字量，才能输入到计算机中进行处理.这些模拟量经过传感器转变成电信号（一般为电压信号）,经过放大器放大后，就需要经过一定的处理变成数字量。

实现模拟量到数字量转变的设备通常成为模数转换器（ADC),简称A/D.随着集成电路的飞速发展,A/D转换器的新设计思想和制造技术层出不穷。

为满足各种不同的检测及控制需要而设计的结构不同、性能各异的A/D转换器应运而生.下面讲讲A/D转换器的基本原理和分类根据A/D转换器的原理可将A/D转换器分成两大类。

一类是直接型A/D转换器，将输入的电压信号直接转换成数字代码,不经过中间任何变量；另一类是间接型A/D转换器，将输入的电压转变成某种中间变量（时间、频率、脉冲宽度等），然后再将这个中间量变成数字代码输出。

尽管A/D转换器的种类很多，但目前广泛应用的主要有三种类型：逐次逼近式A/D转换器、双积分式A/D 转换器、V/F变换式A/D转换器.另外，近些年有一种新型的Σ—Δ型A/D转换器异军突起，在仪器中得到了广泛的应用。

逐次逼近式A/D转换器的基本原理是：将待转换的模拟输入信号与一个推测信号进行比较，根据二者大小决定增大还是减小输入信号,以便向模拟输入信号逼进。

推测信号由D/A转换器的输出获得，当二者相等时，向D/A转换器输入的数字信号就对应的时模拟输入量的数字量。

模数转换器

A/D转换器模数转换器即A/D转换器，或简称ADC，通常是指一个将模拟信号转变为数字信号的电子元件。

通常的模数转换器是将一个输入电压信号转换为一个输出的数字信号。

由于数字信号本身不具有实际意义，仅仅表示一个相对大小。

故任何一个模数转换器都需要一个参考模拟量作为转换的标准，比较常见的参考标准为最大的可转换信号大小。

而输出的数字量则表示输入信号相对于参考信号的大小。

模数转换器最重要的参数是转换的精度，通常用输出的数字信号的位数的多少表示。

转换器能够准确输出的数字信号的位数越多，表示转换器能够分辨输入信号的能力越强，转换器的性能也就越好。

A/D转换一般要经过采样、保持、量化及编码4个过程。

在实际电路中，有些过程是合并进行的，如采样和保持，量化和编码在转换过程中是同时实现的。

一般来说，AD比DA贵，尤其是高速的AD，因为在某些特殊场合，如导弹的摄像头部分要求有高速的转换能力。

一般那样AD要上千美元。

还有通过AD的并联可以提高AD的转换效率，多个AD同时处理数据，能满足处理器的数字信号需求了。

模数转换过程包括量化和编码。

量化是将模拟信号量程分成许多离散量级，并确定输入信号所属的量级。

编码是对每一量级分配唯一的数字码，并确定与输入信号相对应的代码。

最普通的码制是二进制，它有2n个量级（n为位数）,可依次逐个编号。

模数转换的方法很多，从转换原理来分可分为直接法和间接法两大类。

直接法是直接将电压转换成数字量。

它用数模网络输出的一套基准电压，从高位起逐位与被测电压反复比较，直到二者达到或接近平衡（见图）。

控制逻辑能实现对分搜索的控制，其比较方法如同天平称重。

先使二进位制数的最高位Dn-1＝1，经数模转换后得到一个整个量程一半的模拟电压VS，与输入电压Vin 相比较，若V in>VS,则保留这一位；若V in<V in，则Dn-1＝0。

然后使下一位Dn-2＝1,与上一次的结果一起经数模转换后与V in相比较,重复这一过程，直到使D0＝1，再与V in相比较,由V in>VS还是V in<V来决定是否保留这一位。

几款高速数模转换芯片的中文资料

AD9221、AD9223和AD9220均为新一代高性能、12位模数转换器，采用单电源供电。

每款器件都具有真12位线性度和温度漂移性能1，以及11.5位或更佳的交流性能2。

AD9221/AD9223/AD9220均采用相同的接口选项、封装和引脚排列。

因此，该产品系列可根据性能、采样速率和功耗，向上或向下选择器件型号。

这些器件的额定采样速率和功耗各不相同，体现在各自基于频率的动态性能上。

AD9221/AD9223/AD9220采用高速、低成本的单CMOS工艺及新颖的架构，分辨率和速度均达到现有混合单芯片方案的水平，而功耗与成本却低得多。

每款器件均为完整的单芯片ADC，内置片内高性能、低噪声采样保持放大器和可编程基准电压源。

也可以选用外部基准电压，以满足应用的直流精度与温度漂移要求。

这些器件采用多级差分流水线架构，内置数字输出纠错逻辑，在额定数据速率时可提供12位精度，并保证在整个工作温度范围内无失码。

AD9221/AD9223/AD9220的输入非常灵活，能够与成像、通信、医疗和数据采集系统实现轻松接口。

真差分输入结构使单端输入和差分输入采样接口均支持各种输入范围。

采样保持（SHA）放大器既适用于在连续通道中切换满量程电平的多路复用系统，也适合采用最高Nyquist速率及更高的频率对单通道输入进行采样。

此外，AD9221/AD9223/AD9220特别适合采用IF下变频的通信系统，因为在差分输入模式下，SHA可以实现远超过其额定Nyquist频率2的出色动态性能。

采用一个单时钟输入来控制所有内部转换。

数字输出数据格式为标准二进制。

超量程（OTR）信号表示溢出状况，可由最高有效位来确定是下溢还是上溢。

特点和优势∙单芯片12位模数转换器产品系列∙该系列包括：AD9221、AD9223和AD9220∙灵活的采样速率：1.5 MSPS、3.0 MSPS和10 MSPS∙低功耗：59 mW、100 mW和250 mW∙+5 V单电源∙积分非线性误差：0.5 LSB∙微分非线性误差：0.3 LSB∙信噪比（SNR）：70 dB；无杂散动态范围（SFDR）：86 dB∙超量程指示∙28引脚SOIC和28引脚SSOP封装∙Resolution (Bits): 12bit∙# Chan: 1∙Sample Rate: 10MSPS∙Interface: Par∙Analog Input Type: Diff-Uni,SE-Uni∙Ain Range: 2 V p-p,5V p-p∙ADC Architecture: Pipelined∙Pkg Type: SOIC,SOPAD9225是一款单芯片、12位、25 MSPS模数转换器（ADC），采用单电源供电，内置一个片内高性能采样保持放大器和基准电压源。

LED显示AD转换器中英文对照外文翻译文献

中英文资料外文翻译213Digit, LCD/LED Display, A/D Converters Abstract: The Intersil ICL7106 and ICL7107 are high performance, low power,213digit A/D converters. Included are seven segment decoders, display drivers, a reference, and a clock. The ICL7106 is designed to interface with a liquid crystal display (LCD) and includes a multiplexed backplane drive; the ICL7107 will directly drive an instrument size light emitting diode (LED) display.The ICL7106 and ICL7107 bring together a combination of high accuracy, versatility, and true economy. It features autozero to less than 10μV, zero drift of less than 1μV/℃, input bias current of 10pA (Max), and rollover error of less than one count. True differential inputs and reference are useful in all systems, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge type transducers. Finally, the true economy of single power supply operation (ICL7106), enables a high performance panel meter to be built with the addition of only 10 passive components and a display.Keyword : 213Digit LCD/LED Display A/D Converters1 Features (1)Guaranteed Zero Reading for 0V Input on All Scales(2)1pA Typical Input Current(3)True Differential Input and Reference, Direct Display Drive -LCD ICL7106, LED LCL7107(4)Low Noise - Less Than 15μVP-P(5)On Chip Clock and Reference(6)Low Power Dissipation - Typically Less Than 10mW(7)No Additional Active Circuits Required2 Detailed Description2.1 Analog SectionFigure 1 shows the Analog Section for the ICL7106 and ICL7107. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE).FIGURE 1 ANALOG SECTION OF ICL7106 AND ICL71072.2 Auto-Zero PhaseDuring auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the AZ accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10μV.2.3 Signal Integrate PhaseDuring signal integrate, the auto-zero loop is opened, the internal short is removed, and theinternal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined.2.4 De-Integrate PhaseThe final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed is: DISPLAY COUNT=⎪⎪⎭⎫ ⎝⎛REFIN V V 1000 2.5 Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity.2.6 Differential ReferenceThe reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by thereference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case.2.7 Analog COMMONThis pin is included primarily to set the common mode voltage for battery operation (ICL7106) or for any system where the input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6V. However, analog COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (>7V), the COMMON voltage will have a low voltage coefficient (0.001%/V), low output impedance (≅15Ω), and a temperature coefficient typically less than 80ppm/×℃.The limitations of the on chip reference should also be recognized, however. With the ICL7107, the internal heating which results from the LED drivers can cause some degradation in performance. Due to their higher thermal resistance, plastic parts are poorer in this respect than ceramic. The combination of reference Temperature Coefficient (TC), internal chip dissipation, and package thermal resistance can increase noise near full scale from 25μV to 80μVP-P. Also the linearity in going from a high dissipation count such as 1000 (20 segments on) to a low dissipation count such as 1111(8 segments on) can suffer by a count or more. Devices with a positive TC reference may require several counts to pull out of an over-range condition. This is because over-range is a low dissipation mode, with the three least significant digits blanked. Similarly, units with a negative TC may cycle between over-range and a non-overrange count as the die alternately heats and cools. All these problems are of course eliminated if an external reference is used.The ICL7106, with its negligible dissipation, suffers from none of these problems. Ineither case, an external reference can easily be added, as shown in Figure 2.Analog COMMON is also used as the input low return during auto-zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in some applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently tied to analog COMMON, it should be since this removes the common mode voltage from the reference system.Within the lC, analog COMMON is tied to an N-Channel FET that can sink approximately 30mA of current to hold the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is only 10μA of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal reference.FIGURE 2 USING AN EXTERNAL REFERENCE2.8 TESTThe TEST pin serves two functions. On the ICL7106 it is coupled to the internally generated digital supply through a 500Ω resistor. Thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the LCD display. Figures 3 and 4 show such an application. Nomore than a 1mA load should be applied.The second function is a “lamp test”. When TEST is pulled high (to V+) all segments will be turned on and the display should read “1888”. The TEST pin will sink about 15mA under these conditions.FIGURE 3 SIMPLE INVERTER FOR FIXED DECIMAL POINTFIGURE 4 EXCLUSIVE …OR‟ GATE FOR DECIMAL POINT DRIVE2.9 Digital SectionFigures 5 and 6 show the digital section for the ICL7106 and ICL7107, respectively. In the ICL7106, an internal digital ground is generated from a 6V Zener diode and a large P-Channel source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/sec., this is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments.Figure 6 is the Digital Section of the ICL7107. It is identical to the ICL7106 except thatthe regulated supply and back plane drive have been eliminated and the segment drive has been increased from 2mA to 8mA, typical for instrument size common anode LED displays. Since the 1000 output (pin 19) must sink current from two LED segments, it has twice the drive capability or 16mA.In both devices, the polarity indication is “on” for negative analog inputs. If IN LO and IN HI are reversed, this indication can be reversed also, if desired.FIGURE 5 ICL7106 DIGITAL SECTIONFIGURE 6 ICL7107 DIGITAL SECTION2.10 System TimingFigure 7 shows the clocking arrangement used in the ICL7106 and ICL7107. Two basic clocking arrangements can be used:1. Figure 7A. An external oscillator connected to pin 40.2. Figure 7B. An R-C oscillator using all three pins.The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and auto-zero (1000 to 3000 counts). For signals less than full scale, auto-zero gets the unused portion of reference de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used.To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 3331kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz,100kHz, 6632kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz).FIGURE 7 CLOCK CIRCUITS三位半LCD/LED 显示A/D 转换器摘要：ICL7106和ICL7107是高性能、低功耗的三位半A/D 转换电路。

AD转换器介绍

AD转换器介绍D/A 转换器是将输⼊的⼆进制数字量转换成模拟量，以电压或电流的形式输出。

D/A 转换器实质上是⼀个译码器（解码器）。

⼀般常⽤的线性D/A 转换器，其输出模拟电压uO 和输⼊数字量Dn 之间成正⽐关系。

UREF为参考电压。

uO ＝DnUREF将输⼊的每⼀位⼆进制代码按其权值⼤⼩转换成相应的模拟量，然后将代表各位的模拟量相加，则所得的总模拟量就与数字量成正⽐，这样便实现了从数字量到模拟量的转换。

D/A 转换器⼀般由数码缓冲寄存器、模拟电⼦开关、参考电压、解码⽹络和求和电路等组成。

数字量以串⾏或并⾏⽅式输⼊，并存储在数码缓冲寄存器中；寄存器输出的每位数码驱动对应数位上的电⼦开关，将在解码⽹络中获得的相应数位权值送⼊求和电路；求和电路将各位权值相加，便得到与数字量对应的模拟量。

开关Si 的位置受数据锁存器输出的数码di 控制：当di=1时，Si 将对应的权电阻接到参考电压UREF 上；当di=0时，Si 将对应的权电阻接地。

权电阻⽹络D/A 转换器的特点①优点：结构简单，电阻元件数较少；②缺点：阻值相差较⼤，制造⼯艺复杂。

2. 倒T 型电阻⽹络D/A 转换器3. 电阻解码⽹络中，电阻只有R 和2R 两种，并构成倒T 型电阻⽹络。

当di=1时，相应的开关Si 接到求和点；当di=0时，相应的开关Si 接地。

但由于虚短，求和点和地相连，所以不论开关如何转向，电阻2R 总是与地相连。

这样，倒T 型⽹络的各节点向上看和向右看的等效电阻都是2R ，整个⽹络的等效输⼊电阻为R 。

倒T 型电阻⽹络D/A 转换器的特点：①优点：电阻种类少，只有R 和2R ，提⾼了制造精度；⽽且⽀路电流流⼊求和点不存在时间差，提⾼了转换速度。

②应⽤：它是⽬前集成D/A 转换器中转换速度较⾼且使⽤较多的⼀种，如8位D/A 转换器DAC0832，就是采⽤倒T 型电阻⽹络。

三、D/A 转换器的主要技术指标1. 分辨率分辨率⽤于表征D/A 转换器对输⼊微⼩量变化的敏感程度。

AD数模转换器

目录一．设计的目的和意义----------------------------------2 二．设计的内容与要求----------------------------------2 三．系统的硬件要求-------------------------------------2 （1）所用芯片的功能介绍------------------------3（2）设计原理与硬件电路------------------------3 四．系统的软件设计-------------------------------------5 （1）软件控制流程---------------------------------5（2）程序清单---------------------------------------5 五．系统调试与运行-------------------------------------10 六．设计收获----------------------------------------------11 七．主要参考文献----------------------------------------11一．设计的目的与意义1.加深理解逐次逼近法模数转换器的特征和工作原理。

2.掌握ADC0809的接口方法以及A/D输入程序的设计和调试方法。

3.熟悉DAC0832数模转换器的特性和接口方法。

4.掌握D/A输出程序的设计和调试方法。

5.熟悉LED显示器的星系显示方法。

6.利用对以上知识点的掌握设计出一个自动温控系统。

二．设计的内容与要求利用芯片0832、芯片0809、单片机、温敏电阻或温度传感器、调温器和导线等构建一个完整的全自动的温控系统。

用程序控制0809芯片实现A/D 转换，控制0832芯片实现D/A转换，用程序控制单片机实现温控信号的分析命令的下达，线路实现模拟信号的传输。

三、系统的硬件要求（1）所用芯片的功能介绍ADC0809：ADC0809是采样分辨率为8位的、以逐次逼近原理进行模—数转换的器件。

ad9163 指标

ad9163 指标
AD9163是ADI（Analog Devices）推出的一款高性能、低功耗
的数模转换器（DAC），主要应用于通信、无线基础设施、雷达、测
试仪器等领域。

该器件具有多种指标，包括分辨率、采样率、功耗、动态范围、接口类型等。

首先，AD9163的分辨率为16位，这意味着它可以提供高精度
的数字到模拟转换。

其采样率高达12 GSPS（Giga Samples Per Second），使其能够处理高速数据并实现高频率信号的精确重建。

此外，AD9163具有较低的功耗，这对于需要长时间运行或者对功耗
有严格要求的应用非常重要。

在动态范围方面，AD9163能够提供较高的性能，确保在处理各
种信号时能够保持精确度和稳定性。

另外，它还支持多种接口类型，包括JESD204B接口，这使得它能够与各种数字信号处理器（DSP）
和微处理器进行高速数据传输。

总的来说，AD9163作为一款高性能、低功耗的数模转换器，在
多个指标上都表现出色，使其在通信、雷达等领域具有广泛的应用
前景。

希望这些信息能够对你有所帮助。

AD420中文资料

摘要：AD420是具有灵活串行数字接口的16住数模转换器，它带有SPI和Microwire总线接口，使用方便、性价比高。

介绍了AD420的引脚功能、电气特性,阐述了AD420与MSP430的接口技术，并给出了在MSP430控制下的实际应用电路及程序。

关键词：AD420；D/A转换；MSP430；电流环1 概述AD420是ADI公司生产的高精度、低功耗全数字电流环输出转换器。

AD420的输出信号可以是电流信号，也可以是电压信号。

其中电流信号的输出范围为4mA~20mA，0mA~20mA或0mA~24mA，具体可通过引脚RANGE SELECTl，RANGE SELECT2进行配置。

当需要输出电压信号时，它也能从一个隔离引脚提供电压输出，这时需外接一个缓冲放大器，可输出0V～5V，0V~10V，±5V 或±10V电压。

AD420具有灵活的串行数字接口(最大速率可达3.3 Mb/s)，使用方便、性价比高、抑制干扰能力强，非常适合用于高精度远程控制系统。

AD420与单片机的接口方式有2种：3线制和异步制。

单片机系统通过AD420可实现连续的模拟量输出。

其主要特点如下：宽泛的电源电压范围为12 V~32 V，输出电压范围为0V~-2.5 V；带有3线模式的SPI或Microwire接口，可采集连续的模拟输入信号，采用异步模式时仅需少量的信号线；数据输出引脚可将多个AD420器件连接成菊链型；上电初始化时，其输出最小值为0 mA，4 mA或O V；具有异步清零引脚，可将输出复位至最小值(0mA、4 mA或0V)；BOOST引脚可连接一个外部晶体管来吸收回路电流，降低功耗；只需外接少量的外部器件，就能达到较高的精度。

AD420采用24引脚SOIC和PDIP封装，表1是其引脚功能说明。

2 工作原理在AD420中，二阶调节器用于保持最小死区。

从调节器发出的单字节流控制开关电流源，两个连续的电阻电容装置进行过滤。

AD976模数转换器(中文)

AD976 16-Bit BicMOS 模/数转换器特性：■ 快速16-Bit ADC■ 转换速率：200kSPS-AD976A,100kSPS-AD976,■ +5V 单电源工作■ 输入范围：±10V■ 低功耗：≦100mW■ 可采用外部或内部2.5V 基准■ 高速并行接口■ 片上时钟■ 28线 DIP, SSOP or SOIC 封装绝对极限参数1模拟输入Vin ：±25VCAP:+ V ANA+0.3V to AGND2 -0.3V接地电压误差DGND,AGND1,AGND2 ±0.3V 电源电压+ VANA :7VVDIG to VANA ±7VVDIG :7V数字输入: -0.3V to VDIG+0.3V芯片功耗：PDIP(N),SOIC(R),SSOP(RS) 700mW结温：+150℃存储温度：（N,R,RS ）-65℃- +150℃引线温度范围：（焊接10秒）+300℃图1 芯片功能框图图2 DIP,SOIC 和SSOP 封装引脚配置AD976/AD976A 管脚功能描述线性误差是指从“负满量程”到“正满量程”这条直线上每个代码的偏差。

在第一码过渡之前的点是负满量程的1/2LSB。

正满量程定义一级1/2LSB，它超过最后一个码的过渡。

偏差是测量这条真实直线上的每个特定代码来的。

微分非线性误差（DNL）在理想的ADC中，每一个LSB码是分开的。

微分非线性是这个理想值的最大误差。

是保证在没有误码的情况下，通常为分辨率的关系。

±满量程误差末尾码+1转换（从011…10到011…11）将出现一个低于满量程的1/2LSB的模拟电压（对于±10V 范围是9.9995422V）。

满量程误差是理想值最后的偏差的实际水平转换。

双极性0点误差双极性0点误差是理想的中间量程输入电压（0V）和中间输出码所转换的实际电压之间的差异。

输入带宽输入带宽是满量程输入电压下降3dB的区域的输出幅值重建的基本的频率。

ADC是什么意思,ADC全称是什么

ADC 是什么意思,ADC 全称是什么ADC 全称：ADC 即模拟数字转换器（英语：Analog-to-digital converter）是用于将模拟形式的连续信号转换为数字形式的离散信号的一类设备。

一个模拟数字转换器可以提供信号用于测量。

与之相对的设备成为数字模拟转换器。

典型的模拟数字转换器将模拟信号转换为表示一定比例电压值的数字信号。

然而，有一些模拟数字转换器并非纯的电子设备，例如旋转编码器，也可以被视为模拟数字转换器。

中文称之为数模转换器，又称D/A 转换器，简称DAC，它是把数字量转变成模拟的器件。

D/A 转换器基本上由4 个部分组成，即权电阻网络、运算放大器、基准电源和模拟开关。

模数转换器中一般都要用到数模转换器，模数转换器即A/D 转换器，简称ADC，它是把连续的模拟信号转变为离散的数字信号的器件。

在计算机控制系统中，须经各种检测装置，以连续变化的电压或电流作为模拟量，随时提供被控制对象的有关参数（如速度、压力、温度等）而进行控制。

计算机的输入必须是数字量，故需用模数转换器达到控制目的。

分类直接转换模拟数字转换器（Direct-conversion ADC），或称Flash 模拟数字转换器（flash ADC）逐次逼近模拟数字转换器（Successive approximaTIon ADC）跃升-比较模拟数字转换器（Ramp-compare ADC）威尔金森模拟数字转换器（Wilkinson ADC）集成模拟数字转换器（IntegraTIng ADC）Delta 编码模拟数字转换器（Delta-encoded ADC）管道模拟数字转换器（Pipeline ADC）Sigma-Delta 模拟数字转换器（Sigma-delta ADC）时间交织模拟数字转换器（TIme-interleaved ADC）带有即时FM 段的模拟数字转换器也有利用电子技术和其他技术结合的转换器：时间延伸模拟数字转换器（TIme stretch analog-to-digital converter，TS-ADC。

解读ad7699模数转换

解读ad7699模数转换
AD7699是一款8通道、16位、500kSPS吞吐速率的模数转换器（ADC），其特点如下：
1.采样速率高达500kSPS，满足高速信号采样的需求。

2.16位分辨率，可提供高精度的数据转换。

3.支持8个模拟输入通道，可以同时对多个信号进行采样。

4.采用SPI接口进行配置和数据传输，方便与微控制器等数字器件连接。

5.内置数字滤波器，可有效降低噪声和干扰。

6.具有单极性输入和全带宽输入两种模式，可根据实际需求进行选择。

7.内置参考电压源，可实现高精度的数据转换。

8.具有数字滤波器，可对数据进行平滑处理，提高数据质量。

9.支持多种工作模式，如正常模式、低功耗模式等，可根据实际需求进行选择。

总的来说，AD7699是一款高性能的模数转换器，可广泛应用于各种需要进行高速、高精度信号采样的领域，如通信、测量、医疗电子等。

AD数据手册部分内容中文翻译

AD9959数据手册（部分）GENERAL DESCRIPTION概述The AD9959 consists of four direct digital synthesizer (DDS) cores that provide independent frequency, phase, and amplitude control on each channel. This flexibility can be used to correct imbalances between signals due to analog processing, such as filtering, amplification, or PCB layout-related mismatches. Because all channels share a common system clock, they are inherently synchronized. Synchronization of multiple devices is supported. The AD9959 can perform up to a 16-level modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is performed by applying data to the profile pins. In addition, the AD9959 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation.AD9959含有四个直接数字频率合成器（DDS），提供各通道独立的频率、相位和振幅控制。

模数转换AD转换精度和转换速度是衡量ADDA转换器性

仪器仪表与测试设备
示波器
示波器中的模数转换器用于将模拟信号转换为数字信号，以便在屏幕上显示波形，进行信号的观察和分析。
频谱分析仪
传感器数据采集
传感器数据采集系统中，模数转换器用于将传感器的模拟输出信号转换为数字信号，便于数据的处理、分析和传输。
频谱分析仪利用模数转换器将接收到的模拟信号转换为数字信号，进行频谱分析和测量。
吞吐量
衡量AD转换器处理能力的一个指标，表示每秒钟能够完成多少次AD转换。吞吐量通常以每秒转换次数（SPS）表示。
实时性能要求
实时性
指AD转换器的输出结果能否及时反映输入信号的变化。实时性能好的AD转换器能够快速响应输入信号的变化。
跟踪速度
衡量AD转换器实时性能的一个重要指标，表示AD转换器的输出能否跟随输入信号的快速变化。跟踪速度越快，实时性能越好。
模数转换器（AD转换器性能评估
目录
CONTENTS
• 模数转换器（AD转换器）简介 • AD转换精度 • AD转换速度 • AD转换器的应用领域 • AD转换器的发展趋势与挑战 • AD转换器性能评估案例研究
01
CHAPTER
模数转换器（AD转换器）简介
定义与工作原理
定义
模数转换器（AD转换器）是一种将模拟信号转换为数字信号的电子器件。
示。
采样速率
指AD转换器每秒钟能够采样的次数，通常以Hz或SPS（每秒采样点数）表示。
非线性误差
指AD转换器的输出与理想输出之间的偏差，通常以LSB（最低有效位）表示。
电源电压与功耗
指AD转换器正常工作所需的电源电压和功耗，对于便携式应
用非常重要。

12位AD转换器中英文翻译资料

12位AD转换器中英文翻译资料英文原文12-Bit A/D ConverterCIRCUIT OPERATIONThe AD574A is a complete 12-bit A/D converter which requires no external components to provide the complete successive approximation analog-to-digital conversion function. A block diagram of the AD574A is shown in Figure 1.Figure 1. Block Diagram of AD574A 12-BitA-to-D ConverterWhen the control section is commanded to initiate a conversion (as described later), it enables the clock and resets the successiveapproximation register (SAR) to all zeros. Once a conversion cycle has begun, it cannot be stopped or restarted and data is not available from the output buffers. The SAR, timed by the clock, will sequence through the conversion cycle and return an end-of-convert flag to the control section. The control section will then disable the clock, bring the output status flag low, and enable control functions to allow data read functions by external command.During the conversion cycle, the internal 12-bit current output DAC is sequencedby the SAR from the most significant bit (MSB) to least significant bit (LSB) to provide an output current which accurately balances the input signal current through the 5kΩ(or10kΩ) input resistor. The comparator determines whether the addition of each successively-weighted bit current causes the DAC current sum to be greater or less than the input current; if the sum is less, the bit is left on; if more, the bit is turned off. After testing all the bits, the SAR contains a 12-bit binary code which accurately represents the input signal to within 1/2 LSB.The temperature-compensated buried Zener reference provides the primary voltage reference to the DAC and guarantees excellent stability with both time and temperature. The reference is trimmed to 10.00 volts 0.2%; it can supply up to 1.5 mA to an external load in addition to the requirements of the reference input resistor (0.5 mA) and bipolar offset resistor (1 mA) when the AD574A is powered from 15 V supplies. If the AD574A is used with 12 V supplies, or if external current must be supplied over the full temperature range, an external buffer amplifier is recommended. Any external load on the AD574A reference must remain constant during conversion. The thin-film application resistors are trimmed to match the full-scale output current of the DAC. There are two 5 k input scaling resistors to allow either a 10 volt or 20 volt span. The 10 k bipolar offset resistor is grounded for unipolar operation and connected to the 10 volt reference for bipolar operation.DRIVING THE AD574 ANALOG INPUTFigure 2. Op Amp – AD574A InterfaceThe output impedance of an op amp has an open-loop value which, in a closed loop, is divided by the loop gain available at the frequency of interest. The amplifier should have acceptable loop gain at 500 kHz for use with the AD574A. To check whether the output properties of a signal source are suitable, monitor the AD574’s input with an oscilloscope while a conversion is in progress. Each of the 12 disturbances should subside in sorless.For applications involving the use of a sample-and-hold amplifier, the AD585 is recommended. The AD711 or AD544 op amps are recommended for dc applications. SAMPLE-AND-HOLD AMPLIFIERSAlthough the conversion time of the AD574A is a maximum of 35 s, to achieve accurate 12-bit conversions of frequencies greater than a few Hz requires the use of a sample-and-hold amplifier (SHA). If the voltage of the analog input signal driving the AD574A changes by more than 1/2 LSB over the time interval needed to make a conversion, then the input requires a SHA.The AD585 is a high linearity SHA capable of directly driving the analog input of the AD574A. The AD585’s fast acquisition time, low aperture and low aperture jitter are ideally suited for high-speed data acquisition systems. Consider the AD574A converter with a 35 s conversion time and an input signal of 10 V p-p: the maximum frequency which may be applied to achieve rated accuracy is 1.5 Hz. However, with the addition of an AD585, as shown in Figure 3, the maximum frequency increases to 26 kHz.The AD585’s low output impedance, fast-loop response, and low droop maintain 12-bits of accuracy under the changing load conditions that occur during a conversion, making it suitable for use in high accuracy conversion systems. Many other SHAs cannot achieve 12-bits of accuracy and can thus compromise a system. The AD585 is recommended for AD574A applications requiring a sample and hold.Figure 3. AD574A with AD585 Sample and HoldSUPPLY DECOUPLING AND LAYOUT CONSIDERATIONSIt is critically important that the AD574A power supplies be filtered, well regulated, and free from high frequency noise. Use of noisy supplies will cause unstable output codes. Switching power supplies are not recommended for circuits attempting to achieve 12-bit accuracy unless great care is used in filtering any switching spikes present in the output. Remember that a few millivolts of noise represents several counts of error in a 12-bit ADC.Circuit layout should attempt to locate the AD574A, associated analog input circuitry, and interconnections as far as possible from logic circuitry. For this reason, the use of wire-wrap circuit construction is not recommended. Careful printed circuit construction is preferred.UNIPOLAR RANGE CONNECTIONS FOR THE AD574AThe AD574A contains all the active components required to perform a complete 12-bit A/D conversion. Thus, for most situations, all that is necessary is connection of thepower supplies (+5 V, +12 V/+15 V and –12 V/–15 V), the analog input, and the conversion initiation command, as discussed on the next page. Analog input connections and calibration are easily accomplished; the unipolar operating mode is shown in Figure 4.Figure 4. Unipolar Input ConnectionsAll of the thin-film application resistors of the AD574A are trimmed for absolute calibration. Therefore, in many applications, no calibration trimming will be required. The absolute accuracy for each grade is given in the specification tables. For example, if no trims are used, the AD574AK guarantees 1 LSB max zero offset error and 0.25% (10 LSB) max full-scale error. (Typical full-scale error is 2 LSB.) If the offset trim is not required, Pin 12 can be connected directly to Pin 9; the two resistors and trimmer for Pin 12 are then not needed. If the full-scale trim is not needed, a 50 1% metal film resistor should be connected between Pin 8 and Pin 10.The analog input is connected between Pin 13 and Pin 9 for a 0 V to +10 V input range, between 14 and Pin 9 for a 0 V to +20 V input range. The AD574A easilyaccommodates an input signal beyond the supplies. For the 10 volt span input, the LSB has a nominal value of 2.44 mV; for the 20 volt span, 4.88 mV.If a 10.24 V range is desired (nominal 2.5 mV/bit), the gain trimmer (R2) should be replaced by a 50Ωesistor, and a 200Ωtrimmer inserted in series with the analog input to Pin 13 for a full-scale range of 20.48 V (5 mV/bit), use a 500 trimmer into Pin 14. The gain trim described below is now done with these trimmers. The nominal input impedance into Pin 13 is 5kΩ, and 10kΩinto Pin 14.UNIPOLAR CALIBRATIONThe AD574A is intended to have a nominal 1/2 LSB offset so that the exact analog input for a given code will be in the middle of that code (halfway between the transitions to the codes above and below it). Thus, the first transition (from 0000 0000 0000 to 0000 0000 0001) will occur for an input level of +1/2 LSB (1.22 mV for 10 V range).If Pin 12 is connected to Pin 9, the unit will behave in this manner, within specifications. If the offset trim (R1) is used, it should be trimmed as above, although a different offset can be set for a particular system requirement. This circuit will give approximately 15 mV of offset trim range.The full-scale trim is done by applying a signal 1/2 LSB below the nominal full scale (9.9963 for a 10 V range). Trim R2 to give the last transition (1111 1111 1110 to 1111 1111 1111).BIPOLAR OPERATIONThe connections for bipolar ranges are shown in Figure 5. Again, as for the unipolar ranges, if the offset and gain specifications are sufficient, one or both of the trimmers shown can be replaced by a 50 1% fixed resistor. Bipolar calibration is similar to unipolar calibration.Figure 5. Bipolar Input ConnectionsCONTROL LOGICThe AD574A contains on-chip logic to provide conversion initiation and data read operations from signals commonly available in microprocessor systems. Figure 6 shows the internal logic circuitry of the AD574A.The control signals CE, CS, and R/C control the operation of the converter. The state of R/C when CE and CS are both asserted determines whether a data read (R/C = 1) or a convert (R/C = 0) is in progress. The register control inputs AO and 12/8 control conversion length and data format. The AO line is usually tied to the least significant bit of the address bus. If a conversion is started with AO low, a full 12-bit conversion cycleis initiated. If AO is high during a convert start, a shorter 8-bit conversion cycle results. During data read operations, AO determines whether the three-state buffers containing the 8 MSBs of the conversion result (AO = 0) or the 4 LSBs (AO = 1) are enabled. The 12/8 pin determines whether the output data is to be organized as two 8-bit words (12/8 tied to DIGITAL COMMON) or a single 12-bit word (12/8 tied to VLOGIC). The 12/8 pin is not TTL-compatible and must be hard-wired to either VLOGIC or DIGITAL COMMON. In the 8-bit mode, the byte addressed when AO is high contains the 4 LSBs from the conversion followed by four trailing zeroes. This organization allows the datalines to be overlapped for direct interface to 8-bit buses without the need for external three-state buffers. It is not recommended that AO change state during a data read operation. Asymmetrical enable and disable times of the three-state buffers could cause internal bus contention resulting in potential damage to the AD574A.Figure 6. AD574A Control LogicAn output signal, STS, indicates the status of the converter. STS goes high at the beginning of a conversion and returns low when the conversion cycle is complete. TIMINGThe AD574A is easily interfaced to a wide variety of microprocessors and other digital systems. The following discussion of the timing requirements of the AD574A control signals should provide the system designer with useful insight into the operation of the device.Figure 7 shows a complete timing diagram for the AD574A convert start operation. R/C should be low before both CE and CS are asserted; if R/C is high, a read operation will momentarily occur, possibly resulting in system bus contention. Either CE or CS may be used to initiate a conversion; however, use of CE is recommended since itincludes one less propagation delay than CS and is the faster input. In Figure 7, CE is used to initiate the conversion.Figure 7Once a conversion is started and the STS line goes high, convert start commands will be ignored until the conversion cycle is complete. The output data buffers cannot be enabled during conversion.Figure 8 shows the timing for data read operations. During data read operations, access time is measured from the point where CE and R/C both are high (assuming CS is already low). If CS is used to enable the device, access time is extended by 100 ns.Figure 8. Read Cycle TimingIn the 8-bit bus interface mode (12/8 input wired to DIGITAL COMMON), the address bit, AO, must be stable at least 150 ns prior to CE going high and must remain stable during the entire read cycle. If AO is allowed to change, damage to the AD574A output buffers may result.“STAND-ALONE” OPERATIONThe AD574A can be used in a “stand-alone” mode, which is useful in systems with dedicated input ports available and thus not requiring full bus interface capability. In this mode, CE and 12/8 are wired high, CS and AO are wired low, and conversion is controlled by R/C. The three-state buffers are enabled when R/C is high and a conversion starts when R/C goes low. This allows two possible control signals—a high pulse or a low pulse. Operation with a low pulse is shown in Figure 11. In this case, the outputs are forced into the high impedance state in response to the falling edge of R/C and return to valid logic levels after the conversion cycle is completed. The STS line goes high 600 ns after R/C goes low and returns low 300 ns after data is valid.Figure 11. Low Pulse forR/C—Outputs Enabled After ConversionIf conversion is initiated by a high pulse as shown in Figure 12, the data lines are enabled during the time when R/C is high. The falling edge of R/C starts the next conversion, and the data lines return to three-state (and remain three-state) until the next high pulse of R/C.Figure 12. High Pulse for R/C—Outputs Enabled While R/C High, Otherwise High-ZUsually the low pulse for R/C stand-alone mode will be used. Figure 13 illustrates a typical stand-alone configuration for 8086 type processors. The addition of the 74F/S374 latches improves bus access/release times and helps minimize digital feedthrough to the analog portion of the converter.INTERFACING THE AD574A TO MICROPROCESSORSThe control logic of the AD574A makes direct connection to most microprocessor system buses possible. While it is impossible to describe the details of the interface connections for every microprocessor type, several representative examples will be described here.GENERAL A/D CONVERTER INTERFACE CONSIDERATIONSA typical A/D converter interface routine involves several operations. First, a write to the ADC address initiates a conversion.The processor must then wait for the conversion cycle to complete, since most ADCs take longer than one instruction cycle to complete a conversion. Valid data can, of course, only be read after the conversion is complete. The AD574A provides an output signal (STS) which indicates when a conversion is in progress. This signal can be polled by the processor by reading itthrough an external three-state buffer (or other input port). The STS signal can also be used to generate an interrupt upon completion of conversion, if the system timing requirements are critical (bear in mind that the maximum conversion time of the AD574A is only 35 microseconds) and the processor has other tasks to perform during the ADC conversion cycle. Another possible time-out method is to assume that the ADC will take 35 microseconds to co nvert, and insert a sufficient number of “do-nothing” instructions to ensure that 35 microseconds of processor time is consumed Once it is established that the conversion is finished, the data can be read. In the case of an ADC of 8-bit resolution (or less), a single data read operation is sufficient. In the case of converters with more data bits than are available on the bus, a choice of data formats is required, and multiple read operations are needed. The AD574A includes internal logic to permit direct interface to 8-bit or 16-bit data buses, selected by connection of the 12/8 input. In 16-bit bus applications (12/8 high) the data lines (DB11 through DB0) may be connected to either the 12 most significant or 12 least significant bits of the data bus. The remaining four bits should be masked in software. The interface to an 8-bit data bus (12/8 low) is done in a left-justified format. The even address (A0 low) contains the 8 MSBs (DB11 through DB4). The odd address (A0 high) contains the 4 LSBs (DB3 through DB0) in the upper half of the byte, followed by four trailing zeroes, thus eliminating bit masking instructions.SPECIFIC PROCESSOR INTERFACE EXAMPLESZ-80 System InterfaceThe AD574A may be interfaced to the Z-80 processor in an I/O or memory mapped configuration. Figure 15 illustrates an I/O or mapped configuration. The Z-80 uses address lines A0–A7 to decode the I/O port address.An interesting feature of the Z-80 is that during I/O operations a single wait state is automatically inserted, allowing the AD574A to be used with Z-80 processors having clock speeds up to 4 MHz. For applications faster than 4 MHz use the wait state generator in Figure 16. In a memory mapped configuration the AD574A may be interfaced to Z-80 processors with clock speeds of up to 2.5 MHz.附录E 中文翻译12位-AD574A转换器电路工作原理AD574A是一个完善的12位A/D转换器，不需要外部组件提供完全的逐步逼近模拟数字转换功能。