数字电子技术,英文版,chapter05.ppt

17
The NOR Gate as a Universal Logic Element
The NOR gate can be used to produce the NOT, AND, OR, and NAND operations.
18
5-4 COMBINATIONAL LOGIC USING NAND AND NOR GATES
2
& 1
3
6
4
&
5
9
10
& 1
11
8
12
&
13
1
7
GND
5
2 AND-OR-Invert Logic
X AB CD ( A B)(C D) An AND-OR-Invert can be used to implement POS expression.
A B
C D
A
& 1
XB
X
C
&
D
6
gates:
X AB CD
Solution: X AB CD
AB CD AB CD
A
B
X
C
D
21
Example: Implementing the following expression using NOR
gates: X ( A B)(C D)
Solution: X ( A B)(C D)
Example:
X ABC ABC
15
5-3 THE UNIVERSAL PROPERTY OF NAND AND NOR GATES
与非门和或非门的通用特征
16
The NAND Gate as a Universal Logic Element
The NAND gate can be used to produce the NOT, AND, OR, and NOR operations.
( A B)(C D) A B C D
A
B
X
C
D
22
NAND Logic
23
NOR Logic
24
5-5 Logic Hazards
Objective:
Combinational logic hazards Reasons Checking Eliminating methods
使用与非门和或非门的组合 逻辑
19
5 Combinational Logic Using NAND and NOR Gates
NAND AB A B
NOR A B AB
Negative-OR Negative-AND
20
Example: Implementing the
following expression using NAND
12
From a Boolean Expression to a Logic Circuit
Example:
X AB CDE
13
From a Boolean Expression to a Logic Circuit
Example:
X AB(C D EF )
14
From a Truth Table to a Logic Circuit
Example chip: 74LS51 14VCC
74LS51 : dual 2-
wide AND-ORInvert
1 two inputs AND-OR-Invert.
1 three inputs AND-OR-Invert
2
& 1
3
6
4
&
5
9
10
& 1
11
8
12
&
13
1
7
GND
7
3 Exclusive-OR (XOR)异或
0
momentarily as a result of an
input variable changing.
glitches
Static 0 : an output variable should be a 0, but goes to 1 momentarily as a result of an input variable changing.
010
27
Static 1 hazards example
2ds example
30
31
Checking static hazards:
If the circuit can be simplified as follows A+A=1 or AA=0, it has the potential to cause static hazards.
shape symbols
A
& 1
B
X
C
&
D
ANSI standard rectangular outline symbols
4
Example chip: 74HC58 14VCC
74HC58 (CMOS): dual AND-OR
1 two inputs AND-OR.
1 three inputs AND-OR
3
1 AND-OR Logic X=AB+CD
An AND-OR circuit directly implements SOP expression, assuming the complements of the variables are available.
A
B
X
C
D
ANSI standard distinctive
25
Combinational Logic Hazards
Static hazard Dynamic hazard
26
Static hazards
Static hazards have two cases:
Static 1 : an output variable
1
1
should be a 1, but goes to 0
X AB AB
A B
C
A B
1
C
8
9
4 Exclusive-NOR (XNOR)同或
X AB AB
A B
C
A B
1
C
10
X A B AB AB AB AB (A B)(A B) AB AB
11
5-2 IMPLEMENTING COMBINATIONAL LOGIC
实现组合逻辑
Chapter 5 Combinational Logic 组合逻辑
1
Logic circuit
Combinational Logic circuit
Sequential Logic circuit
2
5.1 Basic Combinational Circuits
AND-OR AND-OR-Invert XOR XNOR NAND NOR