[考研类试卷]计算机专业基础综合(存储器系统的层次结构)模拟试卷4.doc

[考研类试卷]计算机专业基础综合（存储器系统的层次结构）模拟试卷

一、单项选择题

1-40小题，每小题2分，共80分。下列每题给出的四个选项中，只有一个选项是最符合题目要求的。

1 下列关于相联存储器的说法中，错误的是( )。

（A）相联存储器指的是按内容访问的存储器

（B）在实现技术相同的情况下，容量较小的相联存储器速度较快

（C）相联存储器结构简单，价格便宜

（D）在存储单元数目不变的情况下，存储字长变长，相联存储器的访问速度下降

2 下列关于DRAM和SRAM的说法中，错误的是( )。

I．SRAM不是易失性存储器，而DRAM是易失性存储器

Ⅱ．DRAM比SRAM集成度更高，因此读写速度也更快

Ⅲ．主存只能由DRAM构成，而高速缓存只能由SRAM构成

Ⅳ．与SRAM相比，DRAM由于需要刷新，所以功耗较高

（A）Ⅱ、Ⅲ和Ⅳ

（B）I、Ⅲ和Ⅳ

（C）I、Ⅱ和Ⅲ

（D）I、Ⅱ、Ⅲ和Ⅳ

3 某机字长32位，主存容量1 MB，按字编址，块长512 B，Cache共可存放16个块，采用直接映射方式，则Cache地址长度为( )。

（A）11位

（B）13位

（C）18位

（D）20位

4 在Cache和主存构成的两级存储体系中，Cache的存取时间是100 ns，主存的存取时间是1 000 ns。如果希望有效(平均)存取时间不超过Cache存取时间的15％，则Cache的命中率至少应为( )。

（A）90％

（B）98％

（C）95％

（D）99％

5 下列关于Cache写策略的论述中，错误的是( )。

（A）全写法(写直达法)充分保证Cache与主存的一致性

（B）采用全写法时，不需要为Cache行设置“脏位／修改位”

（C）写回法(回写法)降低了主存带宽需求(即减少了Cache与主存之间的通信量)

（D）多处理器系统通常采用写回法

6 假定用若干个8K×8位的芯片组成一个32K×32位的存储器，则地址41FOH所在芯片的最大地址是 ( )。

（A）0000H

（B）4FFFH

（C）5FFFH

（D）7FFFH

7 某机器采用四体低位交叉存储器，现分别执行下述操作：

(1)读取6个连续地址单元中存放的存储字，重复80次；

(2)读取8个连续地址单元中存放的存储字，重复60次；

则(1)、(2)所花时间之比为( )。

（A）1：1

（B）2：1

（C）4：3

（D）3：4

8 某计算机的存储系统由Cache-主存系统构成，Cache的存取周期为10ns，主存的存取周期为50 ns。在CPU执行一段程序时，Cache完成存取的次数为4 800次，主存完成的存取次数为200次，该Cache-主存系统的效率是( )。(设Cache和主存不能同时访问。)

（A）0．833

（B）0．856

（C）0．958

（D）0．862

9 某机字长32位，主存容量1 MB，按宇编址，块长512 B，Cache共可存放16个块，采用直接映像方式，则Cache地址长度为( )。

（A）11位

（B）13位

（C）18位

（D）20位

10 n体(模n)交叉编址存储器在( )时，其存取带宽是单体存储器的n倍。

（A）连续访存的n个地址是针对同一个存储模块

（B）任何情况下都能

（C）连续访存的n个地址是针对不同的存储模块

（D）任何情况下都不能

11 设有主存-Cache层次的存储器，其主存容量1 MB，Cache容量16 KB，每字块有8个字，每字32位，采用直接地址映像方式。若主存地址为35301 H，且CPU 访问Cache命中，则该主存块在Cache的第( )字块中(Cache起始字块为第0字块)。

（A）152

（B）153

（C）154

（D）151

12 双端口存储器在( )发生访问冲突。

（A）左端口与右端口同时被访问的情况下

（B）同时访问左端口与右端口的地址码不同的情况下

（C）同时访问左端口与右端口的地址码相同的情况下

（D）任何情况下都不

13 下列关于双端口存储器和交叉存储器的叙述中，正确的是( )。

（A）双端口存储器两个端口使用同一组地址线、数据线和读写控制线，同时访问同一区间、同一单元。

（B）双端口存储器当两个端口同时访问相同的地址码时必然会发生冲突

（C）高位多体交叉存储器的设计依据了程序的局部性原理

（D）高位四体交叉存储器可能在一个存储周期内连续访问四个模块

14 下列关于主存一体多字和多体交叉方案的叙述中，不正确的是( )。

（A）主存一体多字使每个主存单元同时存储几个主存字，则每～次读操作就同时读出几个主存字，大大提高了主存读出一个字的平均速度

（B）多体交叉编址把主存储器分成几个能独立读写的、字长为多个主存字的主体

（C）主存一体多字需要把每次读出的几个主存字保存在一个位数足够长的存储器中

（D）多体交叉编址按读写需要情况，分别对每个存储体执行读写，几个存储体协同运行，提高了存储体的读写速度

15 设存储器容量为32字，字长为64位。模块数m=4，采用低位交叉方式。存储周期T=200 ns，数据总线宽度为64位，总线传输周期r=50 ns。该交叉存储器的带宽是( )。

（A）32×107b／s

（B）8×107b／s

（C）73×107b／s

（D）18×107b／s

16 某机器采用四体低位交叉存储器，现分别执行下述操作：

(1)读取6个连续地址单元中存放的存储字，重复80次；

(2)读取8个连续地址单元中存放的存储字，重复60次。

则(1)和(2)所花时间之比为( )。

（A）1：1

（B）2：1

（C）4：3

（D）3：4

17 设n体交叉编址(低位交叉)存储器中每个体的存储字长等于数据总线宽度，每个体存取一个宇的存取周期为T，总线传输周期为t，则T与t的关系以及读取地址连续的，t个字需要的时间分别是( )。

（A）T=t，T+nt

（B）T=(n—1)t，T+nt

（C）T=nt，T+nt

（D）T=nt，T+(n一1)t

18 实现虚拟存储器的关键是虚拟地址向实际地址的快速变换。为此，在处理器内部设置一个特殊的Cache来记录最近使用页的页表项，以快速完成地址转换。不同文献对这个特殊的Cache有不同的称呼。下列选项中，不属于这些称呼的是( )。

（A）转换旁视缓冲器(TLB)

（B）转换后援缓冲器

（C）快表

（D）慢表

19 虚拟存储器不能解决的问题是( )。

（A）存储系统成本高

（B）编程空间受限

（C）访存速度慢

（D）多道程序共享主存而引发的信息安全

20 在页面尺寸为4 KB的页式存储管理中，页表中的内容依次是2、5、6、8、7、11，则物理地址32773对应的逻辑地址为( )。

（A）32773

（B）42773

（C）12293

（D）62773

21 当缺页故障处理完毕后，处理器将( )。

（A）重新执行引发缺页故障的指令

（B）执行导致发生缺页故障的指令的下一条指令

（C）重新开始执行发生缺页故障的指令所在的进程

（D）终止执行发生缺页故障的指令所在的进程

22 页式存储管理系统不会出现( )。

（A）抖动／颠簸

（B）内零头(内碎片)

（C）外零头(外碎片)

（D）越界访问

23 下列关于页式存储管理与段式存储管理的区别的论述中，正确的是( )。（A）页式存储管理更有利于存储保护

（B）段式存储管理的存储空间利用率较高

（C）在段式存储管理中，指令或数据不会跨段存储

（D）段的尺寸要大于页的尺寸

二、综合应用题

41-47小题，共70分。

24 假设CPU执行某段程序时，950次从Cache得到数据，50次从主存得到数据，已知Cache存取周期为50 ns，主存存取周期为200 ns(设每次访问时，Cache访问与主存访问并发进行，如Cache命中则中断主存的访问)。求：

(1)Cache的命中率。

(2)平均访问时间。

(3)Cache一主存系统的效率。

25 已知某8位机的主存采用半导体存储器，地址码为18位，若使用4K×4位RAM芯片组成该机所允许的最大主存空间，并选用模块条的形式，问：

(1)若每个模块条为32K×8位，共需几个模块条?

(2)每个模块内共有多少片RAM芯片?

(3)主存共需多少RAM芯片?CPU如何选择各模块条?

26 设某机中，CPU的地址总线为A15～A0，数据总线为D7～D0(A0、D0为最低位)。存储器地址空间为3000H～67FFH。其中3000H～4FFFH为ROM区，选用4K×2的ROM芯片；5000H～67FFH为RAM区，选用2K×4的SRAM芯片。请

问： (1)组成该存储器需要多少片ROM芯片和SRAM芯片? (2)ROM芯片、SRAM 芯片各需连接CPU的哪几根地址线和数据线? (3)应如何设置片选信号，分别写出各片选信号的逻辑表达式。

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