current mode VS voltage mode control in synchronous buck converters
反激式变换器电路仿真建模与分析
学号:常州大学毕业设计(论文)(2012届)题目学生学院专业班级校内指导教师专业技术职务校外指导老师专业技术职务二○一二年六月反激式变换器电路仿真建模与分析摘要:开关DC-DC变换器是一种典型的强非线性时变动力学系统,存在各种类型的次谐波、分岔与混沌等丰富的非线性现象。
这些非线性现象严重影响开关DC-DC变换器的性能。
因此,深入分析和研究开关DC-DC变换器的分岔和混沌等非线性动力学现象,对开关DC-DC变换器的设计、运行及控制都具有重要的指导意义。
反激式变换器是一种隔离式开关变换器,该变换器利用变压器实现了输入与输出电气隔离。
变压器具有变压的功能有利于扩大变换器的输出设备应用范围,也便于实现不同电压的多路输出或相同电压的多种输出。
运用变压器进行隔离使电源与负载两个直流系统之间是绝缘的,即使输出短路也不会影响外部电源。
本文利用PSIM电路仿真软件进行电路仿真,给出峰值电流控制反激式变换器和电压反馈控制反激式变换器各电路参数变化时的时域波形和在输出电压-安匝和平面上的相轨图,并对输入电压和负载电阻两个参数进行分析,从而确定其稳定工作时的参数区域。
本文对反激式变换器进行建模和PSIM电路仿真分析,了解到该变换器在不同电路参数时的运行情况,有效地估计出该变换器处于稳定工作状态时的电路参数范围,有助于制作实际反激式变换器电路参数的合理选取。
关键词:反激式变换器;安匝和;峰值电流控制;电压反馈控制;稳定性;PSIM;仿真Simulation Modeling and Analysis of the fly back convertercircuitAbstract: Switching DC-DC converters are a type of strong nonlinear and time-varying dynamical systems with all kinds of nonlinear phenomena, such as subharmonic, bifurcation, and chaos. These phenomena will seriously impact the work of the switching DC-DC converters. So, the deep analysis and study of these nonlinear dynamical phenomena have an important significance for design of switching DC-DC converter.Fly back converter is a special switching DC-DC converter, in which the transformer is employed to isolate the input from output. And the use of transformer in fly back converter is convenient to expand the output range and realize multi-output.In this paper, using the PSIM software, the simulation circuits of peak current mode(PCM) controlled fly back converter and voltage mode(VM) controlled fly back converter are built. Based on the simulation circuit and different circuit parameters, the operation of PCM controlled fly back converter is analysed and studied by time-domain waveforms and phase portraits in inductor current and total ampere-turns plane. Besides, the input voltage and load resistor are considered as two variables to depict the steady-state and unsteady-state region of the converter. The research results can help to choose reasonable circuit parameters in designing fly back converter circuit.Key works:Fly back converter; Total ampere-turns; Chaos; Peak current mode control; V oltage mode control; Stability; PSIM; Simulation目次摘要 (I)目次 (III)1 引言 (1)2 开关DC-DC变换器及其控制技术简介 (2)2.1 开关DC-DC变换器 (2)2.1.1 Buck变换器 (2)2.1.2 Boost变换器 (2)2.1.3 Buck-Boost变换器 (3)2.1.4 反激式变换器 (3)2.2开关DC-DC变换器控制技术 (6)2.2.1 固定频率控制技术 (6)2.2.2 可变频率控制技术 (9)2.3 PSIM软件简介 (10)3 反激式变换器的建模与仿真分析 (11)3.1 PCM控制反激式变换器的PSIM建模 (11)3.2 PCM控制反激式变换器的仿真分析 (12)3.3 VM控制反激式变换器的PSIM建模 (14)3.4 VM控制反激式变换器的仿真分析 (14)4 反激式变换器的稳定工作参数域仿真与分析 (16)4.1利用输入电压和负载确定稳定工作参数域 (16)4.2 利用参考电流和负载确定稳定工作参数域 (21)4.3 利用参考电流和输入电压来确定作参数域 (24)5 结论 (27)参考文献 (28)致谢 (30)1 引言开关DC-DC变换器是一类典型的强非线性时变动力学系统,存在各种类型的次谐波、分岔和混沌等丰富的非线性现象[1-15]。
电流控制模式原理
电流控制模式原理
电流控制模式(CurrentModeControl)又称电流型控制,是一种常用的电源开关控制方式,主要用于开关电源中的稳压控制和输出电流限制。
与传统的电压控制模式( Voltage Mode Control )不同,电流控制模式的控制对象是电感或电容的电流,而不是输出电压。
其原理是通过对电感或电容的电流进行快速反馈调整,从而控制开关管的导通和断开,实现对输出电流的精准控制。
电流控制模式有多种实现方式,其中比较常见的是平均电流控制( Average Current Control )和峰值电流控制( Peak Current Control )。
平均电流控制是通过对电感或电容的平均电流进行反馈控制,实现对输出电流的控制;峰值电流控制则是通过对电感或电容的峰值电流进行反馈控制,实现对输出电流的控制。
两种方式各有优缺点,需要根据具体情况进行选择。
电流控制模式的优点是响应速度快,稳定性好,输出电流波形平稳,对于负载变化响应迅速,可以有效提高系统的动态响应能力。
同时,电流控制模式能够实现电感或电容的电流保护,避免输出电流过载或瞬间过大对系统带来的损害。
因此,在高精度稳压和大功率开关电源中,电流控制模式被广泛应用。
总之,电流控制模式是一种高效、稳定、可靠的开关电源控制方式,具有广泛的应用前景。
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3842典型正激电路
APPLICATION NOTE
INTRODUCTION
With the introduction of the CS3842A PWM IC, current–mode is possible for power supplies of a wide range of output power levels. It’s low cost makes the CS3842A particularly attractive in low power DC to DC converter applications. But because this IC can provide a high output current (1.0 A peak, 200 mA average), it is also capable of driving large power MOSFETS which can switch high amounts of power. Current–Mode vs. Voltage–Mode Control In a switching power supply, the output voltage is controlled by varying the conduction duty cycle of the power switch(es). Traditionally duty cycle control was done by comparing the amplified difference of the output voltage feedback signal and a fixed stable reference to the sawtooth waveform derived from an oscillator. This constitutes the basic voltage mode control (VMC) scheme. VMC was later improved by allowing a sample of the input voltage to vary the slope of the sawtooth waveform. This feed forward scheme provided excellent line regulation in most of the popular circuit topologies. However, the task of compensating voltage mode converters has not been simple due to its resonant peak and 40 dB/decade roll off associated with the output LC filter.
开关电源电压和电流两种控制类型
开关电源电压和电流两种控制类型开关电源有两种控制类型,一种是电压控制(Voltage Mode Control),另一种是电流控制(Current Mode Control)。
二者有各自的优缺点,很难讲某种控制类型对所有应用都是最优化的,应根据实际情况加以选择。
1、电压控制型开关电源的基本原理是什么?电压控制是开关电源最常用的一种控制类型。
以降压式开关稳压器(即Buck变换器)为例,电压控制型的基本原理及工作波形分别如图2-2-2(a)、(b)所示。
电压控制型的特点是首先通过对输出电压进行取样(必要时还可增加取样电阻分压器),所得到的取样电压UQ就作为控制环路的输入信号;然后对取样电压UQ和基准电压UREF进行比较,并将比较结果放大成误差电压Ur,再将Ur送至PWM 比较器与锯齿波电压UJ进行比较,获得脉冲宽度与误差电压成正比的调制信号。
图中的振荡器有两路输出,一路输出为时钟信号(方波或矩形波),另一路为锯齿波信号,CT为锯齿波振荡器的定时电容。
T为高频变压器,VT为功率开关管。
降压式输出电路由整流管VD1、续流二极管VD2、储能电感L和滤波电容CO组成。
PWM锁存器的R 为复位端,S为置位端,Q为锁存器输出端,输出波形如图2-2-2(b)所示。
图2-2-2电压控制型开关电源的基本原理及工作波形(a)基本原理;(b)工作波形2、电压控制型开关电源有哪些优点?电压控制型开关电源具有以下优点:(1)它属于闭环控制系统,且只有一个电压反馈回路(即电压控制环),电路设计比较简单。
(2)在调制过程中工作稳定。
(3)输出阻抗低,可采用多路电源给同一个负载供电。
3、电压控制型开关电源有哪些缺点?电压控制型开关电源的主要缺点如下:(1)响应速度较慢。
虽然在电压控制型电路中使用了电流检测电阻RS,但RS并未接入控制环路。
因此,当输入电压发生变化时,必须等输出电压发生变化之后,才能对脉冲宽度进行调节。
由于滤波电路存在滞后时间,输出电压的变化要经过多个周期后才能表现出来。
开关电源PWM的五种反馈控制模式
一、引言PWM开关稳压或稳流电源基本工作原理就是在输入电压变化、内部参数变化、外接负载变化的情况下,控制电路通过被控制信号与基准信号的差值进行闭环反馈,调节主电路开关器件的导通脉冲宽度,使得开关电源的输出电压或电流等被控制信号稳定。
PWM的开关频率一般为恒定,控制取样信号有:输出电压、输入电压、输出电流、输出电感电压、开关器件峰值电流。
由这些信号可以构成单环、双环或多环反馈系统,实现稳压、稳流及恒定功率的目的,同时可以实现一些附带的过流保护、抗偏磁、均流等功能。
对于定频调宽的PWM闭环反馈控制系统,主要有五种PWM反馈控制模式。
下面以VDMOS开关器件构成的稳压正激型降压斩波器为例说明五种PWM反馈控制模式的发展过程、基本工作原理、详细电路原理示意图、波形、特点及应用要点,以利于选择应用及仿真建模研究。
二、开关电源PWM的五种反馈控制模式1. 电压模式控制PWM (VOLTAGE-MODE CONTROL PWM):如图1所示为BUCK降压斩波器的电压模式控制PWM反馈系统原理图。
电压模式控制PWM是六十年代后期开关稳压电源刚刚开始发展起就采用的第一种控制方法。
该方法与一些必要的过电流保护电路相结合,至今仍然在工业界很好地被广泛应用。
电压模式控制只有一个电压反馈闭环,采用脉冲宽度调制法,即将电压误差放大器采样放大的慢变化的直流信号与恒定频率的三角波上斜波相比较,通过脉冲宽度调制原理,得到当时的脉冲宽度,见图1A中波形所示。
逐个脉冲的限流保护电路必须另外附加。
主要缺点是暂态响应慢。
当输入电压突然变小或负载阻抗突然变小时,因为有较大的输出电容C及电感L相移延时作用,输出电压的变小也延时滞后,输出电压变小的信息还要经过电压误差放大器的补偿电路延时滞后,才能传至PWM比较器将脉宽展宽。
这两个延时滞后作用是暂态响应慢的主要原因。
图1A电压误差运算放大器(E/A)的作用有三:①将输出电压与给定电压的差值进行放大及反馈,保证稳态时的稳压精度。
新款低成本绿色功率便携式PWM控制器CR6848说明书
CR6848Novel Low Cost Green-Power PWM Controller Featuresz Low Cost, PWM&PFM&CRMz Low Start-up Current (about 10µA)z Low Operating Current (about 2mA) z Current Mode Operationz Under Voltage Lockout (UVLO)z Built-in Synchronized SlopeCompensationz Programmable PWM Frequencyz Leading edge Blanking on Sense input z Constant output power limiting foruniversal AC inputz Cycle-by-cycle current limitingz Clamped gate output voltage 16.5Vz Over voltage protect 26.7Vz High-Voltage CMOS Process with ESD z SOT-23-6L、SOP-8 & DIP-8 Pb-Free Packagingz Compatible with SG5701 & SG5848 & LD7535 &OB22632/63Applicationsz Switching AC/DC Adaptor z Battery Charger z Open Frame Switching Power Supply z 384X ReplacementGeneral DescriptionThe CR6848 is a highly integrated low cost current mode PWM controller, which is ideal for small power current mode of offline AC-DC fly-back converter applications. Making use of external resistors, the IC changes the operating frequency and automatically enters the PFM/CRM under light-load/zero-load conditions. This can minimize standby power consumption and achieve green-power functions. With a very low start-up current, the CR6848 could use a large value start-up resistor (1.5Mohm). Built-in synchronized slope compensation enhances the stability of the system and avoids sub-harmonic oscillation. Dynamic peak limiting circuit minimizes output power change caused by delay time of the system over a universal AC input range. Leading edge blanking circuit on current sense input could remove the signal glitch due to snubber circuit diode reverse recovery and thus greatly reduces the external component count and system cost in the design. Pulse-by-pulse current limiting ensures safe operation even during short-circuit.The CR6848 offers more protection like OVP (Over Voltage Protection) and OCP (Over current protection). The CR6848’s output driver is clamped to maximum 16.5Vto protect the power MOSFET. Excellent EMI performance is achieved soft switching control at the totem pole gate driver output. CR6848 is offered in SOT-23-6, SOP-8 and DIP-8 packages.Dec, 2006 V1.5 1/14Block DiagramTYPICAL CHARACTERISTICSVDD startup Current VS TemperatureVDD (OFF) VS TemperatureOVP VS TemperatureDuty cycle VS TemperatureVDD startup Current VS TemperatureVDD Operation Current VS TemperaturePWM frequency VS TemperatureF OSC VS FB CurrentF OSC VS RI pin resistorDec, 2006 V1.5 8/14OPERATION DESCRIPTION Current ModelCompared to voltage model control, current model control has a current feedback loop. When the voltage of the sense resistor peak current of the primary winding reaches the internal setting value V TH , comparator reverse, register reset and power MOSFET cut-off. So that to detect and modulate the peak current cycle by cycle could control the output of the power supply. The current feedback has a good linear modulation rate and a fast input and output dynamic impact avoid the pole that the output filter inductance brings and the second class system descends to first class and so it widens the frequency range and optimizes overload protection and short circuit protection.Startup Current and Under Voltage LockoutThe startup current of CR6848 is set to be very low so that a large value startup resistor can therefore be used to minimize the power loss. For AC to DC adaptor with universal input range design, a 1.5 M Ω, 1/8 W startup resistor and a 10uF/25V VDD hold capacitor could be used.The turn-on and turn-off threshold of the CR6848 is designed to 16.1V/11.1V. During startup, the hold-up capacitor must be charge to 16.1V through the startup resistor. The hysteresis is implemented to prevent the shutdown from the voltage dip during startup.Internal Bias and OSC OperationA resistor connected between RI pin and GND pin set the internal constant current source to charge or discharge the internal fixed cap. The charge time and discharge time determine the internal clock speed and the switching frequency. Increasing the resistance will reduce the value of the input current and reduce the switching frequency. The relationship between RI pin and PWM switching frequency follows the below equation within the RI allowed range.)()(5800kHz K RI F OSC Ω=For example, a 100k Ω resistor RI could generate a 50uA constant current and a 58kHz PWM switching frequency. Thesuggested operating frequency range of CR6848 is within 48KHz to 100KHz.Green Power OperationThe power dissipation of switching mode power supply is very important in zero load or light load condition. The major dissipation result from conduction loss 、switching loss and consume of the control circuit. However, all of them related to the switching frequency. There are many difference topologies has been implemented in different chip. The basic operation theory of all these approaches intended to reduce the switching frequency under light-load or no-load condition.CR6848`s green power function adapts PWM 、PFM and CRM combining modulation. When RI resistor is 100k, the PWM frequency is 58kHz in medium or heavy load operation. Through modifying the pulse width, CR6848 could control output voltage. The current of FB pin increases when the load is in light condition and the internal mode controller enters PFM&PWM when the feedback current is over 0.92mA. The operation frequency of oscillator is to descend gradually. The invariable frequency of oscillator is 11.6kHz when the feedback current is over 1.05mA. To decrease the standby consumption of the power supply , Chip-Rail introduces the Cycle Reset Mode technology ;If the feedback current were over 1.1mA, mode controller of CR6848 would reset internal register all the time and cut off the gate pin, while the output voltage is lower than the set value, it would set register, gate pin operating again. Although the frequency of the internal OSC is invariable, the register would reset some pulses so that the practical frequency is decreased at the gate pin.CR6848 Green-Power FunctionDec, 2006 V1.5 9/14Internal Synchronized Slop Compensation Although there are more advantages of the current mode control than conventional voltage mode control, there are still several drawbacks of peak-sensing current-mode converter. Especially the open loop instability when it operates in higher than 50% of the duty-cycle. CR6848 is introduced an internal slope compensation adding voltage ramp to the current sense input voltage for PWM generation to solve this problem. It improves the close loop stability greatly at CCM, prevents the sub-harmonic oscillation and thus reduces the output ripple voltage.DUTYDUTY DUTYV MAXSLOP ×=×=4389.033.0Current Sensing & Dynamic peak limitingThe current flowing by the power MOSFET comes in to being a voltage V SENSE on the sense pin cycle by cycle, which compares to the internal reference voltage, controls the reverse of the internal register, limits the peak current IMAX of the primary of the transformer. The energy 221MAX I L E ××=deposited by the transformer. So adjusting the R SENSE can set the Max output power of the power supple mode. The current flowing by the power MOSFET has an extra valueD PINT L V I ×=∆ due to the system delay T that the current detected from the sense pin to power MOSFET cut off in the CR6848 (Among these, V IN is the primary winding voltage of the transformer and L P is theprimary wind inductance. IN V ranges from 85VAC to 264V AC. To guarantee the outputpower is a constant for universal input AC voltage, there is a dynamic peak limit circuit to compensate the system delay T that the system delay brings on.Leading-edge Blanking (LEB)Each time the power MOSFET is switched on, a turn-on spike will inevitably occur at the sense pin, which would disturb the internal signal from the sampling of the R SENSE . There is a 300n sec leading edge blanking time built in to avoid the effect of the turn-on spike and the power MOSFET cannot be switched off during this time. So that the conventional external RC filtering on sense input is no longer required.Over Voltage Protection (OVP)There is a 26.7V over-voltage protection circuit in the CR6848 to improve the credibility and extend the life of the chip. The GATE is to shutdown immediately when the voltage of the VDD is over 26.7V and the voltage of VDD is to descend rapidly.Gate Driver & Soft ClampedCR6848’ output designs a totem pole to drive a periphery power MOSFET. The dead time is introduced to minimize the transfixion current when the output is drove. The NMOS is shut off when the other NMOS is turned on. The clamp technology is introduced to protect the periphery power MOSFET from breaking down.。
UC3842 提供低成本电流模式控制
应用笔记U-100AU-100AAPPLICATION NOTEUC3842/3/4/5 PROVIDES LOW-COSTCURRENT-MODE CONTROLINTRODUCTIONCURRENT-MODE CONTROLThe fundamental challenge of power supply design is to simultaneously realize two conflicting objectives: good electrical performance and low cost. The is an integrated pulse width modulator designed with both these objectives in mind. This provides de-signers an inexpensive controller with which they can ob-tain all the performance advantages of current mode op-eration. In addition, the UC3842 series is optimized for ef-ficient power sequencing of off-line converters, DC to DC regulators and for driving power MOSFETs or transistors.This application note provides a functional description of the UC3842 family and highlights the features of each in-dividual member, the UC3842, UC3843, UC3844 and UC3845 Throughout the text, the UC3842 part number will be referenced, however the generalized circuits and performance characteristics apply to each member of the UC3842 series unless otherwise noted. A review of cur-rent mode control and its benefits is included and meth-ods of avoiding common pitfalls are mentioned. The final section presents designs of power supplies utilizing UC3842 control.Figure 1 shows the two-loop current-mode control system in a typical buck regulator application. A clock signal initi-ates power pulses at a fixed frequency. The termination of each pulse occurs when an analog of the inductor current reaches a threshold established by the error signal. In this way the error signal actually controls peak inductor cur-rent. This contrasts with conventional schemes in which the error signal directly controls pulse width without regard to inductor current.Several performance advantages result from the use of current-mode control. First, an input voltage feed-forward characteristic is achieved; i.e., the control circuit instanta-neously corrects for input voltage variations without using up any of the error amplifier’s dynamic range. Therefore,line regulation is excellent and the error amplifier can be dedicated to correcting for load variations exclusively.For converters in which inductor current is continuous,controlling peak current is nearly equivalent to controlling average current. Therefore, when such converters employ current-mode control, the inductor can be treated as anFigure 1. Two-Loop Current-Mode Control SystemUC3842/3/4/5提供了低成本的电流模式控制引言电源设计的主要难题是需要同时实现两个相互矛盾的目标,即:上佳的电性能和低成本。
Current-Mode Modeling for Peak, Valley and Emulated Control Methods
CURRENT-MODE MODELING FOR PEAK, V ALLEY ANDEMULATED CONTROL METHODSReference Guide for Fixed-Frequency, Continuous Conduction-Mode OperationRobert SheehanPrincipal Applications EngineerNational Semiconductor CorporationSanta Clara, CACurrent-Mode ControlFor current-mode control there are three things to consider:1.Current-mode operation. An ideal current-mode converter is only dependent on the dc oraverage inductor current. The inner current loop turns the inductor into a voltage-controlled current source, effectively removing the inductor from the outer voltagecontrol loop at dc and low frequency.2.Modulator gain. The modulator gain is dependent on the effective slope of the ramppresented to the modulating comparator input. Each operating mode will have a unique characteristic equation for the modulator gain.3.Slope compensation. The requirement for slope compensation is dependent on therelationship of the average current to the value of current at the time when the sample is taken. For fixed-frequency operation, if the sampled current were equal to the averagecurrent, there would be no requirement for slope compensation.Current-Mode OperationWhether the current-mode converter is peak, valley, average, or sample-and-hold is secondary to the operation of the current loop. As long as the dc current is sampled, current-mode operation is maintained. The current-loop gain splits the complex-conjugate pole of the output filter into two real poles, so that the characteristic of the output filter is set by the capacitor and load resistor. To understand how this works, voltage-mode operation is examined. The basic concept of pulse-width modulation is used to establish the criteria for the modulator gain. This allows a linear model to be developed, illustrating the dc- and ac-gain characteristics.Having established the basic modulator concept, the current loop is added by sensing the inductor current, and feeding the sensed signal back to the modulator.Modulator GainFor simplicity, the buck regulator is used to illustrate the operation.Figure 1. Pulse-width modulatorVoltage-ModeA comparator is used to modulate the duty cycle. Fixed-frequency operation is shown in Figure 1, where a sawtooth voltage ramp is presented to the inverting input. The control or error voltage is applied to the non-inverting input. The modulator gain F m is defined as the change in control voltage which causes the duty cycle to go from 0% to 100%:RAMPC m V 1v d F ==The modulator voltage gain K m , which is the gain from the control voltage to the switch voltage is defined as:RAMPIN m IN m V V F V K =⋅=For voltage-mode operation, the control-to-output transfer function is found by multiplying the modulator voltage gain by the output filter response. With V IN = 10V and V RAMP = 1V, K m = 10 which is 20dB. Figure 2 shows the schematic, linear model and frequency response plot. The complex-conjugate pole of the LC output filter is clearly seen, with the resulting 180° phase shift.Figure 2. (a) Voltage-mode buck, (b) Linear model, (c) Frequency responseFigure 3. (a) Current-mode buck, (b) Linear model, (c) Frequency response Current-ModeThe same PWM function occurs for current-mode control, except that the ramp is created by monitoring the inductor current. This signal is comprised of two parts: the ac ripple current, and the dc or average value of the inductor current. The output of the current-sense amplifier G i is summed with an external ramp V SLOPE, to produce V RAMP at the inverting input of the comparator.In Figure 3 the effective V RAMP = 1V, which was used for the voltage-mode modulator. With V IN = 10V, the modulator voltage gain K m = 10.The linear model for the current loop is an amplifier which feeds back the dc value of the inductor current, creating a voltage-controlled current source. This is what makes the inductor disappear at dc and low frequency. The ac ripple current sets the modulator gain.The current-sense gain is usually expressed as the product of the current-sense amplifier gain and the sense resistor:S i i R G R ⋅=The current-sense gain is an equivalent resistance, the units of which are volts/amp. The current-loop gain is the product of the modulator voltage gain and the current-sense gain, which is also in volts/amp. The modulator voltage gain is reduced by the equivalent divider ratio of the loadresistor R O and the current-loop gain K m · R i . This sets the dc value of the control-to-output gain. Neglecting the dc loss of the sense resistor:im O Om C O R K R R K V V ⋅+⋅=This is usually written in factored form:im OiOC O R K 11R R V V ⋅+⋅=The dominant pole in the transfer function appears when the impedance of the output capacitor equals the parallel impedance of the load resistor and the current-loop gain:⎟⎟⎠⎞⎜⎜⎝⎛⋅+⋅=im O OP R K 1R1C 1ωThe inductor pole appears when the impedance of the inductor equals the current-loop gain:LR K ωim L ⋅=The current loop creates the effect of a lossless damping resistor, splitting the complex-conjugate pole of the output filter into two real poles.For current-mode control, the ideal steady-state modulator gain may be modified dependingupon whether the external ramp is fixed, or proportional to some combination of input and output voltage. Further modification of the gain is realized when the input and output voltages areperturbed to derive the effective small-signal terms. However, the concepts remain valid, despite small-signal modification of the ideal steady-state value.Slope CompensationThe difference between the average inductor current and the dc value of the sampled inductor current can cause instability for certain operating conditions. This instability is known as sub-harmonic oscillation, which occurs when the inductor ripple current does not return to its initial value by the start of next switching cycle. Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow pulses at the switch node. Adding an external ramp (slope compensation) to the current-sense signal prevents this oscillation.Formal derivation of the criteria for slope compensation is covered in reference [1]. For the purpose of this analysis, a discussion of feed-forward techniques and some illustrations will suffice.For the buck regulator, the modulator voltage gain K m was found to be V IN / V RAMP. For voltage-mode operation, the gain varies with V IN. Feed-forward techniques are often employed to stabilize the gain. This is typically done by generating V RAMP with a voltage-controlled current source or fixed resistor charging a capacitor from V IN.Peak Current-ModePeak current-mode control is often referred to as having inherent line feed-forward. This is basically true, but is not quite ideal. The sensed inductor up-slope, which is used as V RAMP / T for the modulator is equal to (V IN - V O) · R i / L. In order to stabilize the gain, an external ramp ofV SLOPE / T = V O · R i / L must be added to the current-sense signal. The resultant V RAMP / T = V IN · R i / L.Figure 4 shows the under-damped condition, where sub-harmonic oscillation occurs with a duty cycle greater than 50%. The relationship of Q as shown in the graphs is covered in the section on sampling gain. To demonstrate the under-damped condition, V SLOPE / T = 0.1 · V O · R i / L.Figure 4. Peak current-mode sub-harmonic oscillation. For D<0.5, sub-harmonic oscillation is damped. For D>0.5, sub-harmonic oscillation builds with insufficient slope compensation.By adding a compensating ramp equal to the down-slope of the inductor current, any tendency toward sub-harmonic oscillation is damped within one switching cycle. This is demonstrated graphically in Figure 5.Figure 5. Optimally compensated peak current-mode buck.For peak current-mode control, when the compensating ramp is equal to one-half the down-slope of the inductor current, infinite line rejection is achieved. Though a desirable operating point, this represents a special case. As the theoretical limit for stability of the current loop, the tendency toward sub-harmonic oscillation increases as the duty cycle approaches unity. To ensure stability of the current loop, the optimal compensating slope remains equal to one times the down-slope of the inductor current.Valley Current-ModeFor valley current-mode, the down-slope of the inductor current is presented to the modulator, which is V O · R i / L. This transposes the function of the external ramp. It is now necessary to use slope compensation equal to the up-slope of the inductor current, so V SLOPE / T = (V IN - V O) · R i / L. Again, the resultant V RAMP / T = V IN · R i / L.Figure 6 shows the under-damped condition, where sub-harmonic oscillation occurs with a duty cycle less than 50%. To demonstrate the under-damped condition, V SLOPE / T = 0.1 · (V IN - V O) · R i / L.Figure 6. Valley current-mode sub-harmonic oscillation. For D>0.5, sub-harmonic oscillation is damped. For D<0.5, sub-harmonic oscillation builds with insufficient slope compensation.Emulated Peak Current-ModeFor emulated peak current-mode, the valley current is sampled on the down-slope of the inductor current. This is used as the dc value of current to start the next cycle. A slope-compensating ramp is added to produce V RAMP at the modulator input.The primary application for emulated peak current-mode is high input voltage to low output voltage operating at a narrow duty cycle. In any practical design, device capacitance and wiring inductance may cause a significant leading-edge spike on the current-sense waveform, followed by an extended period of ringing. By sampling the inductor current at the end of the switching cycle and adding an external ramp, the minimum on-time can be significantly reduced, without the need for blanking or filtering which is normally required for peak current-mode control.To determine the correct slope compensation, the most salient feature is the absence of any ramp from the inductor, since only the dc value of the valley current is sampled. Formal derivation in reference [1] has shown the optimal compensation to be V SLOPE / T = V RAMP / T = V IN · R i / L. This is consistent with the results for both peak and valley buck regulators.Figure 7 shows the under-damped condition, with V SLOPE / T = 0.55 · V IN · R i / L.Figure 7. Emulated peak current-mode sub-harmonic oscillation. Tendency for sub-harmonic oscillation is independent of duty cycle. Even with minimal damping, it will eventually die out. Since the slope compensation requirement is independent of duty cycle, an interesting observation can be made. If the slope of the ramp is made less than 0.5 · V IN · R i / L, the circuit will exhibit sub-harmonic oscillation at any duty cycle.General Slope Compensation CriteriaFor any mode of operation (peak, valley or emulated), the optimal slope of the ramp presented to the modulating comparator input is equal to the sum of the absolute values of the inductor up-slope and down-slope scaled by the current-sense gain. This will cause any tendency toward sub-harmonic oscillation to damp in one switching cycle.For the buck regulator, this is equivalent to a ramp whose slope is V IN · R i / L.Up-slope = (V IN - V O) · R i / LDown-slope = V O · R i / LFor the boost regulator, this is equivalent to a ramp whose slope is V O · R i / L.Up-slope = V IN · R i / LDown-slope = (V O - V IN) · R i / LFor the buck-boost regulator, this is equivalent to a ramp whose slope is (V IN + V O) · R i / L.Up-slope = V IN · R i / LDown-slope = V O · R i / LTo avoid confusion, V IN and V O represent the magnitude of the input and output voltages as a positive quantity. By identifying the appropriate sensed inductor slope, it is easy to find the correct slope-compensating ramp.Sampling GainA current-mode switching regulator is a sampled-data system, the bandwidth of which is limited by the switching frequency. Beyond half the switching frequency, the response of the inductor current to a change in control voltage is not accurately reproduced. In order to quantify this effect for linear modeling, the continuous-time model of reference [2] successfully placed the sampling-gain term in the closed-current feedback loop. This allows accurate modeling of the control-to-output transfer function using the term H e (s).In order to accurately model the current loop, the unified model of reference [3] placed the sampling-gain term in the forward path. For peak or valley current-mode with a fixed slope compensation ramp, this also accurately models the control-to-output transfer function using the term F m (s).To develop the theory for emulated current-mode control, reference [1] used a fresh approach, deriving general gain parameters which are consistent with both models. In addition, a new representation of the sampling-gain term for the closed current-loop was developed, identifying limitations of the forward-path sampling-gain term.Figure 8 (a) represents the unified form of the model, with K being the feed-forward term. In (b) K n is the dc audio susceptibility coefficient from the continuous-time model. The linear model sampling-gain terms as shown in Figure 2 are defined as:np ωQ s 11)s (H ⋅+=2n2e ωs K s 1)s (H +⋅+=Tπωn =K e is a new term which emerged from the derivation of the closed-loop expression for H(s). This derivation used slope-compensation terms other than the classic fixed ramp for peak or valley current-mode. K e could be expressed asen Q ω1⋅ but this seems rather pointless, as Q e would needa value of infinity for K e = 0. To date, no method has been found which successfully incorporates K e into the open-loop expression for H p (s). Use of H p (s) is limited to peak or valley current-mode with a fixed slope-compensating ramp, for which the value of K e = 0.To place either sampling-gain term into the linear models: F m (s) = F m · H p (s) G i (s) = G i · H(s)The accuracy limit for the sampling-gain term is identified by comparing Q to the modulator voltage gain K m and the feed-forward term K. Q is directly related to the slope-compensation requirement. The derivation starts with the ideal steady-state modulator gain. The physical reason being that at the switching frequency, the relative slopes are fixed with respect to theperiod T. A change in control voltage is then related to a change in average inductor current. Any transfer function which is solely dependent on K m in the forward dc-gain path will have excellentagreement to the switching model up to half the switching frequency. Any transfer function which includes K in the forward dc-gain path will show some deviation at half the switching frequency.Figure 8. Buck regulator with sampling-gain terms. (a) Sampling gain H P(s) in the forward path.(b) Sampling gain H(s) in the closed current-loop feedback path. Simplified Transfer FunctionsNo assumptions for simplification were made during the derivation of the transfer functions. The only initial assumptions are the ones generally accepted to be valid for a first order analysis. Voltage sources, current sources and switches are ideal, with no delays in the control circuit. Amplifier inputs are high impedance, with no significant loading of the previous stage. Simplification of the results was made after the complete derivation, which included all terms. See the appendix for the complete derivation of all transfer functions.In order to show the factored form, the simplified transfer functions assume poles which are well separated by the current-loop gain. Expressions for the low frequency model do not show the additional phase shift due to the sampling effect. The control-to-output transfer function with sampling-gain term accurately represents the circuit’s behavior to half the switching frequency. The line-to-output expressions for audio susceptibility are accurate at dc, but diverge from the actual response as frequency increases.The current-sense gain R i = G i · R S , where G i is the current-sense amplifier and R S is the sense resistor.To include the sampling-gain term in the control-to-output transfer function, replace Lωs 1+with2n 2n ωs Q ωs 1+⋅+ in the low-frequency equations. This represents the closed current-loop sampling-gain term. Inclusion of this term in the line-to-output equations will not produce the same accuracy of results. For peak or valley current-mode with a fixed slope-compensating ramp, . L n ωQ ω=⋅Sampling Gain QUsing a value of Q = 0.637 will cause any tendency toward sub-harmonic oscillation to damp in one switching cycle. With respect to the closed current-loop control-to-output function, the effective sampled-gain inductor pole is given by:⎟⎠⎞⎜⎝⎛−⋅+⋅⋅⋅=1Q 41Q T 41)Q (f 2LThis is the frequency at which a 45° phase shift occurs due to the sampling gain. For Q = 0.637, f L (Q) occurs at 24% of the switching frequency. For Q = 1, f L (Q) occurs at 31% of the switching frequency. For second-order systems, Q = 1 is normally associated with best transient response. Q = 0.5 (δ = 1) is the criteria for critical damping. Using Q = 1 may make an incrementaldifference for the buck, but is inconsequential for the boost and buck-boost with the associated right-half-plane zero of ωR . For the peak current-mode buck with a fixed slope-compensating ramp, the effective sampled-gain inductor pole is only fixed in frequency with respect to changes in line voltage when Q = 0.637. Proportional slope-compensation methods will achieve this for other operating modes.To determine the effect of reducing the slope compensation in order to increase the voltage-loop bandwidth, an emulated peak current-mode buck with proportional slope-compensation (EPCM2) switching circuit was implemented in SIMPLIS. A standard type II 10MHz error amplifier was used for frequency compensation. With T/L = 5μs/5μH and R i = 0.1V/A, the best performance was achieved with Q = 0.637 for a crossover frequency of 40 kHz and 45°phase margin. By setting Q = 1 a crossover frequency of 50 kHz was achieved, again with 45° phase margin but reduced gain margin. This appears to be the practical limit for a stable voltage loop, at the expense of under-damping the current loop. With Q = 1, sub-harmonic oscillation is quite pronounced during transient response, but damps at steady state.Figure 9. Current-mode buck - evaluation of Q.Simulation ProgramsThe choice of simulation program is important, since all SPICE programs do not calculate all parameters with the same degree of accuracy. For switching-model simulation, SIMPLIS is able to produce Bode plots directly from the switching model. This was used for the switching-model results.The linear models were made with SIMetrix, which is the general purpose simulator for the SIMetrix/SIMPLIS program. This simulator only handles Laplace equations for s in numerical form, where the numerator order must be equal or less than the denominator order. PSpice is much better suited for linear models with Laplace functions in parameter form. It is moreaccurate than the SIMetrix/SIMPLIS program, but cannot produce Bode plots directly from the switching model. PSpice or a program with similar capability may be used to obtain the linear-model results.Linear ModelsThe linear models shown in Figures 22, 23 and 24 represent the state of the art in simplicity, accuracy and ease of use. Verification of each linear model has been made to results from the switching model. In this manner, validation for any transfer function is possible, identifying the accuracy limit of the linear model.Transfer Functions in Impedance FormFor all transfer functions:)R R (C s 1)R C s 1(R R ||R C s 1Z C O O C O O O C O O +⋅⋅+⋅⋅+⋅=⎟⎟⎠⎞⎜⎜⎝⎛+⋅=S L L R R L s Z ++⋅=R O represents the load resistance, while R represents the dc operating point V O / I O .For a resistive load R O = R.For a non-linear load such as an LED, R O = R D , where R D represents the dynamic resistance of the load at the operating point, plus any series resistance.For a constant-current load, R O = ∞.G V represents the error amplifier gain as a positive quantity. To find the open-loop transfer functions, let G V = 0.To include either sampling-gain term multiply K m by H P (s), or R i by H(s).Buck Regulator ExampleFor the peak current-mode buck example, comparisons of results from the switching circuit of Figure 10 were made to the linear model of Figure 22 using the sampling-gain term H p(s). In order to use the forward-path sampling-gain term, slope compensation was implemented with a fixed ramp. The results will be slightly different if a proportional ramp is used, as this modifies the modulator gain term K m and feed-forward term K.Figure 10. Buck switching modelResults for the control-to-output gain in Figure 11 show excellent agreement up to half the switching frequency. The line-to-output results in Figure 12 show some deviation due to the feed-forward term K being in the forward-gain path. Slope compensation was set for Q = 0.637. This can be seen from the current-loop crossover in Figure 13, which converges for all line voltages at 60 kHz or 30% of the switching frequency.Figure 11. Buck control-to-outputFigure 12. Buck line-to-outputFigure 13. Buck current loopBoost Regulator ExampleFor the peak current-mode boost example, comparisons of results from the switching circuit of Figure 14 were made to the linear model of Figure 23 using the sampling-gain term H p(s). In order to use the forward-path sampling-gain term, slope compensation was implemented with a fixed ramp. The results will be slightly different if a proportional ramp is used, as this modifies the modulator gain term K m and feed-forward term K. For an actual boost converter implementation with a fixed ramp, it is only possible to get the optimal Q at one input voltage.Figure 14. Boost switching modelResults for the control-to-output gain in Figure 15 show a slight deviation at half the switching frequency. The line-to-output results in Figure 16 show excellent agreement up to half the switching frequency. Slope compensation was set for Q = 0.637. This can be seen from the current-loop crossover in Figure 17, which converges for all line voltages at 60 kHz or 30% of the switching frequency.Figure 15. Boost control-to-outputFigure 16. Boost line-to-outputFigure 17. Boost current loopBuck-Boost Regulator ExampleFor the peak current-mode buck-boost example, comparisons of results from the switching circuit of Figure 18 were made to the linear model of Figure 24 using the sampling-gain termH p(s). In order to use the forward-path sampling-gain term, slope compensation was implemented with a fixed ramp. The results will be slightly different if a proportional ramp is used, as this modifies the modulator gain term K m and feed-forward term K.Figure 18. Buck-boost switching modelResults for the control-to-output gain in Figure 19 show the same slight deviation as the boost at half the switching frequency. Similar to the buck, the line-to-output results in Figure 20 show a more pronounced deviation due to K being in the forward-gain path. Slope compensation was set for Q = 0.637. This can be seen from the current-loop crossover in Figure 21, which converges for all line voltages at 60 kHz or 30% of the switching frequency.Figure 19. Buck-boost control-to-outputFigure 20. Buck-boost line-to-outputFigure 21. Buck-boost current loopCurrent-Mode BuckFigure 22. Buck linear modelLinear Model CoefficientsIN ap V V =INO V V D =IN OIN V V V D 1D −=−=′D M =OOI V R =RM V I ap C ⋅=apm m V K F =Simplified Transfer FunctionsControl-to-Output: Line-to-Output (0v ˆC =): ⎟⎟⎠⎞⎜⎜⎝⎛+⋅⎟⎟⎠⎞⎜⎜⎝⎛++⋅⋅=L P ZD i OC O ωs 1ωs1ωs 1K R R v ˆv ˆ⎟⎟⎠⎞⎜⎜⎝⎛+⋅⎟⎟⎠⎞⎜⎜⎝⎛++⋅⋅⋅⋅=L P ZD i nO IN O ωs 1ωs1ωs 1K R K D R v ˆv ˆWhere:im OD R K R 1K ⋅+=DK K 1K m n −=CO Z R C 1ω⋅=OO D P R C K ω⋅=LR K ωim L ⋅=Current-Mode Buck –Transfer Functions in Impedance FormControl-to-Output:⎟⎟⎠⎞⎜⎜⎝⎛⋅+⎟⎟⎠⎞⎜⎜⎝⎛+⋅=Oi O L mC O Z 1R Z Z 1K 11v ˆvˆLine-to-Output:V Oi O L m m IN O G Z 1R Z Z 1K 1D K K 1D vˆv ˆ+⎟⎟⎠⎞⎜⎜⎝⎛⋅+⎟⎟⎠⎞⎜⎜⎝⎛+⋅⎟⎟⎠⎞⎜⎜⎝⎛−⋅=Output Impedance:V Oi O L mi L mOO G Z 1R Z Z 1K 1R Z K 1i ˆvˆ+⎟⎟⎠⎞⎜⎜⎝⎛⋅+⎟⎟⎠⎞⎜⎜⎝⎛+⋅+⋅=′Input Impedance:⎟⎟⎠⎞⎜⎜⎝⎛⋅−+⎟⎟⎠⎞⎜⎜⎝⎛⋅+⎟⎟⎠⎞⎜⎜⎝⎛++⋅+⎟⎟⎠⎞⎜⎜⎝⎛⋅+⎟⎟⎠⎞⎜⎜⎝⎛+⋅⋅−=O m V O i O L VO i O L m2ININ Z R K 1G Z 1R Z Z R 1D K G Z 1R Z Z 1K 1D R iˆv ˆControl-to-Inductor Current:⎟⎟⎠⎞⎜⎜⎝⎛⋅+⎟⎟⎠⎞⎜⎜⎝⎛+⋅=Oi O L mOC LZ 1R Z Z 1K 1Z 1v ˆi ˆCurrent Loop (): 0vˆC =⎟⎟⎠⎞⎜⎜⎝⎛+⋅⎟⎟⎠⎞⎜⎜⎝⎛⋅−=′O L m O i LL Z Z 1K 1Z 1R i ˆi ˆCurrent-Mode BoostFigure 23. Boost linear modelLinear Model CoefficientsO ap V V =OINO V V V D −=OIN V V D 1D =−=′D 1M ′=OO I V R =RM V I ap C ⋅=apm m V K F =Simplified Transfer FunctionsControl-to-Output: Line-to-Output (0v ˆC =): ⎟⎟⎠⎞⎜⎜⎝⎛+⋅⎟⎟⎠⎞⎜⎜⎝⎛+⎟⎟⎠⎞⎜⎜⎝⎛+⋅⎟⎟⎠⎞⎜⎜⎝⎛−⋅⋅′⋅=L P Z R D i O C O ωs 1ωs1ωs 1ωs1K R D R vˆvˆ⎟⎟⎠⎞⎜⎜⎝⎛+⋅⎟⎟⎠⎞⎜⎜⎝⎛++⋅⋅⋅′⋅=L P ZD i nO IN O ωs 1ωs1ωs 1K R K D R v ˆv ˆWhere: ⎟⎟⎠⎞⎜⎜⎝⎛′+⋅′⋅++=D K K 1R D R R R 1K m i2O O D2i m n D R R K 1K ′⋅+=LD R ω2R ′⋅=CO Z R C 1ω⋅=OO D P R C K ω⋅=LR K ωim L ⋅=Current-Mode Boost –Transfer Functions in Impedance FormControl-to-Output:⎟⎟⎠⎞⎜⎜⎝⎛⋅′−⋅′⋅+⎟⎟⎠⎞⎜⎜⎝⎛+⋅+⎟⎟⎠⎞⎜⎜⎝⎛+′⋅⎟⎟⎠⎞⎜⎜⎝⎛⋅′−⋅′=R D Z 1D K Z 1R 1R Z Z D K 1R D Z 1D vˆv ˆ2L O i O L 2m 2L C OLine-to-Output:⎟⎟⎠⎞⎜⎜⎝⎛⋅′−⋅′⋅++⎟⎟⎠⎞⎜⎜⎝⎛+⋅+⎟⎟⎠⎞⎜⎜⎝⎛+′⋅⎟⎟⎠⎞⎜⎜⎝⎛⋅′+⋅′=R D Z 1D )K G (Z 1R 1R Z Z D K 1R D R K 1D vˆv ˆ2L V O i O L 2m 2i m IN OOutput Impedance:⎟⎟⎠⎞⎜⎜⎝⎛⋅′−⋅′⋅++⎟⎟⎠⎞⎜⎜⎝⎛+⋅+⎟⎟⎠⎞⎜⎜⎝⎛+′⋅+⋅=′R D Z 1D )K G (Z 1R 1R Z Z D K 1R Z K 1i ˆvˆ2L V O i O L 2mi L mOOInput Impedance:⎟⎟⎠⎞⎜⎜⎝⎛⋅′⋅−′⋅+⎟⎟⎠⎞⎜⎜⎝⎛⋅′−⋅′⋅++⎟⎟⎠⎞⎜⎜⎝⎛+⋅+⎟⎟⎠⎞⎜⎜⎝⎛+′⋅⋅⋅′−=O 2m V 2L V O i O L 2m2ININ Z R D K 1D )K G (R D Z 1D )K G (Z 1R 1R Z Z D K 1R D iˆvˆControl-to-Inductor Current:⎟⎟⎠⎞⎜⎜⎝⎛⋅′−⋅′⋅+⎟⎟⎠⎞⎜⎜⎝⎛+⋅+⎟⎟⎠⎞⎜⎜⎝⎛+′⋅+=R D Z 1D K Z 1R 1R Z Z D K 1Z 1R 1v ˆi ˆ2L O i O L 2mOC LCurrent Loop (): 0v ˆC =⎟⎠⎞⎜⎝⎛⋅′−⋅′⋅+⎟⎟⎠⎞⎜⎜⎝⎛+′⋅⎟⎟⎠⎞⎜⎜⎝⎛+⋅−=′R D Z 1D K Z Z D K 1Z 1R 1R i ˆi ˆL O L 2m O i LLCurrent-Mode Buck-BoostFigure 24. Buck-boost linear modelLinear Model CoefficientsO IN ap V V V +=OIN O V V V D +=O IN IN V V V D 1D +=−=′D D M ′=OOI V R =RM V I ap C ⋅=apm m V K F =Simplified Transfer FunctionsControl-to-Output: Line-to-Output (0vˆC =): ⎟⎟⎠⎞⎜⎜⎝⎛+⋅⎟⎟⎠⎞⎜⎜⎝⎛+⎟⎟⎠⎞⎜⎜⎝⎛+⋅⎟⎟⎠⎞⎜⎜⎝⎛−⋅⋅′⋅=L P Z R D i O C O ωs 1ωs1ωs 1ωs1K R D R vˆv ˆ⎟⎟⎠⎞⎜⎜⎝⎛+⋅⎟⎟⎠⎞⎜⎜⎝⎛+⎟⎟⎠⎞⎜⎜⎝⎛+⋅⎟⎟⎠⎞⎜⎜⎝⎛+⋅⋅⋅′⋅⋅=L P Z K D i n O IN O ωs 1ωs1ωs 1ωs1K R K D D R vˆvˆWhere: ⎟⎟⎠⎞⎜⎜⎝⎛′+⋅′⋅+⋅+=D K K 1R D R R D R 1K m i2O O D 2i m n D R DR D K K 1K ′⋅⋅+−=CO Z R C 1ω⋅=DL D R ω2R ⋅′⋅=OO DP R C K ω⋅=LR K ωim L ⋅=KL K D R ωn2K ⋅⋅′⋅=。
开关电源电流控制模式工作原理
开关电源电流控制模式工作原理Switching power supplies are widely used in various electronic devices due to their high efficiency and small size. They work by converting DC power into high-frequency AC power, which is then rectified and filtered to produce the desired output voltage. The output voltage can be adjusted by controlling the duty cycle of the switching converter.开关电源由于其高效率和小尺寸而被广泛应用于各种电子设备。
它们的工作原理是将直流电源转换为高频交流电,然后经过整流和滤波以产生所需的输出电压。
通过控制开关转换器的占空比可以调节输出电压。
One common method of current control in switching power supplies is pulse width modulation (PWM). In PWM, the width of the pulse is varied while the frequency remains constant. By adjusting the duty cycle of the pulse, the average output voltage can be controlled. This allows for precise regulation of the output current.在开关电源中,常见的电流控制方法是脉宽调制(PWM)。
在PWM中,脉冲的宽度被改变,而频率保持不变。
电源专有名词
专用名词缩写词或符号定义AAC-DC 合适的电子设备能操作于交流电流或直流电流.还有: ac dc, ac/dc, ac-dcAC-DC转换器AC-DC CONVERTER 一个把交流电转到直流电的器件,通常是指离线转换器,当中交流电压被整流为直流电,或包括功率因素校正或其它功能. 还有: ac dc 转换器, ac/dc 转换器, ac-dc 转换器交流电源正常信号AC-OK SIGNAL 该信号用于指示由115/230Vac电源输入的交流电压的导通和中断.高度测试ALTITUDE TESTING 飞机或其他飞行器中电子设备的某些功能和特性.根据军用标准MIL-STD-810,通常需要进行高度测试.环境温度AMBIENT TEMPERATURE 环境温度通常是指最贴近电源处静止空气的温度.视在功率APPARENT POWER 交流电路中功率的数值.该功率等于电路中有效值(rms)电流与有效值(rms)电压的乘积,计算该功率时,不考虑功率因数.B球式栅格阵列BALL GRID ARRAY BGA 一种普遍用于集成电路的标准表面贴装连接方法,用于板内安装VI晶片.频带宽度BANDWIDTH 确定某种现象必须考虑的频率范围.基板BASEPLATE 电源模块都有一个安装用的铝基板.怀格规定该基板的温度为模块的工作温度.该基板应加到散热器导热表面.BELLCORE技术规范BELLCORE SPECIFICATION Bellcore提出的通信工业标准.双极型晶体管BI-POLAR TRANSISTOR 利用少数载流子穿过PN结原理制成的晶体管,与电压型控制器件(如MOSFET)不同,该晶体管为电流型控制器件.泄漏电阻BLEEDER RESISTOR 为了使电容放电,在电路中可接入一只泄漏电阻,以便产生很小的漏电流.线圈骨架BOBBIN 线制变压器或电感线圈的支架.该骨架也可使线圈与铁芯绝缘.倍增器转换器模块BOOSTER CONVERTER 在驱动器/倍增器模块组合结构中,接到驱动器模块的“被控”模块.在组合结构中,多只倍增器模块可以接到一个驱动器模块上.击穿电压BREAKDOWN VOLTAGE 在该电压的作用下,电气绝缘被破坏,随之将产生较大的漏电流,甚至产生弧光火花.在电源系统中,击穿电压是指加到输入端到输出端或输入、输出端到底盘的最高交流或直流电压.桥式转换器BRIDGE CONVERTER 桥式转换器是直流—直流转换器的一种电路结构.在功率变压器两端的桥式结构中,采用两或四只有源开关器件.桥式整流器BRIDGE RECTIFIER 采用四只整流管的桥式全波整流电路.节电BROWNOUT 需求的电量超过发出的电量或配给的电量时,为了减小功耗,电力公司通常将降低交流电源配给的电压.老化BURN-IN 电源产品出厂前,为了排除元件初期故障和其他潜在的影响,通常应在额定负载下运行一段时间,这个过程称为产品老化.母线转换器模块BUS CONVERTER MODULE BCM VTM的其中一款,配合中转母线架构IBA应用而设计.BCM从一个预穏压直流来源提供隔离的中转母线电压,到非隔离负载奌转换器.BCM比传统砖型IBCs更优越.C加拿大标准协会CANADIAN STANDARDS ASSOCIATION CSA 明确规定电源组件的标准和安全规格.电容耦合CAPACITIVE COUPLING 两个电路之间通过分立电容器或寄生电容器产生的信号耦合.中心抽头CENTER TAP 在变压器或电感线圈中点引出的电气接头,通常线圈中心抽头两端的匝数应相等.C-级C-GRADE 一种工业标准,C级器件的工作温度不能低于-20˚C.底盘安装结构CHASSIS MOUNT CONFIGURATION 各种模块或交流前端电路直接装在底盘上,称为底盘安装结构.共模噪声COMMON–MODE NOISE 两导体对某个基准点具有相等的噪声,通常是指交流电源火线和中线对地的噪声.COMPAC 怀格的直流输入电源,该电源可满足工业品和通信产品对EMC滤波和瞬变保护的要求.恒流电源CONSTANT–CURRENT POWER SUPPLY 当电源电压、负载、环境温度变化或输出电压随时间变化时,输出电流保持稳定不变的电源.稳压电源CONSTANT–VOLTAGE POWER SUPPLY 当电源电压、负载、环境温度变化或输出电流随时间漂移时,输出电压保持稳定不变的电源.控制电路CONTROL CIRCUIT 闭环系统中采用的一种电路.该电路通常会有一个误差放大器,控制系统的工作,以便调整系统的状态.转换器CONVERTER 利用电感及电容滤波配合高频开关作用,而将直流输入电压转换为不同直流输出电压的电路.波峰因数CREST FACTOR 在交流电路中,波形的峰值与有效值(rms)之比.在传输功率一定的条件下,随著峰值増大,有效值(rms)也増大.因此,功耗也増大.波峰因数有时用来说明交流电源线中电流的应力.波峰因数基本上与功率因数描述的信息相同,并且、在电源术语中,可由功率因数取代.交叉调整CROSS REGULATION 一路输出端负载变化对另一路输出负载的调整作用.通常,在无二次调整(准调整)的输出电路中会产生交叉调整.急剧短路电路CROWBAR 一种过压保护方法.检测到过压故障后,为了保护负载,该电路可使电源输出端迅速短路到地.限流CURRENT LIMITING 一种过流保护电路.为了保护负载和电源,限流保护电路可以限制电源的最大输出电流.电流型CURRENT MODE 开关型转换器的一种控制方法,采用电流型控制法时,转换器通过双环控制电路,根据检测出的输出电流和输出电压调整脉冲宽度,以便稳定输出电压.电流监控器CURRENT MONITOR 可输出与输出电流成正比的模拟信号.DDC-DC转换器DC-DC CONVERTER 把直流电从一个电压转换到另一个电压的电路.还有: dc dc 转换器, dc/dc 转换器, dc-dc 转换器DC-DC电源DC-DC POWER SUPPLY 供一个或多个直流输出电压的电源系统.还有: dc dc 电源, dc/dc 电源, dc-dc 电源直流电源正常信号DC-OK SIGNAL 监控直流输出状态的信号.降额DERATING 为了提高可靠性而降低运作规格.在电源系统中,当环境温度较高时,为了安全工作,通常需要降低输出功率.设计寿命DESIGN LIFE 预期的电源工作寿命.在这个时间内,电源运作应符合标定的技术要求.差模噪声DIFFERENTIAL MODE NOISE 排除共模噪声后,在两条电源线之间测出的电源线对公共基准点的噪声.测试结果为两电源线的噪声分量之差.在电源系统中通常在直流输出端和直流返回端测试噪声.分布式电源结构DISTRIBUTED POWER ARCHITECTURE 中心电源向各个临近负载供电的电源结构.常采用直流供电.漂移DRIFT 当电源电压、负载和工作温度等参数保持不变的情况下,在预热过程后,输出电压随时间的变化称为漂移.驱动器模块DRIVER MODULE 在单独的或驱动器/倍増器模块组合结构中的主控模块.驱动器模块中含有全部控制电路.跌落电压DROPOUT 交流输入电压下限,输入电压低于该值后,输出电压就不能稳定.在线性电源中,跌落电压主要决定于电源输入电压;在大部分开关电源中,跌落电源主要决定于负载电流,输入电压的影响较小.动态负载调整率DYNAMIC LOAD REGULATION 输出电流迅速变化时,输出电压产生的变化.E效率EFFICIENCY 用百分数表示的总输出功率与输入功率之比.通常规定,在额定输入电压和75%负载状态下,量度或标示.电子负载ELECTRONIC LOAD 接到电源输出端作负载用的一种电子器件.该负载通常可动态变化,频密改变或由计算机控制.电磁兼容性ELECTROMAGNETIC COMPATIBILITY EMC 关于电磁波之发射及感受性标准.电磁干扰ELECTROMAGNETIC INTERFERENCE EMI 这是电源或其他电子、电气设备工作过程中产生的有害噪声.等效串联电阻EQUIVALENT SERIES RESISTANCE ESR 与理想电容器串联的电阻值.它能反映真实电容器的特性.F分比式母线FACTORIZED BUS Vf 由PRM或直流—直流转换器产生的输出电压,并可被调节来控制一个或多个VTMs产品的稳定或变化.分比式功率结构FACTORIZED POWER ARCHITECTURE FPA FPA(分比式功率架构)为一个创新的功率分布架构,该架构把通常用在分布式功率架构的DC-DC转换器的传统功能分为稳压及隔离/电压转变组件.虽然“纯粹”的分比式功率架构(FPA)应由各种V•I晶片(VIC)构成,但传统的功率产品,如DC-DC转换器、非隔离负载点转换器及开关器也可构成FPA系统的部份.故障容错结构FAULT TOLERANT CONFIGURATION 采用幷联工作电路时,接入输出隔离二极管后,单个电源(模块)的故障不会使电源系统的输出电压中断.在这种结构中,单个电源发生故障时,幷联系统的总输出电流不能小于负载要求的电流,也就是说,单个电源发生故障后,幷联系统不能出现过载现象.场效应晶体管FIELD EFFECT TRANSISTOR FET 多数载流子—电压控制型晶体管.FINMOD 怀格VI系列变换器模块及相关模块采用的无凸缘且带有散热片的封装形式.FLATPAC 怀格生产的具有1路、2路或3路输出电压的AC-DC开关电源.额定输出功率为50-600W.悬浮输出FLOATING OUTPUT 电源一个输出端的电压,不以另外任何一个输出端为基准,通常表示各输出端全部隔离.悬浮输出电源可以输出正电压,也可以输出负电压.非悬浮输出电源有一个公共返回线,因此,一个输出端的直流电压都以另一个输出端为基准.折返限流FOLDBACK CURRENT LIMITING 一种过流保护方式.采用折返限流方式时,当负载电流达到一定数值后就开始下降,当负载接近短路状态时,输出电流下限到最小值.正激变换器FORWARD CONVERTER 一种变换器电路.在该电路中,当变压器初级开关元件导通时,输入能量传输到输出端.G门极输入GATE IN 模块上的Gate In脚可用来开通或关断模块.当Gate In为低电平时(到-Vin脚的电压小于1V、电流为4mA),模块关断;当Gate In 脚悬空时(开路集电极),模块导通.Gate In脚到-Vin脚开路电压都低于10V.在驱动器模块和倍增器模块组合结构中,必须连接Gate In和Gate Out 脚.门极输出GATE OUT Gate Out脚为转换器的时钟脉冲输出脚.在大功率阵列中,该脚信号可使倍增器模块与驱动器同步运行.接地GROUND 接地或接到其他接地导体上.有时“ground”用于表示公共接点.但是除非公共接点接地,这种用法是错误的.接地回路GROUND LOOP 这是两个或多个电路共同一个接地点而产生的有害反馈回路.H迭加正弦波HAVERSINE 该波形基本为正弦波特性,但它是迭加在其他波形上的正弦波部分.典型离线式电源的输入电流波形即为这种波形.输入、输出电压差HEADROOM 用于有关串联导通稳压电源情形,它表示输入电压与输出电压之差.散热片HEATSINK 散热片为一大热容量物料,幷可以有限地吸收热量,幷且温度基本上保持不变.怀格电源模块不一定需要这种散热片,它主要用于大功率电源和环境温度较高的设备中.最高电源输入电压HIGH LINE INPUT 输入脚可加入的最高稳态输入电压.高压(HIPOT)HIGH POTENTIAL (HIPOT) 高压通常用于按管理机构提出的点气安全要求测试绝缘耐压能力.保持电容器HOLDUP CAPACITOR 该电容的贮能可在输入电压中断后的一段时间内,保持输出电压.保持时间HOLDUP TIME )很小,所以,维持时间很短.在开关型 交流输入电源发生故障后.电源能够保持输出电压不变的时间.在线性稳压电源中,次级低压输出电容器的贮能(CV电源中,初级高压电容器的贮能较大,所以保持时间较长.热插拔HOT SWAP 在通电的系统中将电源插入或拔出.II-GRADE 一种工业标准.I-级器件的工作温度不能低于-40˚C.阻抗IMPEDANCE 在规定频率下,电压与电流之比.减应噪声INDUCED NOISE 磁场变化,通过其他电路在该电路中产生的噪声.输入电源滤波器INPUT LINE FILTER 电源内部外接的低通或带阻滤波器,该滤波器可衰减进入电源的噪声.输入浪涌电流INRUSH CURRENT 电源接通瞬间,流入电源设备的峰值电流.由于输入滤波电容迅速充电,所以该峰值电流远远大于稳态输入电流.浪涌电流限制INRUSH CURRENT LIMITING 电源接通瞬间,限制输入浪涌电流的电路.中转母线结构INTERMEDIATE BUS ARCHITECTURE IBA 这结构的特点是使用中转母线转换器(IBC),在板上转换较低压的分布电压,并连接非隔离负载点转换器(niPOLs)为负载供电.中转母线转换器INTERMEDIATE BUS CONVERTER IBC 市面上多个制造商,IBC一般是指从预稳压直流母线转变到非稳压和隔离中转电压的砖型转换器.一般的中转电压是12、8、5或3Vdc,典型负载是非隔离负载点转换器(niPOLs).绝缘ISOLATION 两电路之间的直流电压和交流电压完全隔离.在电源设备中,输入端与输出端通过变压器隔离.绝缘电压ISOLATION VOLTAGE 可连续加到电源输入端到输出端和输入、输出端到底盘的最高交流或直流电压.L漏电流LEAKAGE CURRENT 流过交流电源线和接地线之间的电流.出现漏电流不一定是故障状态.在电流设备中,漏电流指流过接在交流电源线和接地线之间的EMI滤波电容器(Y电容)的60Hz漏电流.线性稳压器LINEAR REGULATOR 在这种稳压器中,输入和输出端之间串入有源器件,比如晶体管,通过改变串联调整管的压降来稳定输出电压.电源电压调整率LINE REGULATION 交流输入电压从最低值变到规定的最大值时,输出电压的变化.交流电源电压(Mains)LINE VOLTAGE (Mains) 加到电源设备输入端的正弦波电压,该电压通常用有效值表示.负载调整率LOAD REGULATION 输出负载电流改变时,输出电压的变化.本机取样LOCAL SENSING 用电源设备输出端的电压作调整输出电压的取样电压.长期稳定性LONG TERM STABILITY 在所有其他因素保持不变的条件下,电源设备输出电压随时间的变化.该性能用百分数表示,幷且随元器件的老化程度而变.最低电源电压LOW LINE 能够维持变换器输出电压稳定的最低稳态输入电压.M电力线MAINS 通用交流电源线.MARGINING 为了验证电源电压变化时,电源系统性能的极限,电源输出电压需要从额定值调高或调低到极限值.通常利用系统中的控制信号调整电源输出电压.MEGA MODULES 采用底盘安装式封装的模块,该模块包含1个、2个或3个VI-200系列变换器模块,有1路、2路或3路输出电压,输出功率可达到600W.M-级M-GRADE 一种工业标准.为了满足M级标准,器件的工作温度不能低于-55˚C军规标准MIL SPECS 在军用环境内使用的器件所必须满足的标准.小型MINIMOD 输出功率达VI-200系列DC-DC变换器模块的一半的小型封装(VI-J00)模块,它的体积为2.28英寸(L)x2.4英寸(W)x0.5英寸(H). 最小负载电流MINIMUM LOAD 为了满足技术要求,电源设备应具有的最小负载电流或最小功率.为了防止电源设备发生故障,电源频率不能过低,负载电流也不能过小.模块评估板MODULE EVALUATION BOARD 用于评估怀格直流模块的测试装置.怀格可提供交流和直流输入的评估板.平均无故障时间(MTBF)MEAN TIME BETWEEN FAILURE MTBF 平均无故障时间(MTBF)是产品总数的63%不再满足技术要求的时间.MTBF可以计算,也可以论证.通常都是按MIL-STD-217修订版E介绍的方法计算.也可由温度加速寿命试验来论证.论证的MTBF通常比计算出的MTBF长.N额定输入电压NOMINAL INPUT 输入电压范围的中间值.额定值NOMINAL VALUE 一种常见的数值、平均值、额定值或要求的工作条件.该数值通常不等于实际测试出的数值.非隔离负载点转换器(niPOLs)NON-ISOLATED POINT-OF-LOAD CONVERTER niPOL 典型的非隔离负载点转换器(niPOLs)是从中转母线转换为低电压输出的补偿转换器.市面上有多个制造商及多款规格.O离线OFF LINE 电源设备的输入功率直接由交流电源供给.整流和滤波电路以前,无采用50Hz/60Hz电源变压器,这种电源称为离线式电源.开放式框架OPEN FRAME 一种无金属外壳的电源设备.该电源是一种可直接应用的带有机座、安装元件和各种接头的印刷电路板.工作温度OPERATING TEMPERATURE 在工作温度范围内,电源能够满足技术规范的要求.光电隔离器OPTOISOLATOR 一种光电器件,它可以传输隔离直流电路两边的信号.或门二极管OR’ING DIODES在故障状态下,使一台电源与另一台电源隔离的二极管.输出滤波OUTPUT FILTERING 用于衰减开关电源输出纹波和噪声的滤波器.输出电压正常OUTPUT GOOD 一种电源状态信号,它可以指示输出电压在规定的允许偏差以内,当输出电压过高或过低时,输出电压正常信号将消失.输出阻抗OUTPUT IMPEDANCE 输出电压的増量与负载电源増量之比.OUTPUT NOISE 电源直流输出端出现的交流分量.开关型电源输出噪声通常可分为两部分:频率与变换器开关频率相等的低频噪声和变换器开关快速转换产生的高频噪声.用示波器检测该噪声时,必须用极短的接地经探头直接在输出端量度.额定输出功率OUTPUT POWER RATING 在保持安全机构认证的条件下,电源的最大输出功率(W).输出电压精度OUTPUT VOLTAGE ACCURACY 请参看“设定精度”过载保护OVERLOAD PROTECTION 过载状态下限制输出电流的一种电源保护电路.过冲OVERSHOOT 电源接通或关断时,或者电源电压和负载突变时,瞬时输出电压超过规定的最高极限.过热告警OVERTEMP WARNING 一种TTL兼容信号,它指示电源出现过热状态.过压保护OVERVOLTAGE PROTECTION OVP 一种电源保护电路,当输出电压过高时,该电路可以关断电源或者将电源输出端与地短路.P幷联倍增PARALLEL BOOST VI-200驱动器模块可以与多只倍增器模块幷联输出几千瓦的功率.倍增器模块内没有任何反馈或控制电路.幷联工作PARALLEL OPERATION 为了输出更大的电流,两台或多台电源的输出端可以接在一起.幷联时,每台电源都必须具有负载均流功能.周期或无规律偏移PERIODIC AND RANDOM DEVIATION PARD 它是电源直流输出端所有纹波和噪声分量之和,不管其本质或根源.峰值功率PEAK POWER 在不会直接损坏的情况下,电源可输出的绝对最大功率.峰值输出功率典型值都超过连续输出功率,但是,平均功率不能超过额定功率.PI型滤波器PI FILTER 为了减小反射纹波电流,在开关电源或DC-DC变换器输入端常用的一种滤波器,该滤波器通常由两只电容器和一只电感组成.电感接在两只幷联电容器之间.二次稳压POST REGULATOR 电源辅助输出端的二次稳压电路.该电路可输出更加稳定的电压.功率转换POWER CONVERSION 是把功率从一个形式转换成另一个形式的过程.电源故障POWER FAIL 一种电源接口告警信号,该信号表示输入电压将不再能维持满载稳定输出电压.功率因数POWER FACTOR 交流电路中,真实功率与视在功率之比.在功率变换技术中,功率因数常用于描述电源的交流输入电流.供电器POWER SUPPLY 一个电能来源,为电子电路导管或半导体器件提供适当的电压及电流以供操作.预置负载PRELOAD 为了使电源稳定工作,电源可能需要驱动一定的负载.通常电源供给该负载的电流很小.预稳压模块PRE-REGULATOR MODULE PRM V•I晶片(VIC)的其中一款,它把范围广阔(宽度可达5:1)的非穏定直流母线(即36-75V母线常用于48V电讯系统),转换为分比式母线输出来推动VTMs或其它FPA产品.PRM是一个非常高效率(可达至99%)非隔离的降压/升压转换器,也能操控分比式母线.PRIMARY 隔离电源的输入部分,它接到交流电源,因此带有危险的高电压.产品等级PRODUCT GRADE 怀格产品的等级.由环境和验收测试表现決定.脉冲宽度调制PULSE WIDTH MODULATION PWM 一种开关电源变换技术.采用这种技术时,开关管的导通时间(或宽度)由负回输电路控制,使输出保持稳定. 推挽变换器PUSH-PULL CONVERTER 一种开关电源电路结构.该电路由一个带中心抽头的变压器和两只功率开关管组成,两只功率开关管交替导通与关断. Q准稳输出电压QUASI-REGULATED OUTPUT 辅助输出电压是通过调整主输出电压来调整的.与所需辅助输出电压相应的变压器的匝比和主控闭环回路的输出电压共同控制辅助输出电压.因此,在变换器中准稳输出电压将受二次调整的影响.R额定输出电流RATED OUTPUT CURRENT 在规定环境温度下,电源可输出的最大负载电流.反射纹波电流REFLECTED RIPPLE CURRENT 电源输入端的有效值(rms)或峰-峰值交流纹波电流,该电流是由变换器的开关频率造成的.调整率REGULATION 根据输入电压和负载的变化,电源将输出电压维持在规定范围的能力.调整范围REGULATION BAND 输出电压允许的变化范围.输出电压的变化应考虑所有参数:电源电压、负载、温度和时间等的影响.规管机构REGULATORY AGENCIES CSA:Canadian Standards Association(加拿大标准协会);FCC:Federal Communications Commission(美国联邦通信委员会);FTZ:Fernmelde Technisches Zentralamt;TÜV:Technischer Überwachungs Verein;U.L.:Underwriters Laboratory(保险商实验室);VDE:Verband Deutscher Electrotechniker.遥控关闭REMOTE INHIBIT 一种与TTL信号兼容的电源接口信号,它可以关断电源的一路输出或全部输出.遥控导通或关断REMOTE ON/OFF 遥控电源接通或关断.该控制脚开路或接入TTL高电平“1”时,电源接通;该控制脚到地的开关闭合或该脚接入TTL低电平“0”时,电源关断.遥控取样REMOTE SENSE 在电源输出电缆两端,接入两条取样线,可以检测负载两端的实际电压.这样,可以补偿输出电缆和隔离器的压降.返回RETURN 电源输出的公共端.输出电流从该端返回.电压反接保护REVERSE VOLTAGE PROTECTION 反向电压加到电源输入端或输出端时,电压反接保护电路可防止损坏电源.射频干扰RADIO FREQUENCY INTERFERENCE RFI 在射频干扰的作用下,电源或其他电子电气设备将产生噪声.在电源技术中,RFI和EMC相同.纹波和噪声RIPPLE AND NOISE 电源直流输出端交流分量的幅值,通常用峰-峰值或有效值(rms)表示.在线性电源中,该交流分量的频率与交流电源的频率相同.在开关电源中,该交流分量的频率是开关频率.S安全接地SAFETY GROUND 旁路到地的导电通路.该通路可将错误操作或偶然事故引起的全部危险电流旁路到地,从而防止人员遭受电击.SECONDARY 隔离电源的输出部分.该部分与交流电源隔离,因而保证人员在带电系统中工作时的安全.安全超低电压SAFETY EXTRA LOW VOLTAGE SELV 安全机构将该电压定义为:人员可以触及幷且不会引起伤害的最高电压,该电压的数值为30Vac或42.4Vdc.设定精度SETPOINT ACCURACY 实际输出电压与规定输出电压的比值.排列程序SEQUENCING 在多路输出的电源中,建立各输出电路供电顺序的方法.软起动SOFT START 刚接通电源后,电源设备的输出电压逐渐上升.采用这种方法可以限制输入浪涌电流.高阻抗电源SOFT LINE 具有较大阻抗的交流电源.当负载增加时,电源设备的输入电压将显著下降.分裂线圈架绕组SPLIT BOBBIN WINDING 一种变压器的绕线方法.采用这种方法时,变压器的初次级线圈幷排绕在一个线圈架上,幷且两个线圈之间应加绝缘隔板.静态电流STANDBY CURRENT 输入控制信号(遥控关闭)使电源设备关断时,或在空载状态下,电源设备的输入电流.低阻抗电源STIFF LINE 阻抗很小的交流电源.当负载变化时,电源设备的输入电压不会发生明显变化.开关频率SWITCHING FREQUENCY 在开关电源中,直流电压接通和关断的速度.T温度系数TEMPERATURE COEFFICIENT 环境温度系变化1˚C,平均输出电压变化的百分数.该温度系数只有在规定的温度范围内才有效.温度降额TEMPERATURE DERATING 当温度升高时,为了使电源穏定工作,应当降低电源额定输出功率.导热垫THERMAL PAD 石墨层压板,是变换器与散热器或机架之间的传导介面.过热保护THERMAL PROTECTION 一种电源保护电路.当电源内部温度过高时,该电路可以关断电源.结构TOPOLOGY 变换器的设计类型.它表明晶体管的配置、变压器的应用和滤波器的类型等.常用变换器的结构有反激式、正激式、半桥式、全桥式、谐振式和零电流开关变换器.跟踪TRACKING 多路输出电源的一种特性.在多路输出的电源中,电源电压、负载和温度变化引起的一路输出电压的任何变化都与其他各路输出电压的变化成正比.瞬变恢复时间TRANSIENT RECOVERY TIME 电源电压或负载突变后,输出电压恢复到规定精度极限以内所需的时间.真实功率TRUE POWER 在交流电路中,真实功率就是实际消耗的功率,它与视在功率不同,真实功率中不包含无功分量.U突降UNDERSHOOT 输入电源接通或关断时,或者电源电压、或负载突变时,瞬时输出电压达不到规定电压范围的下限值.。
摩尔利斯电子MP2155单导线涨跌调压器产品说明书
M P S C O N F I D E N T I A L U S E R E L E C T R O N I C S E R N A L U S E O N L Y O T D I S T R I B U T EMP2155High EfficiencySingle Inductor Buck-Boost ConverterDESCRIPTION The MP2155 is a highly efficient, low quiescent current Buck-Boostconverter, which operates from input voltage above, below and equal to the output voltage. The device provides power solution for products powered by a one-cell Lithium-Ion or multi-cell alkaline battery applications where the output voltage is within battery voltage range.The MP2155 uses a current mode, fixed frequency PWM control for optimal stability and transient response. The fixed 1MHz switching frequency and integrated low R DS(ON) N-channel and P-channel MOSFETs minimize the solution footprint while maintaining high efficiency.To ensure the longest battery life MP2155 has an optional pulse skipping mode that reduces switching frequency under light load conditions. For other low noise applications where variable frequency power save mode may cause interference, the logic control input MODE pin forces fixed frequency PWM operation under all load conditions.The MP2155 operates with input voltage from 2V to 5.5V to provide adjustable output voltage (1.5V to 5V). With an input from 2.7V to 5.5V it can supply a maximum 1A current to load at 3.3V output voltage. The MP2155 is available in small QFN10-3x3mm package.FEATURES∙ High Efficiency up to 95%.∙ Load Disconnect During Shutdown∙ Input Voltage Range: 2V to 5.5V∙ Adjustable Output Voltage from 1.5V to 5V ∙3.3V/1A Load Capability from 2.7V-to-5.5V Vin∙1MHz Switching Frequency∙ Pulse Skipping Mode at Light Load ∙ Typical 80μA Quiescent Current ∙ Internal Loop Compensation for Fast Response∙ Internal Soft Start ∙ OTP, Hiccup SCP∙ Available in Small 3x3mm QFN10 Package APPLICATIONS∙ Battery-Powered Products ∙ Portable Instruments ∙ Tablet PCs ∙ POS Systems ∙ GSM/GPRS ∙System ControlsAll MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance.“MPS” and “The Future of Analog IC Technology ” are Registered Trademarks of Monolithic Power Systems, Inc.M P S C OM O U S E R E I N T E R N A L L Y D O N O T D I S T U T EMPS CONFIDENTIAL AND PROPRIETARY INFORMATION - MOUSER ELECTRONICS INTERNAL USE ONLYORDERING INFORMATION* For Tape & Reel, add suffix –Z (e.g. MP2155GQ –Z);PACKAGE REFERENCEABSOLUTE MAXIMUM RATINGS (1)IN to GND .................................... –0.3V to 6.5V SW1/2 to GND ...... –0.3V(-2V for <10ns) to 6.5V All Other Pins .............................. –0.3V to 6.5 V Junction Temperature .............................. 150︒C Lead Temperature ................................... 260︒CContinuous Power Dissipation (T A = +25°C) (3)QFN10 3X3mm .......................................... 2.5W Storage Temperature ............... -65︒C to +150︒CRecommended Operating Conditions (4)Supply Voltage V IN ............................ 2V to 5.5V Output Voltage V OUT .......................... 1.5V to 5V Operating Junct. Temp. (T J ) .... –40︒C to +125︒CThermal Resistance (5)θJA θJC3X3 QFN10 ............................ 50 ...... 12 ... ︒C/WNotes:1) Exceeding these ratings may damage the device2) The maximum allowable power dissipation is a function of themaximum junction temperature T J (MAX), the junction-to-ambient thermal resistance θJA , and the ambient temperature T A . The maximum allowable continuous power dissipation at any ambient temperature is calculated by P D (MAX) = (T J (MAX)-T A )/θJA . Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage.3) The device is not guaranteed to function outside of itsoperating conditions.4) Measured on JESD51-7, 4-layer PCB.M P SM O U S E I N T E R N D O N O T ELECTRICAL CHARACTERISTICSV = V =V =3.3V, T = 25 C, unless otherwise noted.Notes:5) Guaranteed by engineering sample Characterization, not tested in production.SI D EN L R O N I C S N N L Y T ETYPICAL CHARACTERISTICSV IN = 3.3V, V OUT = 3.3V, L = 3.3µH, C OUT =2x22uF, T A = +25ºC, unless otherwise noted.SERRINTEDTYPICAL PERFORMANCE CHARACTERISTICSV IN = 3.3V, V OUT = 3.3V, L = 3.3µH, C OUT=2x22uF, T A = +25ºC, unless otherwise noted.M P S C O N F IM O U S E R E L E C T I N T E R N A L U S E D O N O T D I S T R I B ETYPICAL PERFORMANCE CHARACTERISTICS (continued)V IN = 3.3V, V OUT = 3.3V, L = 3.3µH, C OUT =2x22uF, T A = +25ºC, unless otherwise noted.Notes:6) Tested with 1.8A inductor peak current at 3.3V input point. Under other V IN conditions, it takes the same current limit variation trend withV IN into consideration as “Current Limit vs. Input Voltage” curve show s"M P S C ON F I D E N T I A L M O U S E R E L E C T R O N I C S I N T E R N A L U S E O N L Y D O N O T D I S T R I B U T ETYPICAL PERFORMANCE CHARACTERISTICS (continued)V IN = 3.3V, V OUT = 3.3V, L = 3.3µH, C OUT =2x22uF, T A = +25ºC, unless otherwise noted.M P S C ON F I D E N T I A L M O U S E R E L E C T R O N I C S I N T E R N A L U S E O N L Y D O N O T D I S T R I B U T ETYPICAL PERFORMANCE CHARACTERISTICS (continued)V IN = 3.3V, V OUT = 3.3V, L = 3.3µH, C OUT =2x22uF, T A = +25ºC, unless otherwise noted.M P S C ON F I D E N T I A L M O U S E R E L E C T R O N I C S I N T E R N A L U S E O N L Y D O N O D I S T R I B U T ETYPICAL PERFORMANCE CHARACTERISTICS (continued)V IN = 3.3V, V OUT = 3.3V, L = 3.3µH, C OUT =2x22uF, T A = +25ºC, unless otherwise noted.M P S C O N F I D E N T I A L M O U S E R E L E C T R O N I C S I N T E R N A L U S E O N L Y D O N O T D I S T R I B U T ETYPICAL PERFORMANCE CHARACTERISTICS (continued)V IN = 3.3V, V OUT = 3.3V, L = 3.3µH, C OUT =2x22uF, T A = +25ºC, unless otherwise noted.M P S C OM O U S E R E L I N T E R N A L U D O N O T D I S T PIN FUNCTIONSM P S CM O U S E R I N T E R N A L D O N O T D I SFigure 1— Function Block DiagramM PF I D E N T I A L M O U S E C T R O N I C S I N T E R L U S E O N L Y D O N O T D I S T R I B U T EOPERATIONThe MP2155 is a high efficiency, dual mode buck-boost converter that provides output voltage above, equal to or below the input voltage. When the MODE pin is held high, the MP2155 operates in constant-frequency PWM mode with peak current mode control. As shown in Figure 1, the output voltage is sensed via the FB pin through an external resistor-divider from the output to ground. The voltage difference between FB pin and the internal reference is amplified by error amplifier to generate control signal V C-Buck . By comparing V C-Buck with internal compensation ramp (the sensed SWA’s current with slope compensation) through Buck comparator, a PWM control signal for PWM buck mode is outputted. Another control signal V C-Boost is derived from V C-Buck through level shift. Similarly, V C-Boost compares with the same ramp signal through Boost comparator and generates the PWM control signal for PWM boost mode. The switch topology for the buck-boost converter is shown in Figure 2.Figure 2—Buck-Boost Switch TopologyBuck Region (Vin > Vout)When the input voltage is significantly greater than output voltage, which means the converter can deliver energy to load within the maximum duty cycle of SWA, so the converter operates in buck mode. The control signal V C-Boost is always lower than compensation ramp because Buck can deliver enough energy to load, thus switch D turns on constantly and switch C remains off. Meanwhile, V C-Buck compares with compensation ramp normally and generates PWM signal, therefore, switches A and B are pulse-width-modulated to produce the required duty cycle to support the output voltage.Buck-Boost Region (Vin ≈ Vout)When Vin is close to Vout, due to duty cycle limit of SWA the converter isn’t able to provide wanted energy to load. In this case SWA will be turned on over all the period, that is, there is no BD operation(SWB and SWD being turned on simultaneously). Now a new period begins. Since there is no BD in last period, an offset voltage is added to the ramp signal to make the ramp signal easily hit V C-Buck . At the same time due to loop regulation V C-Boost (as well as V C-Buck ) rises to some level, so that the ramp signal can intersect it to produce the PWM driving signal for Boost operation. After SWC is turned off the ramp signal continues rising (the actual inductor current may rise or fall depending on the difference between Vin and Vout), when the ramp intersects V C-Buck , PWM signal for Buck operation then is generated . Now the buck’s duty cycle is within its limit, so there is BD operation in current period, which means next period the offset voltage will be removed. This is the so-called buck-boost region. With heavy load due to voltage drop on switches the actual input range for this region may be a little wide.Boost Region (Vin < Vout)When the input voltage is significantly lower thanoutput voltage, the converter operates in boost mode. The control signal V C-Buck is always higher than compensation ramp even with the offset voltage always added, thus switch A turns on continuously and switch B remains off. Meanwhile, V C-Boost compares compensation ramp normally and generates PWM signal, therefore, switches C and D are pulse-width-modulated to produce the required duty cycle to support the output regulation voltage.PSMWhen Mode Pin is pulled down below the low level threshold, the MP2155 will automatically enter PSM if load is light. When working in PSM, a train of SW pulses are initiated by a Boost operation, and ended with BD operation. During this process, SWD will be turned off if inductor current is below about 100mA. In actualM P S C O N F I D E N T I A L M O U S E R E L E C T R O N I C S I N T E R N A L U S E O N L Y D O N O T D I S T R I B U T Ewaveforms the current may be much lower than this value when SWD is turned off because of internal delay.SCP/OCP vs. two current limitsThere are two current limits in MP2155. The primary one is for steady PWM opera tion and it’s typically from 2A to 3A, depending on Vin; The secondary one is for limiting inrush current at startu p, it’s typically 1.6A to 1.9A, depending on Vin, too. When load is over heavy, the primary limit would protect MP2155 from being over thermal. Therefore Vout would drop due to OCP. If Vout drops below 0.6 times normal output, a hiccup period is initiated to protect MP2155. this is the SCP. In hiccup period, SWA and SWC are turned off while SWB and SWD are turned on. After the hiccup period ends, a soft re-startup begins. Because Vout is below 1V (due to over load or output short), the secondary current takes charge of this process. After Vo rises above 1V, primary current limit get in charge of. Now if load is still over heavy (or output short still exists) such that after SS ends Vout is still below 0.6*V OUT_NORMAL and current hits one of the limits, another hiccup period begins. However if the load recovers to normal value during re-startup so that current doesn’t hit its limit, or, Vout already rises above 0.6*V OUT_NORMAL , the re-startup succeeds, and MP2155 enter normal operation.As to the input/EN startup, the cases are same as the SCP recovery process.EnableThe MP2155 has a dedicated enable control pin (EN). The device operates when it is set high. If it is set low the device stops switching, all the internal blocks are turned off. Tie EN to Vin through a resistor for automatic start up. Due to EN bias or leakage current, the value of this resistor should be set to provide EN pin with a current above 10uA. Any signal to drive this pin should be limited to 100uA if the maximum voltage of this signal is above 6.5V.Internal Soft-start When EN pin is pulled high, and at the same time the voltage on Vcc pin is above its UVLO rising threshold MP2155 will start up with Soft-start function to eliminate output overshoot. Soft-start also functions during SCP recovery.Under-Voltage Lockout The under voltage lockout (UVLO) is implement to protect the device from improper operating at insufficient supply voltage. When the supply voltage at VCC is below the UVLO threshold the device is in shutdown mode. The UVLO rising threshold is about 1.8V with 200mV hysteresis. Over-Temperature ProtectionAn internal temperature sensor continuously monitors the IC junction temperature. If the IC temperature exceeds 160ºC typically the device stops operating. As soon as the temperature falls below 140 ºC typically normal operation is restored.M P S C O N F I D E N T I A L M O U S E R E L E C T R O N I C S I N T E R N A L U S E O N L Y D O N O T D I S T R I B U T EAPPLICATION INFORMATIONSetting the Output VoltageTo use MP2155 correctly, A resistor divider must be connected between Vout and GND, and the middle point of the divider connected to FB pin as shown in Typically Application on page 1. 2R )1V V(1R FBOUT ⨯-= (1)High R2 resistance (eg. 100k Ω) can reduce the power consumption, while lower than 1M Ω resistance is recommended for R1 for good output accuracy.Inductor SelectionThe inductor is the key passive component for switching converters. With a buck-boost device, the inductor selection affects the boundary conditions in which the converter works, as buck at the maximum input voltage and as a boost at the minimum input voltage.Two critical inductance values are then obtained according to the following formulas. L REQ )M AX (IN OUT )M AX (IN OUT BUCK M IN I F V )V V (V L ∆⨯⨯-⨯=-(2) LREQ OUT )M IN (IN OUT )M IN (IN BOOST M IN I F V )V V (V L ∆⨯⨯-⨯=-(3)Where:F REQ : minimum switching frequency∆I L : the peak-to-peak inductor ripple inductor current. As a rule of thumb, the peak-to-peak ripple can be set at 10%-20% of the output current.The minimum inductor value for the application isthe higher one between Equation 2 and Equation 3. In addition to the inductance value the maximum current the inductor can handle must be calculated in order to avoid saturation.LF V 2)V V (V I I REQ )M AX (IN OUT )M AX (IN OUT OUT BUCK PEAK ⨯⨯⨯-⨯+η=- (4) LF V )V V (V V I V I REQ OUT )M IN (IN OUT )M IN (IN )M IN (IN OUT OUT BOOST PEAK ⨯⨯-⨯+⨯η⨯=-(5) Where η is the estimated efficiency of MP2155.The maximum of the two values above must be considered when selecting the inductor.Input and Output Capacitor SelectionIt is recommended to use ceramic capacitors with low ESR as input and output capacitors in order to filter any disturbance present in the input line and to obtain stable operation.Minimum values of 10uF for both capacitors are needed to achieve good behavior of the device. The input capacitor must be placed as close as possible to the device.Other ConsiderationMP2155 employs the classic hiccup mode for SCP. This method has an inherited drawback: if the output short is released at a time closed to SS end, then Vo would has overshoot. To attenuate Vo overshoot at SCP recovery, a forward RC series can be connected in parallel with high side resistor of FB divider, as R3 and C5 in Figure 5 shows. The RC acts as a soft startup when Vo short is released at the time of internal SS’s end.PCB Layout Guide1. Input and output capacitors should be close to MP2155’s Vin, Vout and PGND pins.2. The wire connecting input capacitor to Vcc pin should be as short as possible. For better performance in noisy environment, an additional capacitor very close to Vcc pin can be used to bypass noise for Vcc.FT I A M T N I C I N U S E O Y D O D I S T R I B U 3. FB resistor divider should be very close to FB pin, and keep FB trace far away from noise.Figure 3 shows an example of PCB layout for which the reference schematic is shown on Figure 4.Top LayerBottom LayerFigure 3—PCB LayoutFigure 4—Reference Circuit for PCB GuideDesign ExampleBelow is a design example following the application guidelines for the specifications:The detailed application schematic is shown in Figure 5 and its performance can be found in TPC section.F I M C I N E D O I B TYPICAL APPLICATION CIRCUITS3.3uHL1 3.3uHFigure 5—3.3V Output Application Circuit 3.3uHGNDFigure 6—5V Output Application CircuitO EM E L T R I N U O D O D I S T U T NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications.PACKAGE INFORMATIONQFN10 (3mmX3mm)SIDE VIEW TOP VIEW BOTTOM VIEWPIN 1 ID RECOMMENDED LAND PATTERNNOTE:1) ALL DIMENSIONS ARE IN MILLIMETERS .2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH . 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX . 4) DRAWING CONFORMS TO JEDEC MO -229, VARIATION VEED-5. 5) DRAWING IS NOT TO SCALE .PIN 1 ID OPTION B PIN 1 ID OPTION A DETAIL APIN 1 ID。
Control mode
e.g. Elevators, positioning drives, main rolling mill drives
Control mode 控制模式 Closed-loop speed control with V/Hz characteristic :P100=0
Control mode 控制模式 V/Hz control without speed actual value acquisition:P100 = 1
Speed controller
f<f
s
controller
Gating unit
f>f
s
Effective for f > f
s
Load control
fSlip
Motor model with vector transformation
calculated
nact
Measured
T
Control mode 控制模式
without high demands placed on dynamic performance e.g. Pumps, fans, simple traversing drives
without speed encoder
with speed encoder
Single-motor and group drives
Single-motor drives
With low up to high demands placed on dynamic performance for speed control ranges 1:10
e.g. Extruders, fans, traversingand hoisting drives, centrifuges
变频器相关参数调试及基本原理变频器常用术语中英文对照
变频器基本参数的调试变频器功能参数很多,一般都有数十甚至上百个参数供用户选择。
实际应用中,没必要对每一参数都进行设置和调试,多数只要采用出厂设定值即可。
但有些参数由于和实际使用情况有很大关系,且有的还相互关联,因此要根据实际进行设定和调试。
因各类型变频器功能有差异,而相同功能参数的名称也不一致,为叙述方便,本文以富士变频器基本参数名称为例。
由于基本参数是各类型变频器几乎都有的,完全可以做到触类旁通。
一加减速时间加速时间就是输出频率从0上升到最大频率所需时间,减速时间是指从最大频率下降到0所需时间。
通常用频率设定信号上升、下降来确定加减速时间。
在电动机加速时须限制频率设定的上升率以防止过电流,减速时则限制下降率以防止过电压。
加速时间设定要求:将加速电流限制在变频器过电流容量以下,不使过流失速而引起变频器跳闸;减速时间设定要点是:防止平滑电路电压过大,不使再生过压失速而使变频器跳闸。
加减速时间可根据负载计算出来,但在调试中常采取按负载和经验先设定较长加减速时间,通过起、停电动机观察有无过电流、过电压报警;然后将加减速设定时间逐渐缩短,以运转中不发生报警为原则,重复操作几次,便可确定出最佳加减速时间。
二转矩提升又叫转矩补偿,是为补偿因电动机定子绕组电阻所引起的低速时转矩降低,而把低频率范围f/V增大的方法。
设定为自动时,可使加速时的电压自动提升以补偿起动转矩,使电动机加速顺利进行。
如采用手动补偿时,根据负载特性,尤其是负载的起动特性,通过试验可选出较佳曲线。
对于变转矩负载,如选择不当会出现低速时的输出电压过高,而浪费电能的现象,甚至还会出现电动机带负载起动时电流大,而转速上不去的现象。
三电子热过载保护本功能为保护电动机过热而设置,它是变频器内CPU根据运转电流值和频率计算出电动机的温升,从而进行过热保护。
本功能只适用于“一拖一”场合,而在“一拖多”时,则应在各台电动机上加装热继电器。
电子热保护设定值(%)=[电动机额定电流(A)/变频器额定输出电流(A)]×100%。
电源反馈设计速成篇之八建模篇(Peak Current Mode)
电源反馈设计速成篇之八: 建模篇(Peak Current Mode) 图1为Peak Current Mode 等效小信号模型. Vg为输入电压, Vo为输出电压, io 为输出电流, iL 为电感电流, d为占空比, Vc为反馈控制电压. Gvg为Vg到Vo的传递函数, Gvd为d 到Vo的传递函数, Gig, Gio, Gid分别为Vg, io, d到iL的传递函数, Zo为开环输出阻抗, Fm为等效调制比(Voltage Mode就是三角波幅度倒数, Current Mode是电压和电流的综合),Kf和Kr是考虑了Vg和Vo的扰动影响, 其值很小, 一般忽略没有大的影响. Hv是电压反馈环, Hi是电流采样系数, 负号表示负反馈. 如果是采样电阻的CIC(Current Injection Control)法, Hi就是采样电阻,如果是电感电压的SCM(Standard Current Mode)法, Hi要根据具体电路求得. Current Mode的精髓是要知道电感的di/dt.Gvg, Gvd, Zo, Gig, Gid, Gio这些传递函数都可以由Voltage Mode得到. 不再赘述.图1. Peak Current Mode等效小信号模型He 是等效采样保持传递函数1)(−⋅=⋅sT s se e T s s HTs 为开关周期.如下表:: Ri 为电流取样电阻, 即Hi.可以证明, 不论Ri 去多大, 电流内环都一样, 因为Fm 可以和Ri 对消.一般Ri 由功耗等决定.定义s e n s n c m T S S T S m F )(11+==, ne cS S m +=1Ts 为开关周期, Se 为外加斜坡补偿三角波幅值, Sn 为电感电流采样等效三角波幅值. mc 为衡量斜坡补偿效果系数, mc=1即Se=0, 为纯电流控制,mc>>1既外加斜坡补偿>>电感电流采样等效三角波幅值, 退化为Voltage Mode.一般mc=1.5-2.Hv 为设计参数,一般用Type2补偿,零点决定响应快慢,极点补偿ESR 零点,RHP零点,或1/2开关频率,三者取其低的值.以上为CCM Mode, 如果为DCM mode, 则开环参数为DCM mode 下的各个参数, 如下表:图1为整个系统的信号流图, 在推导小信号公式时有很多变量为零, 可大大简化. 以控制到输出传递函数为例, 图2为buck 电路, 图3为buck 小信号模型和控制到输出信号流图.V in图2. Buckd*Vap/Dvc图3. Buck 小信号模型和控制到输出信号流图可以求得电流内环开环回路增益Ti 为)()(s G s H H F T id e i m i ⋅⋅⋅=,电阻取样Hi=Ri, 否则要另行计算, 和具体电路有关. 当电流内环闭环时, 控制到输出传递函数Goc 为)(1)(s G F K T s G F G vd m r i vd m oc ⋅⋅−+⋅=电压回路增益Tv 为)()(s G s H F T vd v m v ⋅⋅=, Hv(s)为要设计的反馈部分.电压外环回路增益T2为ivT T T +=12, 根据T2来看相位和幅值裕量. 电流环闭合后输出阻抗Zoicl 为gi vd m e i vd o oicl V T s G F s H H s G s Z Z ⋅+⋅⋅⋅⋅+=)1()()()()(, Zo(s)为开环输出阻抗.电流环和电压环都闭合后输出阻抗Zovcl 为ivd m r vd m v oiclovcl T s G F K s G F s H Z Z +⋅⋅−⋅⋅+=1)()()(1 例子 Buck 电路:Vg 11:=L 37.5106−⋅:= Rc 0.02:= C 400106−⋅:= Fs 50103⋅:= Vo 5:= R 1:=Ri 0.33:=Sn Vg Vo −L Hi ⋅:= Sn 5.28104×=Fm mc ()1mc Sn ⋅Ts ⋅:=mc 设为变量, 对Hv 零点和极点的选取:选择 wzc 使Settling time 为 0.5ms,wzc 10.5103−⋅:=wzc 2103×=选择wpc 为 ESR 零点, RHP 零点, 1/2 开关频率, 三者的低频:w ZESR 1.25105×=ws 2π⋅Fs ⋅:= 0.5ws 1.571105×= 因没有RHP 零点, ESR 零点比1/2 开关频率低, 取wpc w ZESR :=wpc 1.25105×= Rx 103:=Ry 103:=Hv s wi ,()Ry Rx Ry +wis1swzc +1s wpc+⋅:=Kr Ts Ri⋅2L ⋅:=Kr 0.088=Kf D −Ts ⋅Ri⋅L1D 2−⎛⎜⎝⎞⎟⎠⋅:=Kf 0.062−=图4为电流内环闭环时, 控制到输出传递函数Goc, 参变量mc 为1,1.2,1.5,2,4. Mc=1.5 –2时系统相位和幅值变化平稳. 选取mc=1.5.变化wi 不会改变Hv 相位, 选取 wi 以满足相位和幅值裕量要求. 图5给出了T2和wi 关系. 选取 wi = 40000, 剪切频率fc=13253 Hz, 相位和幅值裕量 55 degree, 6 dB.图6为求得反馈部分电阻,电容值后电流内环闭环时, 控制到输出传递函数Goc, mc=1为纯电流控制, mc=1.5为外加斜坡补偿的优化设计.图7为电流环闭合后输出阻抗Zoicl, mc=1为纯电流控制, mc=1.5为外加斜坡补偿的优化设计.图8为电流环和电压环都闭合后输出阻抗Zoicl, mc=1为纯电流控制, mc=1.5为外加斜坡补偿的优化设计.图9-11分别为mc=1时的PSPICE 仿真结果, 用来验证公式的正确.101001.1031.1041.1051.10660402020gain Goc 2i π⋅f n ⋅1,()()gain Goc 2i π⋅f n ⋅ 1.2,()()gain Goc 2i π⋅f n ⋅ 1.5,()()gain Goc 2i π⋅f n ⋅2,()()gain Goc 2i π⋅f n ⋅4,()()f n101001.1031.1041.1051.10620015010050180−phase Goc 2i π⋅f n ⋅1,()()phase Goc 2i π⋅f n ⋅ 1.2,()()phase Goc 2i π⋅f n ⋅ 1.5,()()phase Goc 2i π⋅f n ⋅2,()()phase Goc 2i π⋅f n ⋅4,()()f n图4. 电流内环闭环控制到输出传递函数Goc101001.1031.1041.1051.10660303060gain T22i π⋅f n ⋅ 1.5,10000,()()gain T22i π⋅f n ⋅ 1.5,20000,()()gain T22i π⋅f n ⋅ 1.5,40000,()()gain T22i π⋅f n ⋅ 1.5,100000,()()gain T22i π⋅f n ⋅ 1.5,200000,()()f n101001.1031.1041.1051.10630025020015010050180−phase T22i π⋅f n ⋅ 1.5,10000,()()phase T22i π⋅f n ⋅ 1.5,20000,()()phase T22i π⋅f n ⋅ 1.5,40000,()()phase T22i π⋅f n ⋅ 1.5,100000,()()phase T22i π⋅f n ⋅ 1.5,200000,()()f n图5. 电压外环回路增益T2 和wi 关系1101001.1031.1041.1051.1068060402020gain Goc 2i π⋅f n ⋅1,()()gain Goc 2i π⋅f n ⋅mc,()()f n1101001.1031.1041.1051.10620015010050180−phase Goc 2i π⋅f n ⋅1,()()phase Goc 2i π⋅f n ⋅mc,()()f n图6. 电流内环闭环控制到输出传递函数Goc (mc=1, 1.5)1101001.1031.1041.1051.10640302010gain Zoicl 2i π⋅f n ⋅1,()()gain Zoicl 2i π⋅f n ⋅mc ,()()f n1101001.1031.1041.1051.10680604020phase Zoicl 2i π⋅f n ⋅1,()()phase Zoicl 2i π⋅f n ⋅mc,()()f n图7.电流环闭合后输出阻抗Zoicl (mc=1, 1.5)1101001.1031.1041.1051.10680604020gain Zovcl 2i π⋅f n ⋅1,wi,()()gain Zovcl 2i π⋅f n ⋅mc ,wi,()()f n1101001.1031.1041.1051.106200100100180−phase Zovcl 2i π⋅f n ⋅1,wi ,()()phase Zovcl 2i π⋅f n ⋅mc ,wi ,()()f n图8. 电流环和电压环都闭合后输出阻抗Zovcl (mc=1, 1.5)图9. Pspice 结果:电流内环闭环控制到输出传递函数Goc (mc=1)图10. Pspice 结果: 电流环闭合后输出阻抗Zoicl (mc=1)图11. Pspice 结果: 电流环和电压环都闭合后输出阻抗Zovcl (mc=1)。
电流模式与电压模式
电源变换器中电流模式和电压模式相互转化adlsong摘要摘要::本文先简单的介绍了电流模式和电压模式的工作原理和这两种工作模式它们各自的优缺点;然后探讨了理想的电压模式利用输出电容ESR 取样加入平均电流模式和通过输入电压前馈加入电流模式的工作过程。
也讨论了电流模式在输出轻载或无负载时,在使用大的电感或在占比大于0.5加入斜坡补偿后,系统会从电流模式进入电压模式工作过程。
关键词关键词::电流模式,电压模式,转化,斜坡补偿Mutual Variation between Current Mode and V oltage Mode in PowerSupply Converter(AOS Semiconductor Co., Ltd., Shanghai 201203)Abstract: The operation principle and features of current mode and voltage mode are introduced in this paper. The converter at voltage mode will own good dynamic performances of current mode when current signal via ESR of output capacitance or input voltage forward feedback is imposed into control loop of voltage mode. The converter at current mode will go intocycle. Key words: 目前,电压模式和电流模式是开关电源系统中常用的两种控制类型。
通常在讨论这两种工作模式的时候,所指的是理想的电压模式和电流模式。
电流模式具有动态响应快、稳定性好和反馈环容易设计的优点,其原因在于电流取样信号参与反馈,抵消了由电感产生的双极点中的一个极点,从而形成单阶的系统;但正因为有了电流取样信号,系统容易受到电流噪声的干扰而误动作。
UC3842变压器算法
GND 16 V (8.4 V)
6.0 V (0.5 V)
Set/ Reset
5–V Reference
VREF
Internal Bias 2.50 V Output Enable NOR S + VFB – Error Amplifier R 1.0 V 2R R Current Sensing Comparator PWM Latch VOUT
OSCBiblioteka OscillatorCOMP SENSE
( ) Indicates CS2843A/3843A
Figure 3. CS3842A/3843A Block Diagram
2
CS3842AAN/D
VOUT VCC 120 V AC INPUT CS3842A VOUT
In current mode control, (CMC) the control signal represents the peak inductor current and forms a second loop in the circuit (Figure 1). The advantages of current mode control are: • Instantaneous correction to line voltage variations; the inductor current slope varies with input voltage. • Stable power supply designs; the pole associated with the inductor is eliminated. • Equal current sharing in paralleled power stages when both share the same control signal and have the same current sense circuits. • No current limit amplifier is needed. • Flux balancing exists in push–pull circuits. Disadvantages: • Slope compensation is required for peak versus average inductor current error and for compensating instabilities associated with load disturbances in single ended topologies operating at greater than 50% duty cycle. Premature shutdown due to the turn on current spike caused by the reverse diode recovery of the output free wheeling diode. • Runaway conditions when half bridge topology is operated in current–mode control.
TI 控制模式快速参考指南说明书
Control-mode quick reference guideOverviewTI is active in the development of leading-edge controlcircuits to help engineers address specific designchallenges. Since no control mode is optimal for everyapplication, various control modes for non-isolated step-down controllers and converters are referenced with theiradvantages and how to learn more about each mode.The TI portfolio contains 15 types of control architecturesfor non-isolated TPS- and LM-series switching DC/DCconverters and controllers.Voltage modeInternally-compensatedadvanced currentmode (ACM)Direct connection tothe output capacitor(D-CAP™)Voltage mode with voltage feed-forward Hysteretic controlmodeD-CAP+™controlmodePeak current mode Constant on-time D-CAP2™ controlmodeAverage currentmodeConstant on-timewith emulated ripplemodeD-CAP3™ controlmodeEmulated currentmodeDCS-Control™:Direct control withseamless transitioninto power-savemodeD-CAP4™controlmodeVoltage modePulse-width modulation (latch output) is accomplished by comparing a voltage error signal (V E) from the output voltage and reference voltage to a constant saw-tooth-ramp waveform. The ramp is initiated by a clock signal from an oscillator. Good noise-margin performance is attained with a fixed ramp amplitude (V R). Voltage regulation is independent of the output current. Voltage mode uses type-3 compensation addressing a double-pole power stage to support a wide range of output filter combinations for externally compensated devices.When to use: When a fixed, predictable switching frequency is desired. Also useful when wide output-load variations are possible.Popular devices: TPS54610, TPS40040, LM22670Learn more:Switching Power Supply Topology Voltage Mode vs. Current ModeCLOCKVVLATCHEROUTPUTVoltage mode with voltage feed-forward Similar to voltage mode, but ramp generator varies the PWM ramp slope with the input voltage at a constant ramp magnitude and delivers an instantaneous response to input voltage variations. The PWM does not have to wait for loop delays to change the duty cycle.When to use: When a fixed, predictable switching frequency is desired. Also useful when wide variationsof input voltage and output load are possible.Popular devices:TPS40057, TPS40170, TPS56121 Learn more:Effect of Programmable UVLO on Maximum Duty Cycle Achievable With the TPS4005x and TPS4006x Family of Synchronous Buck ControllersVt>t and D>DVtD=tPeak current modePulse-width modulation (latch output) is accomplished by comparing a voltage error signal (V E) and a ramp waveform (V S) derived from the output current. The ramp is initiated by the clock signal. This mode offers fastresponse to output current changes. However, it can be susceptible to noise sensitivity at low duty cycles due to leading-edge current spike. It uses type-2 compensation addressing a single-pole power stage for externally compensated devices.When to use: When a fixed, predictable switching frequency is needed with a lower parts count than the externally-compensated, double-pole voltage mode.Peak current mode uses a single zero compensator,which is easier to design than voltage mode’s double-zero compensator.Popular devices: TPS54620, TPS62913, LM5140-Q1Learn more: Understanding and Applying Current-Mode ControlTheoryCLOCKV EV SLATCH OUTPUTAverage current modeAverage current mode addresses noise immunity issues, peak-to-average current errors, and slope compensation needs of peak current mode. Average current mode introduces a high gain integrating current error amplifier into the current loop. The voltage across a current sense resistor represents the actual inductor current. The difference, or current error, is amplified and compared to a large amplitude saw-tooth (oscillator ramp) at the PWM comparator inputs. The gain of the current loop effectively sets the slope compensation without restricting the minimum on-time or minimum-off time. Current sensing is usually inside the regulator, but can be external.When to use: Effectively control currents other than inductor current, allowing a much broader range of topological application.Popular devices: TPS546D24S , TPS546B24SLearn more: Average Current Mode Control of Switching Power SuppliesEmulated current modeSimilar to current mode, but employs a gated sample and hold circuit to capture current information emulated by measuring inductor voltage to estimate the ramp current. Eliminates the leading-edge spike issue of the traditional peak-current mode by allowing smaller duty cycles. Provides a clean current waveform when operating near the minimum on-time.When to use: When low duty cycle is neededversus traditional current mode, without current noise susceptibility.Popular devices: LM5116, LM5119Learn more: Emulated Current Mode Control for Buck Regulators Using Sample and Hold TechniqueInternally-compensated advanced currentmode (ACM)Internally-compensated ACM is a ripple-based, peak-current-mode control scheme that uses an internally generated ramp to represent the inductor current. This control mode provides a balance between the fast transient response of non-linear control modes (D-CAP™, constant on-time, and so forth) and the broad capacitor stability of other externally-compensated, fixed-frequency control modes (voltage mode, current mode). Internally-compensated advanced current mode provides a fixed, predictable frequency and a simplified compensation selection to reduce external components.When to use: When fixed frequency and/or stack ability is needed with good output capacitor tolerance and a simplified compensation selection.Popular devices: TPS543B22 , TPS543C20A , TPS543620Learn more: Internally Compensated Advanced Current Mode(ACM)Hysteretic control modeThe simplest control scheme. The PWM (SW) on-time (T ON ) is terminated when the feedback voltage is greater than a reference-high threshold and the off-time (T OFF ) is terminated when the feedback voltage is less than a reference-low threshold. No compensation components are required. The PWM switching frequency is not controlled and varies with load current and delivers higher efficiency at lighter loads.When to use: When fast transient response is required. There is no clock-signal time delay to initiate the ramp. A certain amount of ripple is required at the output from the output capacitor’s ESR.Popular devices: LM3475, LM3485Learn more: LM3485 Hysteretic PFET Buck Controller Data SheetI OUTV REF (HIGH)V OUT GNDV IN V REF (LOW)Constant on-timeA slight variation to hysteretic control minimizing frequency shift, but with a single voltage-threshold level, yet achieving fast transient response. The on-time is terminated by a one-shot on-timer and is proportional to the input voltage. The off-time is terminated when the feedback voltage falls below the reference-low threshold.When to use: When fast transient response is required and a fixed or predictable switching frequency is not required. A certain amount of ripple is required at the output from the output capacitor ESR.Popular devices: LM5017, LM2696, TPS54A20Learn more: Controlling Output Ripple and Achieving ESR Independence in Constant On-Time (COT) Regulator DesignsI OUTV OUTGNDV V IN V REFConstant on-time with emulated ripple modeA variation of the COT regulator that senses a portion of the low-side MOSFET’s off-time current and injects it into the error comparator to emulate ripple. This control mode has the same fast transient response and fewer external component advantages of COT.When to use: When employing low-ESR ceramic capacitors or when an external ripple injection circuit is undesirable.Popular devices:LM3100, LM3150Learn more:Emulated ripple technique advances hysteretic switch-mode suppliesDCS-Control™: Direct control with seamless transition into power-save modeCombines the advantages of hysteretic control for a fast transient response without compensation components, and the advantages of voltage-mode control for high DC accuracy with a seamless transition from PWM to power saving mode (PSM).When to use: When light-load efficiency is needed with small, low-ESR ceramic capacitors.Popular devices:TPS62872,TPS628303, TPS62903, TPS82130Learn more:High-efficiency, low-ripple DCS-Control™ offers seamless PWM/power-save transitionsFBDirect connection to the output capacitor (D-CAP™)Similar to COT control except a one-shot timer generates an on-time pulse that is proportional to the input voltage and the output voltage. When the falling feedback voltage equals the reference voltage, a new PWM on-pulse is generated. Fast response to load changes is achieved with a high-speed comparator in the control loop. D-CAP™ minimizes frequency shift compared to hysteretic control.When to use: When a fast transient response is required and POSCAP or medium-ESR output capacitors are used. No loop-compensation calculation or components are needed.Popular devices:TPS51116, TPS53219A, TPS53355Learn more:Adaptive Constant On-Time (D-CAP™) Control Study in Notebook ApplicationsT OND-CAP+™D-CAP+ adds an error amplifier to D-CAP that compares V FB to V REF for better output voltage accuracy and a current sense amplifier to sense the current directly, instead of relying on output ESR to act as the sense element. D-CAP+ is a true voltage-controlled current source without a clock limitation like most variants of current mode control. D-CAP+ is used where true current sensing is required, such as multi-phase and droop-compensation (load-line) applications with one output voltage. Current sensing may be accomplished either inside or outside of the power IC depending on the device.When to use: When high accurate current sensingis needed for load-line or multi-phase controller applicationsPopular devices:TPS53661, TPS53667, TPS548C26Update Learn more:D-CAP+™ Control for Multi-phase, Step-Down Voltage Regulators for Powering MicroprocessorsD-CAP2™A slight variation of D-CAP with the same transient and external component advantages as D-CAP . This control mode supports ceramic output capacitance without external circuitry. A signal from an internal ripple-injection circuit is fed directly into the comparator, thus reducing the need for output voltage ripple from the capacitor’s ESR. The ramp is emulated by the output inductor.When to use: When desiring fast transient response with low-ESR ceramic output capacitors.Popular devices: TPS563202, TPS563210Learn more:D-CAP2™ Frequency Response ModelD-CAP3™A variation of D-CAP2™ with the same transient and external component advantages. A sample-and-hold circuit is built-in to the converter to remove an offset voltage created by D-CAP2’s emulated ramp circuit,improving the voltage reference accuracy. Well suited for powering low-core-voltage FPGAs, ASICs and DSPs.When to use: When a tighter reference voltage accuracy and a fast transient response are desirable when using ceramic output capacitors.Popular devices: TPS565247 , TPS56C231, TPS548B28, TPS563206Learn more: Accuracy-Enhanced Ramp-Generation Design forD-CAP3 ModulationD-CAP4™D-CAP4 includes the advantages as D-CAP3, but desensitizes the loop gain to the output voltage in order to improve the transient response at higher output voltages. The ramp injection principle is the same as D-CAP3, except the ramp common mode and amplitude are independent of the output voltage. The ramp common mode is inversely proportional to (1-D), keeping ramp amplitude constant, so there is less need to adjust the ramp for different output voltages.When to use: When fast transient response time is needed with higher output voltages, like 3.3 V or 5 V .Popular devices:TPS54KB20Important Notice: The products and services of Texas Instruments Incorporated and its subsidiaries described herein are sold subject to TI’s standard terms and conditions of sale. Customers are advised to obtain the most current and complete information about TI products and services before placing orders. TI assumes no liability for applications assistance, customer’s applications or product designs, software performance, or infringement of patents. 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Enhanced Current Mode PWM Controller 说明书
The CS51021/22/23/24 Fixed Frequency PWM Current ModeController family provides all neces-sary features required for AC-DC or DC-DC primary side control.Several features are included elimi-nating the additional components needed to implement them external-ly. In addition to low start-up cur-rent (75µA) and high frequency operation capability, the CS51021/22/23/24 family includes overvolt-age and undervoltage monitoring,externally programmable dualthreshold overcurrent protection,current sense leading edge blank-ing, current slope compensation,accurate duty cycle control and an externally available 5V reference.The CS51021 and CS51023 feature bidirectional synchronization capa-bility, while the CS51022 and CS51024 offer a sleep mode with 100µA maximum IC current con-sumption. The CS51021/22/23/24family is available in a 16 lead nar-row body SO package.s 75µA Max. Startup Current s Fixed Frequency CurrentMode Controls 1MHz Switching Frequency s Undervoltage ProtectionMonitors Overvoltage ProtectionMonitor withProgrammable Hysteresis s Programmable DualThreshold Overcurrent Protection with Delayed Restarts Programmable Soft Start s Accurate Maximum DutyCycle Limits Programmable SlopeCompensations Leading Edge CurrentSense Blankings 1A Sink/Source Gate Drive Description2000 South County Trail, East Greenwich, RI 02818Tel: (401)885-3600 Fax: (401)885-5786Email:********************Power Supply Voltage, V CC ............................................................................................................................................-0.3V, 20V Driver Supply Voltage, V C ..............................................................................................................................................-0.3V, 20V SYNC, SLEEP, R T C T , SOFT START, V FB , SLOPE, I SENSE , UV, OV, I SET (Logic Pins).......................................-0.25V to V REF Peak GATE Output Current.........................................................................................................................................................1A Steady State Output Current..................................................................................................................................................±0.2A Operating Junction Temperature, T J .....................................................................................................................................150°C Storage Temperature Range, T S ...................................................................................................................................-65 to 150°C ESD (Human Body Model).........................................................................................................................................................2kV Lead Temperature Soldering: Reflow (SMD styles only).............................................60 sec. max above 183°C, 230°C peakC S 51021/22/23/24Note 1: Guaranteed by Design, not 100% tested in production.Package Pin DescriptionCI V I REFV SYNC R T C Figure 1: CS51021/22/23/24 Block DiagramBlock Diagram3/24input of the PWM comparator is a combination of thesetwo voltages. The slope compensation, , is calcu-lated using the following formula:= 0.1 ×It should be noted that internal capacitance of the IC willcause an error when determining slope compensation capacitance C S . This error is typically small for large val-ues of C S , but increases as C S becomes small and compara-ble to the internal capacitance. The effect is apparent as a reduction in charging current due to the need to charge the internal capacitance in parallel with C S . Figure 3 shows a typical curve indicating this decrease in available charg-ing current.Figure 3: The slope compensation pin charge current reduces when a small capacitor is used.Undervoltage (UV) and Overvoltage (OV) Monitor Two independent comparators monitor OV and UV con-ditions. A string of three resistors is connected in series between the monitored voltage (usually the input voltage)and ground (see Figure 4). When voltage at the OV pin exceeds 2.5V, an overvoltage condition is detected and GATE shuts down. An internal 12.5µA current source turns on and feeds current into the external resistor, R 3,creating a hysteresis determined by the value of this resis-tor (the higher the value, the greater the hysteresis). The hysteresis voltage of the OV monitor is determined by the following formula:V OV(HYST)= 12.5µA ×R 3where R 3is a resistor connected from the OV pin to ground.When the monitored voltage is low and the UV pin is less than 1.45V, GATE shuts down. The UV pin has fixed 75mV hysteresis.Both OV and UV conditions are latched until the Soft Start capacitor is discharged. This way, every time a fault con-dition is detected the controller goes through the power up sequence.Figure 4: UV/OV Monitor DividerTo calculate the OV/UV resistor divider:1. Solve for R 3, based on OV hysteresis requirements.R 3= ’where V OV(HYST)is the desired amount of overvoltage hys-teresis, and V MAX is the input voltage at which the supply will shut down.2. Find the total impedance of the divider.R TOT = R 1+ R 2+ R 3= 3. Determine the value of R 2from the UV threshold condi-tions.R 2= −R 3,where V MIN is the UV voltage at which the supply will shut down.4. Calculate R 1.R 1= R TOT −R 2−R 35. The undervoltage hysteresis is given by:V UV(HYST)=SynchronizationA bi-directional synchronization is provided to synchro-nize several controllers. When SYNC pins are connected together, the converters will lock to the highest switching frequency. The fastest controller becomes the master, pro-ducing a 4.3V, 200ns pulse train. Only one, the highest fre-quency SYNC signal, will appear on the SYNC line.SleepThe sleep input is an active high input. The CS51022/51024is placed in sleep mode when SLEEP is driven high. In sleep mode, the controller and MOSFET are turned off.Connect to Gnd for normal operation. The sleep mode operates at V CC ≤15V.Oscillator and Duty Cycle LimitThe switching frequency is set by R T and C T connected to the R T C T pin. C T charges and discharges between 3V and 1.5V.The maximum duty cycle is set by the ratio of the on time,t ON , and the whole period, T = t ON + t OFF . Because theV MIN ×0.0751.451.45 ×R TOTV MIN V MAX ×R 32.5V OV(HYST) ×2.5VV MAX ×12.5µA53µAC SdV SLOPE dt dV SLOPEdt CS51021/22/23/24C S 51021/22/23/24timing capacitor’s discharge current is trimmed, the maxi-mum duty cycle is well defined. It is determined by the ratio between the timing resistor R T and the timing capaci-tor C T . Refer to figures 5 and 6 to select appropriate values for R T and C T.f SW = ; T SW = t CH + t DISFigure 5: Frequency vs. R T for Discrete Capacitor Values.Figure 6: Duty Cycle vs. R T for Discrete Capacitor Values.1T SWCS51021/22/23/24Ordering InformationThermal Data 16L SO NarrowR ΘJC typ 28˚C/W R ΘJAtyp115˚C/WDLead Count Metric EnglishMax Min Max Min 16L SO Narrow10.009.80.394.386Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information.。
ZDP控制方法介绍及与其他控制方法的比较
Agenda•Background•Voltage Mode•Peak Current Mode•Constant On-Time•Zero Delay PWMo Block Diagram/Operationo Hardware Resultso Pros and ConsInfotainment SOCSystem PowerHV Buck LV BuckHV LDOHV Boost PMICHV Buck-BoostLV LDOCANDual AntennaLDO+PreboostDual AntennaLDOLV Load SwitchLV LDOLV BoostUSB ChargerDDRTerminationAM/FM/SATGPSEthernet, LVDSMemoryTunerSingle Dual Port,Type-A Type-C,PDLV BoostBacklightTFT BiasBattery Front EndController, E-FuseVbatt•~ 5 years ago, automotive applications were low power (<20W) and could be covered with a 3 or 4A buck.o>6A were infrequently require.o Transient requirements were not stringent.•As computing requirements increased, POLs/LV bucks using COT were very common •COT considered for off-battery/HV bucks, but customers were hesitant due to EMI o Peak Current Mode control was ubiquitous, but lacks load transient performance•Additionally,MPSalsohaddifficultycovering18V->********************* spectrumo Large minimum on time gated the ability for a large conversion ratio at >2MHz fswGOAL: Create a control topology that combined the dynamic benefits of COT with fixed frequency operation while allowing for a narrow on time.•Clock turns on HS•Ramp was generated by clock•Output Voltage is compared to VREF to generate COMP signal.•COMP signal is compared to ramp to generate the LS on signalVoltage Mode Control –OperationVINCINHSLSLCOUTLOAD+-VREFRFB1RFB2CC3RC2+-+-CC2RC1CC3RAMPDRIVERS VOUTPWM ComparatorQR SCLOCKPWM LATCHCOMPQQ’EAVoltage Mode Control –Load Transient OperationVINCINHSLSLCOUTLOAD+-VREFRFB1RFB2CC3RC2+-+-CC2RC1CC3RAMPDRIVERSVOUTPWM ComparatorQR SCLOCKPWM LATCHCOMP1. Sudden load current increase causes VOUT to drop2. VOUT drop causes COMP to increase3. COMP increases causes duty cycle to increaseLegendFast Change:Slow change:+Simplest Control Method+Good noise immunity no current noise-Due to undamped LC output filter, requires high ESR capacitors or type III compensation-Load transient performance is okay -Line transient is poor, unless line feedforward is used on the rampVoltage Mode Control –Pros and ConsVINCINHSLSLCOUTLOAD+-VREFRFB1RFB2CC3RC2+-+-CC2RC1CC3RAMPDRIVERSVOUTPWM ComparatorQR SCLOCKPWM LATCHCOMPVINCINHSLSLCOUTLOAD+-VREFRFB1RFB2+-SLOPE COMPDRIVERSVOUTPWM ComparatorQRSCLOCKPWM LATCH+-CC1RC1CC2CURRENT SENSECOMPPeak Current Mode Control -Operation•Output voltage is compared to VREF to generate COMP signal.•COMP signal is compared to sensed current.•Most implementations add a slope compensation ramp to the current signalVINCINHSLSLCOUTLOAD+-VREFRFB1RFB2+-SLOPE COMPDRIVERSVOUTPWM ComparatorQRSCLOCKPWM LATCH+-CC1RC1CC2CURRENT SENSECOMP1. Sudden load current increase causes VOUT to drop2. VOUT drop causes COMP to increase3. COMPincrease causes duty cycle to increasePeak Current Mode Control –Load Transient OperationLegendFast Change:Slow change:VINCINHSLSLCOUTLOAD+-VREFRFB1RFB2+-SLOPE COMPDRIVERSVOUTPWM ComparatorQRSCLOCKPWM LATCH+-CC1RC1CC2CURRENT SENSECOMPPeak Current Mode Control –Pros and Cons+Improved compensation with current feedback that acts a lossless resistor damping the output LC filter+Good line transient performance -Okay load transient performance -Complex compared to voltage mode-Large minimum on time limits minimum conversion ratio due to “blanking time” for peak current sense•Output voltage (with synthetic ramp) is fed directly into PWM Comparator and acts as a fast loop response to VOUT changes •Output voltage compared to VREF to create COMP signal for improved DC regulation•Synthetic ramp is added to allow operation with low ESR capacitors•On-time can be generated at any time (after a minimum off-time)Constant On-time Control -Operation(w/ Offset Cancellation & Synthetic Ramp)VINCINHSLSL COUTLOAD+-VREFRFB1RFB2+-DRIVERSPWM ComparatorQS RPWM LATCH+-CC1RC1CC2CURRENT SENSECOMP-VOUTRAMP GENERATORONE SHOT TIMER VOUTVINSimple COTConstant On-time Control –Load Transient Operation(w/ Offset Cancellation & Synthetic Ramp)VINCINHSLSLCOUTLOAD+-VREFRFB1RFB2+-DRIVERSPWM ComparatorQS RPWM LATCH+-CC1RC1CC2CURRENT SENSECOMP-VOUTRAMP GENERATORONE SHOT TIMER VOUTVIN1. Sudden load current increase causes VOUT to drop3. COMP adjusts as needed to maintain 2. VOUT dropping directly and immediatelycauses additional on-time pulsesLegendFast Change:Slow change:Constant On-time Control –Pros and Cons(w/ Offset Cancellation & Synthetic Ramp)+Great line & load transient response+Low cost implementation-Switching frequency may change, especially during transients, which is unsuitable for EMI in off-battery application-Synthetic ramp required for low ESR capacitorsVINCINHSLSLCOUTLOAD+-VREFRFB1RFB2+-DRIVERSPWM ComparatorQS RPWM LATCH+-CC1RC1CC2CURRENT SENSECOMP-VOUTRAMP GENERATORONE SHOT TIMER VOUTVIN•Like COT, output voltage is fed directly into PWM Comparator for a fast loop and compared toVREF to create COMP signal for improved DC regulation•Like Peak Current Mode, asensed current signal, with slope compensation, is used. And PWM latch is reset with a fixed frequency clock•The slope compensation isproportional to VIN and includes offset cancelation to improve the line transient response.•Valley current mode does not require “blanking time”, allowingfor a small minimum on timeZero Delay PWM (ZDP) –OperationVINCINHSLSLCOUTLOAD+-VREFRFB1RFB2-+SLOPE COMPDRIVERSVIN*KPWM ComparatorQS RCLOCKPWMLATCH+-CC1RC1CC2CURRENT SENSECOMPOFFSET CANCELATIONVOUTAC COUPLERZero Delay PWM (ZDP) –Load Transient Operation1. Sudden load current increase causes VOUT to drop3. COMP adjusts as needed to maintain DC regulation2. VOUT dropping directly and immediatelycauses duty cycle to increaseLegendFast Change:Slow change:VINCINHSLSLCOUTLOAD+-VREFRFB1RFB2-+SLOPE COMPDRIVERSVIN*KPWM ComparatorQSRCLOCKPWM LATCH+-CC1RC1CC2CURRENT SENSECOMPOFFSET CANCELATIONVOUTAC COUPLERZDP vs COT Comparison•In COT, SR latch is reset by a one shot timer•In Zero Delay PWM, SR latch is reset by a clock•Both topologies bring FB directly to the PWM comparator.•3x faster transient compared to peak current mode with the same components and setupo 12V input, 3.3V output, 0A to 3.5A load step o 1uH Lout, 2x22uF CoutZero Delay PWM –Load Transient Hardware523mVpk-pk (+/-8%)170mVpk-pk (+/-2.5%)Peak Current ModeZero Delay PWMZero Delay PWM –Pros and Cons+Type I or Type II compensation is sufficient for stability+True fixed frequency operation +Can be synchronized without a PLL +Line/Load transient performance on par with COTReduced output capacitance requirement+Valley current allows for a very narrow minimum on timeWorst case 35ns compared to 60-100ns for peak current mode-Complexity -> High cost implementationVINCINHSLSLCOUTLOAD+-VREFRFB1RFB2-+SLOPE COMPDRIVERSVIN*KPWM ComparatorQS RCLOCKPWM LATCH+-CC1RC1CC2CURRENT SENSECOMPOFFSET CANCELATIONVOUTAC COUPLERThank You。
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Current-Mode Vs. Voltage-Mode Control In Synchronous Buck Convertersby Brian Lynch, Texas Instruments IncorporatedFor the past twenty years, feedback current-mode control (CMC) has been the method of choice for many high-performance power supply applications. But is it the optimum choice for all power supplies? Here we discuss the pros and cons of CMC Vs. voltage-mode control (VMC) as applied to general purpose dc-dc synchronous buck converters. The choice of whether to implement CMC or VMC as the feedback control method in a synchronous buck dc-dc converter is based on a number of considerations. While the perceived advantage of CMC is better feedback loop response, today’s high-frequency VMC controlled converters closely rival their CMC counterparts.Fig. 1 illustrates the difference in feedback loop performance for a 3.3-V to 1.8-V dc-dc converter with a 10-A output using CMC and VMC and operating at 600 kHz. Since the conversion ratio is above 50% duty cycle, a small amount of slope compensation is added to the CMC loop. In textbook fashion the CMC control-to-output gain is higher at low frequencies and has a zero gain crossover frequency much higher than the VMC counterpart has.Fig. 1: CMC And VMC Control-To-Output Loop Gain/PhaseThe difference can be narrowed (see Fig. 2) by using Type 3 compensation around the VMC error amplifier when the overall loop performance matches that of a CMC system, albeit at the expense of requiring a higher-bandwidth amplifier.Fig. 2: CMC And VMC Closed-Loop Gain/PhaseNotice that near the L-C pole frequency the CMC closed-loop phase response is more smooth than the closed-loop phase response of the VMC system, due to L-C resonance combined with the HF pole-then-zero of the Type 3 compensation (see Fig. 3.) Ringing in the output voltage during load transients will be less damped than with the CMC system.Fig. 3 Error-Amplifier Gain And PhaseConverters with a wide input-voltage range must compensate for open-loop gain variation by selecting compensation components either for worst-case (high-input voltage) or by including a gain-compensating circuit. With VMC, since converter gain is dependent on the input voltage and the PWM ramp amplitude, input-voltage feed-forward is used. Conversely, peak CMC directly provides input-voltage gain compensation by the change in inductor slope during the switch ON time. While in practice this compensation is not as effective as pure voltage feed-forward, it is nonetheless “free” in CMC.From a signal path standpoint in VMC, a load current change must first have an effect on the output voltage before the voltage amplifier can react and make a correction. CMC on the other hand senses a change in load current directly so the voltage amplifier does not need to react in order for the loop to make a correction. This cause-and-then-react approach makes VMC slower to respond than CMC with very high-speed load transients. One key differentiator in applying either of the two control methods is current sensing. CMC requires accurate current sensing for control loop stability, and relatively large voltage levels are required to ensure that a good SNR is maintained at light loads. This voltage level with the load current at full load can result in significant power loss. To reduce the power loss, a smaller sense element may be used. However, to increase the sensed signal to a useable level requires a high bandwidth current-sense amplifier. In most applications, a small amount of slope compensation is also required to ensure loop stability. Generally this is accomplished by summing in a small amount of signal from an oscillator ramp into the measured current signal.Output voltage regulation is independent of current with VMC, so relatively crude current sensing may be acceptable since it is only necessary for output overload protection. This can save considerable circuit complexity and reduce circuit power loss.ILoadFig. 4: Alternate Points To Measure Current - With Different TradeoffsIn location A (see Fig. 4), average input current is monitored. While this is useful for controlling inrush current, it is not a very useful place for current mode control. Whenused for current limit protection, input power is limited instead of output fault current and therefore this method implements a power limiting approach to fault protection. To keep the power limiting constant with input-voltage variation, additional circuitry is required to reduce the limiting threshold level with increasing input voltage.Location B, in series with the upper MOSFET switch (or it may be the RdsON of the switch itself while the MOSFET is ON) is a popular location for current sensing when peak current mode control is implemented. Since slope information is available, ac feedback information is available for the control loop. A drawback at narrow pulse widths (due to high input-to-output conversion ratios or high operating frequency) is that the amount of useable slope information can become virtually non-existent due to circuit ringing and blanking time intervals. The ON impedance of a MOSFET can be used as a sense element with no penalty in power loss or circuit cost; however component variance, RdsON temperature coefficient and the ringing seen at the switch node can all affect feedback loop performance. If this approach is used, then slope compensation must be added for duty cycles of greater than 50%.Current measured at Location C is also peak current, but it is the peak current measured during the OFF time of the upper switch instead of the ON time as is the case in B. In this way CMC applies the same OFF time current information to the feedback loop so long as leading edge PWM is the control technique, instead of the more commonly used trailing edge PWM when slope compensation must be added for duty cycles of less than 50% Current measured in location D is the output current directly and is therefore the most attractive from a feedback standpoint. Here average dc output current as well as ac slope information is available and so any change in the output load current is quickly translated into a feedback response. Unfortunately, since the current is mostly dc at this point, current sensing at this location is also more dissipative than at the first three. A low value resistor may be used as a sense element at the expense of low current noise immunity, or the dc resistance of the inductor may be used, at the expense of additional filtering. Location E carries dc load current information and cannot be used for CMC, but it can be used for applications requiring a slow current sharing loop. There is a similar power loss issue as in D. However, since no high frequency control information is required, then filtering may be applied and light load SNR is not an issue.For general purpose single output dc-dc converters, the overall advantage goes with VMC. The feedback network, even with a “Type 3” compensation network around the voltage-error amplifier, is relatively simple to compensate. In many ways it is simpler than compensating a current loop, plus a voltage loop, plus adding slope compensation. This, along with the improved noise immunity at light loads, makes VMC attractive from a circuit performance standpoint.From a customer point of view, having features such as slope compensation or input voltage feed-forward internally added by an IC vendor is both a plus and a minus. On the plus side the customer does not have to add any components. On the minus side whatevermanner the IC vendor chooses to implement the feature is the manner the customer is stuck with. Perhaps for a specific approach the manner is acceptable, but what of the corners of operation where the customer has to work around the built-in feature? A good parallel to this is internal feedback compensation Vs. external compensation. In some cases, it can reduce component count; however, it also severely limits the selection of the operating frequency, the filter inductor, and the output capacitors. The best compromise is to have a feature included in the IC with the means for a customer to adjust its effect. From an implementation standpoint the current sensing requirements of CMC require higher accuracy than those of VMC, so higher power loss or circuit complexity is likely. For most general purpose applications, where only basic current overload protection is required, low-value/low-cost sensing elements are used without worrying about noise sensitivity at light loads. If tight tolerance in overload protection is a requirement, then either VMC or CMC can be designed to meet that need equally.About the author。