EDA课程设计 多功能数字钟设计程序清单 数字系统设计与verilog HDL(第四版) 王金明

EDA课程设计

多功能数字钟设计程序清单

数字系统设计与verilog HDL(第四版)

王金明

/*引脚锁定基于DE2一70，芯片为EP2C70F896，信号定义如下: Clk50m: 50MHz 时钟输，

mode:模式选择0：计时模式1：设置闹钟模式

mcheck:手动调整时间

turn:手动调整时间，在时、分之间选择

change:对选中的数据调整

led hourl，led_hour0，led_minul，led_minu0，led_secl,led sec0；

alert: 闹钟输出

ld_alert: 是否设置了闹钟

ld_hour,id_min,ld_sec：在调整时，指示选中了时，分还是秒*/

module

clock(clk50m,mode,turn,change,mreset,led_hour1,led_hour0,led_minu1,led_minu0, led_sec1,led_sec0, alert,ld_alert,ld_check,ld_hour,ld_min,ld_sec);

input clk50m;

input mode; // key0键

input turn; //keyl键

input change; // key2 键

input mreset; //switch0复位，低电平有效

output alert; //gpioO->IOAO

output ld_alert; //ledgO-led19

output ld_check; //ledgl-led22

output ld_hour; //ledr3-led13

output ld_min; //ledr9-led9

output ld_sec; //ledr7-led7

output[6:0] led_hour1;

output[6:0] led_hour0;

output[6:0] led_minu1;

output[6:0] led_minu0;

output[6:0]led_sec1;

output[6:0]led_sec0;

reg [1:0] modestate;

//00: 计时模式10:闹钟模式; 01：手动调整模式；11:非法模式

wire nowmode;//记录当前模式，0：计时模式；1: 设置闹钟模式

wire ischecking; //是否在手动调整时间

assign {nowmode, ischecking}=modestate;

always@(negedge mode)//两个按钮都是低电平有效

begin

case (modestate)

2'b00 : modestate<=2'b10; //设置闹钟模式优先

2'b10: modestate<=2'b01; //手动调整模式

2'b01: modestate<=2'b00;

default :modestate<=2'b00;

endcase

end

wire reset, clk_1hz;

switch #(8) rmjitter(clk50m,mresetr,reset);

clk50mtol genlhz (clk50m, clk_1hz) ; //生成1Hz的时钟

wire [2 : 0] selcode; //对turn信号在不同模式

bitsel seldecoder (nowmode, ischecking, turn, selcode, reset);

wire [3:0] clocktime0,clocktimel,clocktime2,clocktime3,clocktime4,clockthre5;

//计时输出的时钟数值

wire clockalarmon; //整点报时的闹钟输出

wire [2 : 0] counterselcode;

assign counterselcode=(modestate==2'b01)?selcode:3'b000;

counter_time clock_time (clk_1hz,counterselcode,~change,clocktime5,clocktime4,clocktime3,clocktime2,clock time1,clocktime0,clockalarmon,reset);

wire[3:0] alarmtime0,alarmtime1,alarmtime2,alarmtime3;

wire alarmon;

alarm_time alarm_time ( clk_1hz , nowmode , selcode [ 2 : 1] , change ,

{clocktime5, clocktime4, clocktime3, clocktime2, clocktime1},

{alarmtime3, alarmtime2, alarmtime1, alarmtime0} , alarmon, reset) ;

wire voiceout ;

alarm alarmvoice (clk50m,{clockalarmon, alarmon} ,voiceout, raset) ;

//显示输出部分

assign {ld_hour,ld_min,ld_sec}=(ischecking||nowmode)?selcode:3'b000; assign alert=voiceout;

reg[3:0] showout2,showout3,showout4,showout5;

led led5 (showout5,led_hour1) ; //led译码显示

led led4 (showout4,led_hour0) ;

led led3 (showout3,led_minu1) ;

led led2 (showout2,led_minu0) ;

led led1 (clocktime1,led_sec1) ;

led led0 (clocktime0,led_sec0) ;

always

begin if ( nowmode)

begin showout5=alarmtime3 ; showout4=alarmtime2 ;

showout3=alarmtime1; showout2=alarmtime0 ; end else begin

showout5=clocktime5; showout4=clocktime4 ;

showout3=clocktime3 ; showout2=clocktime2 ; end end

assign ld_alert=nowmode; assign ld_check=ischecking;

endmodule

/*alarm.V：闹铃模块

Clk50m: 50MHz输入时钟

alarmon:闹铃是否打开，2'b00:不打开：2'b01：闹钟;2'b10:整点报时

ala rmoUt:闹铃声音输出*/

module alarm(clk50m,alarmon,alarmout,reset);

input[1:0] alarmon;

input clk50m,reset;

output reg alarmout;

reg[15:0] counter_1k;

wire clk_1k;

assign clk_1k=counter_1k[4];

always@(posedge clk50m)

begin if (counter_1k==20) counter_1k<=0;

else counter_1k<=counter_1k+1'b1; end

wire ddd_du_out,ddd_out;

sound_ddd_du ddd_du (clk_1k,alarmon[1] ,ddd_du_out) ;

sound_ddd ddd(clk_1k,alarmon[0],ddd_out);

always

begin if (!reset)

begin if (alarmon [0]==1'b1) //ddd,闹钟的响铃优先级更高

alarmout=ddd_out ;

else if (alarmon==2'b10) alarmout=ddd_du_out;

else alarmout=0 ;

end else alarmout=0 ;