晶体管资料24c04(pdf 16)
FM24C04
Product Specifications
Absolute Maximum Ratings
Ambient Storage Temperature
–65°C to +150°C
All Input or Output Voltages with Respect to Ground
–0.3V to 6.5V
NC 1
8 VCC
A1 2
7 WP
24C05
A2 3
6 SCL
VSS 4
5 SDA
Pin Names
A1,A2 VSS SDA SCL WP VCC NC
See Package Number N08E, M08A and MTC08
Device Address Inputs Ground Serial Data I/O Serial Clock input Write Protect Power Supply No Connection
This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s). The Standard IIC protocol allows for a maximum of 16K of EEPROM memory which is supported by the Fairchild family in 2K, 4K, 8K, and 16K devices, allowing the user to configure the memory as the application requires with any combination of EEPROMs. In order to implement higher EEPROM memory densities on the IIC bus, the Extended IIC protocol must be used. (Refer to the FM24C32 or FM24C65 datasheets for more information.)
24C1024中文资料
1Features•Low-voltage Operation –2.7 (V CC = 2.7V to 5.5V)•Internally Organized 131,072 x 8•2-wire Serial Interface•Schmitt Triggers, Filtered Inputs for Noise Suppression •Bi-directional Data Transfer Protocol•400 kHz (2.7V) and 1 MHz (5V) Clock Rate•Write Protect Pin for Hardware and Software Data Protection •256-byte Page Write Mode (Partial Page Writes Allowed)•Random and Sequential Read Modes •Self-timed Write Cycle (5 ms Typical)•High Reliability–Endurance: 100,000 Write Cycles/Page –Data Retention: 40 Years•8-lead PDIP , 8-lead EIAJ SOIC, 8-lead LAP and 8-ball dBGA TM PackagesDescriptionThe AT24C1024 provides 1,048,576 bits of serial electrically erasable and program-mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device’s cascadable feature allows up to 2 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead Leadless Array (LAP) and 8-ball dBGA packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) versions.Pin ConfigurationsPin Name Function A1Address Input SDA Serial Data SCL Serial Clock Input WPWrite Protect NCNo Connect8-lead PDIP8-lead Leadless ArrayBottom View8-lead SOIC8-ball dBGABottom View2AT24C10241471H–SEEPR–03/03Block DiagramAbsolute Maximum Ratings*Operating Temperature..................................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature.....................................-65°C to +150°C Voltage on Any Pinwith Respect to Ground.....................................-1.0V to +7.0V Maximum Operating Voltage ..........................................6.25V DC Output Current........................................................5.0 mA3AT24C10241471H–SEEPR–03/03Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A1): The A1 pin is a device address input that can be hard-wired or left not connected for hardware compatibility with AT24C128/256/512. When the A1pin is hardwired, as many as two 1024K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). When the pin is not hardwired, the default A1 is zero.WRITE PROTECT (WP): The hardware Write Protect pin is useful for protecting the entire contents of the memory from inadvertent write operations. The write-protect input, when tied to GND, allows normal write operations. When WP is tied high to V CC , all write operations to the memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP to V CC prior to a write operation creates a software write-protect function.Memory OrganizationAT24C1024, 1024K SERIAL EEPROM: The 1024K is internally organized as 512 pages of 256 bytes each. Random word addressing requires a 17-bit data word address.4AT24C10241471H–SEEPR–03/03Pin Capacitance (1)Note:1.This parameter is characterized and is not 100% tested.DC CharacteristicsNote:1.V IL min and V IH max are reference only and are not tested.Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +2.7V.Symbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 1, SCL)6pFV IN = 0VApplicable over recommended operating range from: T AI = -40°C to +85°C, V CC = +2.7V to +5.5V, T AC = 0°C to +70°C,V CC = +2.7V to +5.5V (unless otherwise noted).Symbol Parameter Test ConditionMin TypMax Units V CC Supply Voltage 2.75.5V I CC Supply Current V CC = 5.0V READ at 400 kHz 2.0mA I CC Supply Current V CC = 5.0V WRITE at 400 kHz 5.0mA I SB Standby Current V CC = 2.7V V IN = V CC or V SS3.0µA V CC = 5.5V 6.0µA I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage CurrentV OUT = V CC or V SS0.053.0µA V IL Input Low Level (1)-0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL Output Low LevelV CC = 3.0VI OL = 2.1 mA0.4V5AT24C10241471H–SEEPR–03/03AC Characteristics2.AC measurement conditions:R L (connects to V CC ): 1.3 k Ω (2.7V , 5V)Input pulse voltages: 0.3 V CC to 0.7 V CC Input rise and fall times: ≤50 nsInput and output timing reference voltages: 0.5 V CCApplicable over recommended operating range from T A = -40°C to +85°C, V CC = +2.7V to +5.5V, C L = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.Symbol ParameterTest Conditions MinMax Units f SCL Clock Frequency, SCL 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 1000400kHz t LOW Clock Pulse Width Low 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.41.3µs t HIGH Clock Pulse Width High 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.40.6µs t AA Clock Low to Data Out Valid4.5V ≤ V CC ≤5.5V 2.7V ≤ V CC ≤ 5.5V 0.050.050.550.9µs t BUF Time the bus must be free before a new transmission can start (1) 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.51.3µs t HD.STA Start Hold Time 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 0.250.6µs t SU.STA Start Setup Time 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V0.250.6µs t HD.DAT Data In Hold Time 0µs t SU.DA T Data In Setup Time 100ns t R Inputs Rise Time (1)0.3µs t F Inputs Fall Time (1) 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V 100300ns t SU.STO Stop Setup Time 4.5V ≤ V CC ≤ 5.5V 2.7V ≤ V CC ≤ 5.5V0.250.6µs t DH Data Out Hold Time 50ns t WRWrite Cycle Time10ms Endurance (1) 5.0V , 25°C, Page Mode100KWrite Cycles6AT24C10241471H–SEEPR–03/03Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the Stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-edge that it has received each word.STANDBY MODE: The AT24C1024 features a low-power standby mode which is enabled: a)upon power-up and b)after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:1.Clock up to 9 cycles,2.Look for SDA high in each cycle while SCL is high.3.Create a start condition.7AT24C10241471H–SEEPR–03/03Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)Note:1.The write cycle time t WRis the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.8AT24C10241471H–SEEPR–03/03Data ValidityStart and Stop DefinitionOutput Acknowledge9AT24C10241471H–SEEPR–03/03DeviceAddressingThe 1024K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1). The device address word con-sists of a mandatory one, zero sequence for the first five most significant bits as shown. This is common to all 2-wire EEPROM devices.The 1024K uses the one device address bit, A1, to allow up to two devices on the same bus.The A1 bit must compare to the corresponding hardwired input pin. The A1 pin uses an inter-nal proprietary circuit that biases it to a logic low condition if the pin is allowed to float.The seventh bit (P 0) of the device address is a memory page address bit. This memory page address bit is the most significant bit of the data word address that follows. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state.DATA SECURITY: The AT24C1024 has a hardware data protection scheme that allows the user to write-protect the entire memory when the WP pin is at V CC .WriteOperationsBYTE WRITE: To select a data word in the 1024K memory requires a 17-bit word address.The word address field consists of the P 0 bit of the device address, then the most significant word address followed by the least significant word address (refer to Figure 2)A write operation requires the P 0 bit and two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller,then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, T WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2).PAGE WRITE: The 1024K EEPROM is capable of 256-byte page writes.A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 255 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must ter-minate the page write sequence with a stop condition (refer to Figure 3).The data word address lower 8 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 256 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “rollover” during write is from the last byte of the current page to the first byte of the same page.ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue.10AT24C10241471H–SEEPR–03/03ReadOperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations:current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “rollover”during read is from the last byte of the last memory page, to the first byte of the first page.Once the device address with the read/write select bit set to one is clocked in and acknowl-edged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condi-tion (refer to Figure 4).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a fol-lowing stop condition (refer to Figure 5).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero, but does generate a following stop condition (refer to Figure 6).11AT24C10241471H–SEEPR–03/03Figure 1. Device AddressFigure 2. Byte WriteFigure 3. Page WriteFigure 4.Current Address Read12AT24C10241471H–SEEPR–03/03Figure 5. Random ReadFigure 6.Sequential Read13AT24C10241471H–SEEPR–03/03Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.Ordering InformationOrdering CodePackage Operation RangeA T24C1024-10CI-2.7A T24C1024C1-10CI-2.7A T24C1024-10PI-2.7A T24C1024W-10SI-2.7A T24C1024-10UI-2.78CN38CN18P38S28U8Industrial (-40°C to 85°C)Package Type8CN38-lead, 0.230" Wide, Leadless Array Package (LAP)8CN18-lead, 0.300" Wide, Leadless Array Package (LAP)8P38-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)8S28-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)8U88-ball, die Ball Grid Array Package (dBGA)Options-2.7Low Voltage (2.7V to 5.5V)14AT24C10241471H–SEEPR–03/03Packaging Information8CN3 – LAP15AT24C10241471H–SEEPR–03/038CN1 – LAP16AT24C10241471H–SEEPR–03/038P3 – PDIP17AT24C10241471H–SEEPR–03/038S2 – EIAJ SOIC18AT24C10241471H–SEEPR–03/038U8 – dBGA1471H–SEEPR–03/03xMDisclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906Tel: 1(719) 576-3300Fax: 1(719) 540-1759Scottish Enterprise Technology Park Maxwell BuildingEast Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000Fax: (44) 1355-242-743RF/AutomotiveTheresienstrasse 2Postfach 353574025 Heilbronn, Germany Tel: (49) 71-31-67-0Fax: (49) 71-31-67-23401150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906Tel: 1(719) 576-3300Fax: 1(719) 540-1759Biometrics/Imaging/Hi-Rel MPU/High Speed Converters/RF DatacomAvenue de Rochepleine BP 12338521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00Fax: (33) 4-76-58-34-80e-mailliterature@Web Site© Atmel Corporation 2003. All rights reserved. Atmel ® and combinations thereof, are the registered trademarks, and dBG A ™ is the trademark of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.。
24lc04
WP, SCL and SDA pins: High level input voltage Low level input voltage Hysteresis of Schmitt trigger Inputs Low level output voltage
VIH VIL VHYS
VOL
.7 VCC —
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
.05 VCC
— .3 VCC
—
—
.40
Input leakage current
ILI
-10
10
Output leakage current
ILO
-10
10
Pin capacitance (all inputs/outputs)
CIN, COUT
—
10
Operating current
ICC WRITE
FIGURE 1-1: BUS TIMING START/STOP
VHYS
SCL SDA
TSU:STA
THD:STA
TSU:STO
START
STOP
DS21051E-page 2
© 1996 Microchip Technology Inc.
24LC04B/08B
TABLE 1-3: AC CHARACTERISTICS
24C04中文资料
24C02串行E2PROM的读写I2C总线是一种用于IC器件之间连接的二线制总线。
它通过SDA（串行数据线）及SCL（串行时钟线)两根线在连到总线上的器件之间传送信息，并根据地址识别每个器件：不管是单片机、存储器、LCD驱动器还是键盘接口。
1．I2C总线的基本结构采用I2C总线标准的单片机或IC器件，其内部不仅有I2C接口电路，而且将内部各单元电路按功能划分为若干相对独立的模块，通过软件寻址实现片选，减少了器件片选线的连接。
CPU不仅能通过指令将某个功能单元电路挂靠或摘离总线，还可对该单元的工作状况进行检测，从而实现对硬件系统的既简单又灵活的扩展与控制。
I2C总线接口电路结构如图1所示。
2．双向传输的接口特性传统的单片机串行接口的发送和接收一般都各用一条线，如MCS51系列的TXD和RXD，而I2C 总线则根据器件的功能通过软件程序使其可工作于发送或接收方式。
当某个器件向总线上发送信息时，它就是发送器(也叫主器件)，而当其从总线上接收信息时，又成为接收器(也叫从器件)。
主器件用于启动总线上传送数据并产生时钟以开放传送的器件，此时任何被寻址的器件均被认为是从器件。
I2C总线的控制完全由挂接在总线上的主器件送出的地址和数据决定。
在总线上，既没有中心机，也没有优先机。
总线上主和从(即发送和接收)的关系不是一成不变的，而是取决于此时数据传送的方向。
SDA和SCL均为双向I/O线，通过上拉电阻接正电源。
当总线空闲时，两根线都是高电平。
连接总线的器件的输出级必须是集电极或漏极开路，以具有线“与”功能。
I2C总线的数据传送速率在标准工作方式下为100kbit/s，在快速方式下，最高传送速率可达400kbit/s。
3．I2C总线上的时钟信号在I2C总线上传送信息时的时钟同步信号是由挂接在SCL时钟线上的所有器件的逻辑“与”完成的。
SCL线上由高电平到低电平的跳变将影响到这些器件，一旦某个器件的时钟信号下跳为低电平，将使SCL线一直保持低电平，使SCL线上的所有器件开始低电平期。
24LC04中文资料
TABLE 1-1: PIN FUNCTION TABLE
Name
VSS SDA SCL WP VCC A0, A1, A2
Function
Ground Serial Address/Data I/O Serial Clock Write Protect Input +2.5V to 5.5V Power Supply No Internal Connection
TABLE 1-2: DC CHARACTERISTICS
VCC = +2.5V to +5.5V Commercial (C): Tamb = 0˚C to +70˚C Industrial (I): Tamb = -40˚C to +85˚C
Parameter
Symbol
Min
Max Units
TABLE 1-3: AC CHARACTERISTICS
Parameter
Symbol
STANDARD MODE
VCC = 4.5 - 5.5V FAST MODE Units
Remarks
Min Max Min Max
Clock frequency
FCLK
—
100
—
400 kHz
Clock high time
—
10M
—
10M
— cycles 25°C, Vcc = 5.0V, Block Mode
元器件交易2网4LwwCw.c0ec4b2Bb.c/o0m8B
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maximum Ratings*
VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS .............. -0.3V to VCC + 1.0V Storage temperature ..................................... -65˚C to +150˚C Ambient temp. with power applied ................ -65˚C to +125˚C Soldering temperature of leads (10 seconds) ............. +300˚C ESD protection on all pins ..................................................≥ 4 kV *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
S-24C04BPHAL资料
Rev.2.1_002-WIRE CMOS SERIAL E2PROM S-24C04BPHALThe S-24C04BPHAL is a 2-wire, low-power, wide-range-operation 4k bit serial E2PROM organized as512 words × 8 bits. Page write and sequential readare possible.Features• Low power consumption Standby: 1.0 µA max. (V CC = 5.5 V)Operating: 0.8 mA max. (V CC = 5.5 V)0.3 mA max. (V CC= 3.3 V)• Wide operating voltage range: Reading: 1.6 to 5.5 VWriting: 1.7 to 5.5 V• Page write: 16 bytes/page• Sequential read• Operating frequency: 400 kHz (V CC = 5 V ±10%)• Endurance: 106 cycles/word*1*1. For each address (Word: 8 bits)• Data retention: 10 years• Write protection 100%• Lead-free productsPackageDrawing CodePackage NamePackage Tape Reel WLP-5A HA005-A HA005-A HA005-ACaution This product is intended for use in general electronic devices such as consumer electronics, office equipment, and communications devices. Before using the product inmedical equipment or automobile equipment including car audio, keyless entry, andengine control units, be sure to contact SII.2-WIRE CMOS SERIAL E 2PROMS-24C04BPHAL Rev.2.1_00Pin ConfigurationWLP-5A Bottom viewTable 1Pin No. Symbol Description 1 VCC Power supply 2SDASerial data I/O3 WP Write Protection pinConnected to Vcc: Protection validConnected to GND: Protection invalid4 SCL Serial clock input5 GND GroundRemark See Dimensions for details of the package drawings. Figure 1S-24C04BPHAL2-WIRE CMOS SERIAL E2PROM Rev.2.1_00S-24C04BPHALBlock DiagramSCLSDAFigure 2Absolute Maximum RatingsTable 2UnitItem SymbolRatingsPower supply voltage V CC −0.3 to +7.0 VInput voltage V IN −0.3 to V CC+ 0.3 VOutput voltage V OUT −0.3 to V CC VOperating ambient temperature T opr−40 to + 85 °CStorage temperature T stg −65 to + 150 °CCaution The absolute maximum ratings are rated values exceeding which theproduct could suffer physical damage. These values must thereforenot be exceeded under any condition.2-WIRE CMOS SERIAL E2PROMS-24C04BPHAL Rev.2.1_00Recommended Operating ConditionsTable 3Max.Typ.UnitMin.Item SymbolConditionsReading 1.6− 5.5 V Power supply voltage V CCWriting 1.7− 5.5 VV CC = 2.5 to 5.5 V 0.7 × V CC−V CC V High-level input voltage V IHV CC = 1.6 to 2.5 V 0.8 × V CC−V CC VV CC = 2.5 to 5.5 V 0.0 −0.3 × V CC V Low-level input voltage V ILV CC = 1.6 to 2.5 V 0.0 −0.2 × V CC VPin CapacitanceTable 4(Ta = 25°C, f = 1.0 MHz, Vcc = 5 V)Max.Typ.UnitMin.Item SymbolConditionsInput capacitance C IN V IN= 0 V (SCL, WP) −−10 pFInput/output capacitance C I/O V I/O = 0 V (SDA) −−10 pFEnduranceTable 5Operating Temperature Min. Typ. Max. Unit Item SymbolEndurance NW −40 to +85°C 106 −−Cycles/word*1 *1. For each address (Word: 8 bits)2-WIRE CMOS SERIAL E 2PROMRev.2.1_00S-24C04BPHALDC Electrical CharacteristicsTable 6V CC = 4.5 to 5.5 V V CC = 2.5 to 4.5 V V CC = 1.6 to 2.5 VItem Symbol Conditions Min.Typ.Max.Min.Typ.Max. Min. Typ. Max.UnitCurrent consumption (READ)I CC1 f = 100 kHz − − 0.8*1− − 0.3 − − 0.2 mA Current consumption (PROGRAM) I CC2 f = 100 kHz − − 4.0 − − 1.5 − − 1.5*2mA *1. f = 400 kHz*2. V CC = 1.7 to 2.5 VTable 7V CC = 4.5 to 5.5 V V CC = 2.5 to 4.5 V V CC = 1.6 to 2.5 V Item Symbol ConditionsMin.Typ.Max.Min.Typ.Max. Min. Typ. Max.Unit Standby currentconsumptionI SB V IN = V CC or GND − − 1.0 − − 0.6 − − 0.4 µA Input currentleakageI LI V IN = GND to V CC −0.1 1.0 − 0.1 1.0 − 0.1 1.0 µA Output currentleakageI LO V OUT = GND to V CC −0.1 1.0 − 0.1 1.0 − 0.1 1.0 µA I OL = 3.2 mA − − 0.4 − − 0.4 − − − V Low-level output voltage V OL I OL = 1.5 mA − − 0.3 − − 0.3 − − 0.5 V Current addresshold voltageV AH − 1.5 − 5.5 1.5 − 4.5 1.5 − 2.5 V2-WIRE CMOS SERIAL E 2PROMS-24C04BPHALRev.2.1_00AC Electrical CharacteristicsTable 8 Measurement ConditionsInput pulse voltage 0.1 × V CC to 0.9 × V CC Input pulse rise/fall time 20 ns Output judgment voltage 0.5 × V CC Output load 100 pF + pull-up resistor 1.0 k Ω= 100 pFCC= 1.0 k ΩFigure 3 Output Load CircuitTable 9V CC = 4.5 to 5.5 V V CC = 1.6 to 4.5 VItem Symbol Min. Typ. Max. Min. Typ. Max.UnitSCL clock frequency f SCL 0 − 400 0 − 100 kHz SCL clock time “L” t LOW 1.0 − − 4.7 − − µs SCL clock time “H” t HIGH 0.9 − − 4.0 − − µs SDA output delay time t AA 0.1 − 0.9 0.1 −3.5 µs SDA output hold time t DH 50 − − 100 − − ns Start condition setup time t SU. STA 0.6 − −4.7 − − µs Start condition hold time t HD. STA 0.6 − − 4.0 − − µs Data input setup time t SU. DAT 100 − − 200 − − ns Data input hold time t HD. DAT 0 − − 0 − − ns Stop condition setup time t SU. STO 0.6 − − 4.7 − − µs SCL • SDA rise time t R − − 0.3 − − 1.0 µs SCL • SDA fall time t F − − 0.3 − − 0.3 µs Bus release time t BUF 1.3 − − 4.7 −−µsNoise suppression timet I− −50−−100 nsSCLSDA INSDA OUTFigure 4 Bus Timing2-WIRE CMOS SERIAL E2PROM Rev.2.1_00S-24C04BPHALTable 10Item Symbol Min. Typ. Max. UnitWrite time t WR 4.0 10.0 msSCLSDAAcknowledgeFigure 5 Write Cycle Timing2-WIRE CMOS SERIAL E2PROMS-24C04BPHAL Rev.2.1_00Pin Functions1. SDA (serial data input/output) pinThe SDA pin is used for bidirectional transfer of serial data. It consists of a signal input pin and an Nch open-drain transistor output pin. Usually pull up the SDA line to V CC via a resistor, and use it with other open-drain or open-collector output devices connected in a wired-OR configuration.2. SCL (serial clock input) pinThe SCL pin is used for serial clock input. It is capable of processing signals at the rising and falling edges of the SCL clock input signal. Make sure the rise time and fall time conform to the specifications.3. WP pinThe WP pin is used for write protection. When there is no need for write protection, connect the pin to GND; when there is a need for write protection, connect the pin to V CC.2-WIRE CMOS SERIAL E2PROM Rev.2.1_00S-24C04BPHAL Operation1. Start conditionWhen the SDA line changes from “H” to “L” with the SCL line at “H”, the device is in the start condition.All operations begin from the start condition.2. Stop conditionWhen the SDA line changes from “L” to “H” with the SCL line at “H”, the device is in the stop condition.When the device receives the stop condition signal during a read sequence, the read operation is interrupted, and the device enters standby mode.When the device receives the stop condition signal during a write sequence, the retrieval of write data is halted, and rewriting the E2PROM starts.t SU. STOt SU. STA t HD. STAStart condition Stop conditionFigure 6 Start/Stop Condition2-WIRE CMOS SERIAL E2PROMS-24C04BPHAL Rev.2.1_003. Data transferChanging the SDA line while the SCL line is “L” allows the data to be transferred.A start or stop condition is recognized when the SDA line changes while the SCL line is “H”.SCLSDAFigure 7 Data Transfer Timing4. Acknowledgment8 bits of data are transferred in succession. The device on the system bus that receives the data changesthe SDA line to “L” during the 9th clock cycle and outputs the acknowledge signal to inform that it has received the data.The device does not output the acknowledge signal while the E2PROM is being rewritten.SCL(E2SDASDA(E2Figure 8 Acknowledge Output Timing5. Device addressingTo perform data communications, the master device mounted on the system outputs the start condition signal to the slave device. Next, the master device outputs a 7-bit device address and a 1-bit read/write instruction code onto the SDA bus.The higher 4 bits of the device address are called the “Device Code”, and are fixed to “1010”. The following 2 bits are “don’t care” bits.When the comparison results match, the slave device outputs the acknowledge signal during the 9th clock cycle.Device codeS-24C04BPHALMSBLSBDon’t care Remark X: Don’t careFigure 9 Device AddressIn the S-24C04BPHAL, the 7th bit is a page address bit.Accordingly, when P0 = 0, the first half of the memory area (2 Kb: addresses 000h to 0FFh) is selected; when P0 = 1, the second half of the memory area (2 Kb; addresses 100h to 1FFh) are selected.6. Write operation6.1 Byte writeWhen the E 2PROM receives a 7-bit device address and the 1-bit read/write instruction code “0”, following the start condition signal, it outputs the acknowledge signal.Next, when the E 2PROM receives an 8-bit word address, it outputs the acknowledge signal.After the E 2PROM receives 8-bit write data and outputs the acknowledge signal, it receives the stop condition signal. Next, rewriting the specified memory address of the E 2PROM starts.While the E 2PROM is being rewritten, all operations are prohibited and the acknowledge signal is not output.S T A W R I M S B SDA lineADR INC(ADDRESS INCREMENT)A C K S T A C KA C KFigure 10 Byte Write6.2 Page writeUp to 16 bytes per page can be written in the S-24C04BPHAL.Basic data transfer procedures are the same as those in “Byte write”. The S-24C04BPHAL performs page write by successively receiving 8-bit write data sized pages.When the E2PROM receives a 7-bit device address and the 1-bit read/write instruction code “0” following the start condition signal, it outputs the acknowledge signal. When the E2PROM receives an 8-bit word address, it outputs the acknowledge signal. After the E2PROM receives 8-bit write data and outputs the acknowledge signal, it receives 8-bit write data corresponding to the next word address, and outputs the acknowledge signal. The E2PROM repeats reception of 8-bit write data and output of the acknowledge signal in succession and can receive write data corresponding to the maximum page size. When the stop condition signal is received, E2PROM corresponding to the size of the page on which write data starting from the specified memory address is received starts to be rewritten.S WFigure 11 Page WriteThe lower 4 bits of the word address are automatically incremented each time when the E2PROM receives 8-bit write data. Even when the write data exceeds 16 bytes, the higher 4 bits of the word address and page address P0 remain unchanged, and the lower 4 bits are rolled over and overwritten.6.3 Write ProtectionWrite protection is available in the S-24C04BPHAL. When the WP pin is connected to the V CC , write operation to memory area is forbidden at all.When the WP pin is connected to the GND, the write protection is invalid, and write operation in all memory area is available.Fix the level of the WP pin from the rising edge of SCL for loading the last write data (D0) until the end of the write time (10 ms max.). If the WP pin changes during this time, the address data being written at this time is not guaranteed.There is no need for using write protection, the WP pin should be connected to the GND. The write protection is valid in the operating voltage range.SDAWPSCLFigure 12 WP Pin Fixed Period6.4 Acknowledge PollingAcknowledge polling is used to know the completion of the write cycle in the E 2PROM.After the E 2PROM receives a stop condition and once starts the write cycle, all operations are forbidden and no response is made to the signal transmitted by the master device.Accordingly the master device can recognize the completion of the write cycle in the E 2PROM by detecting a response from the slave device after transmitting the start condition, the device address and the read/write instruction code to the E 2PROM, namely to the slave devices.That is, if the E 2PROM does not generate an acknowledge, the write cycle is in progress and if the E 2PROM generates an acknowledge, the write cycle has been completed. Keep the level of the WP pin fixed until acknowledge is confirmed.It is recommended to use the read instruction "1" as the read/write instruction code transmitted by the master device.7. Read7.1 Current address readThe E 2PROM holds the last accessed memory address during both writing and reading. The memory address is retained as long as the power voltage is the retention voltage V AH or more. Accordingly, when the master device recognizes the position of the address pointer inside the E 2PROM, data can be read from the memory address of the current address pointer without specifying a word address. This is called “Current Address Read”.“Current Address Read” is explained for when the address counter inside the E 2PROM is address “n”.When the E 2PROM receives a 7-bit device address and the 1-bit read/write instruction code “1”, following the start condition signal, it outputs the acknowledge signal.Next, 8-bit data at address “n” is output from the E 2PROM, in synchronization with the SCL clock.The address counter is incremented to address n + 1 at the falling edge of the SCL clock at which the 8th bit of data is output. The master device does not output the acknowledge signal and transmits the stop condition signal to finish reading.M S BDATAFigure 13 Current Address ReadFor recognition of the address pointer inside the E 2PROM, take into consideration the following:The memory address counter inside the E 2PROM is automatically incremented for every falling edge of the SCL clock at which the 8th bit of data is output during reading. During writing, the higher bits of the memory address (higher 4 bits of the word address) are left unchanged and are not incremented at any falling of the SCL clock when the 8th bit of the write data is received.7.2 Random readRandom read is a mode used when data is read from arbitrary memory addresses.To load a memory address into the address counter inside the E2PROM, first perform a dummy write following the procedure below.When the E2PROM receives a 7-bit device address and the 1-bit read/write instruction code “0” following the start condition signal, it outputs the acknowledge signal.Next, the E2PROM receives an 8-bit word address and outputs the acknowledge signal. The memory address has now been loaded into the address counter of the E2PROM.Following this, the E2PROM receives the write data during byte or page writing. However, data reception is not performed during dummy write.The memory address is loaded into the memory address counter inside the E2PROM during dummy write.After that, the master device can read the data starting from the arbitrary memory address by transmitting a new start condition signal and performing the same operation as that in the “Current Address Read”.That is, when the E2PROM receives a 7-bit device address and the 1-bit read/write instruction code “1”following the start condition signal, it outputs the acknowledge signal.Next, 8-bit data is output from the E2PROM in synchronization with the SCL clock. The master device does not output an acknowledge signal and transmits the stop condition signal instead. Reading is then complete.Figure 14 Random Read7.3 Sequential readWhen the E2PROM receives a 7-bit device address and the 1-bit read/write instruction code “1” in both current and random read operations following the start condition signal, it outputs the acknowledge signal.When 8-bit data is output from the E2PROM, in synchronization with the SCL clock, the memory address counter inside the E2PROM is automatically incremented at the falling edge of the SCL clock at which the 8th data is output.When the master device transmits the acknowledge signal, the next memory address data is output.When the master device transmits the acknowledge signal, the memory address counter inside the E2PROM is incremented and data can be read in succession. This is called “Sequential Read”.When the master device does not output an acknowledge signal and transmits the stop condition signal, the read operation is finished.Data can be read in the “Sequential Read” mode in succession. When the memory address counter reaches the last word address, it rolls over to the first memory address.SDAlineFigure 15 Sequential Read8. Address increment timingThe address increment timing is as follows. During a read operation, the memory address counter is automatically incremented at the falling edge of the SCL clock (where the 8th bit of read data is output).During a write operation, the memory address counter is also automatically incremented at the falling edge of the SCL clock when the 8th bit of write data is fetched.SDAAddress incrementFigure 16 Address Increment Timing in Read OperationSCLAddress incrementFigure 17 Address Increment Timing in Write OperationUsing S-24C04BPHAL1. Adding a pull-up resistor to SDA I/O pin and SCL input pinAdd a 1 k Ω to 5 k Ω pull-up resistor to the SCL input pin *1 and the SDA I/O pin in order to enable the functions of the I 2C Bus protocol. Normal communication cannot be provided without a pull-up resistor.*1. When the SCL input pin of the E 2PROM is connected to a tri-state output pin of the microprocessor,connect the same pull-up resistor to prevent a high impedance status from being input to the SCL input pin.This protects the E 2PROM from malfunction due to an undefined output (high impedance) from the tri-state pin when the microprocessor is reset when the voltage drops.2. Slave addressThe S-24C04BPHAL does not have slave address pins (A0, A1, A2). Therefore two or more of this IC cannot be used on the same bus.However, slave addresses can be used without changing the communication software because they are arbitrary addresses in communication with the master device.SDA lineMSBLSBFigure 183. I/O pin equivalent circuitThe I/O pins of this IC do not include pull-up and pull-down resistors. The SDA pin is an open-drain output.The following shows the equivalent circuits.Figure 19 SCL PinFigure 20 WP PinFigure 21 SDA Pin4. Maximum effectiveness of write protectionThe following conditions must be satisfied to prevent erroneous writing at power-on due to write protection.(1) Set the WP pin to high level at a time other than when the write instruction is being executed, includingduring power-on or off.(2) Adjust the phase after power-on.Pulling up the WP pin to V CC to always enable the WP pin at the absolute maximum rated voltage or lower prohibits writing all the time regardless of the conditions of the VCC, SDA, and SCL pins.5. Matching phases while E2PROM is accessedThe S-24C04BPHAL does not have a pin for resetting (the internal circuit), therefore, the E2PROM cannot be forcibly reset externally. If a communication interruption occurs in the E2PROM, it must be reset by software.For example, even if a reset signal is input to the microprocessor, the internal circuit of the E2PROM is not reset as long as the stop condition is not input to the E2PROM. In other words, the E2PROM retains the same status and cannot shift to the next operation. This symptom applies to the case when only the microprocessor is reset when the power supply voltage drops. With this status, if the power supply voltage is restored, reset the E2PROM (after matching the phase with the microprocessor) and input an instruction.The following shows this reset method.[How to reset E2PROM]The E2PROM can be reset by the start and stop instructions. When the E2PROM is reading data “0” or is outputting the acknowledge signal, 0 is output to the SDA line. In this status, the microprocessor cannot output an instruction to the SDA line. In this case, terminate the acknowledge output operation or read operation, and then input a start instruction. Figure 22 shows this procedure.First, input the condition. Then transmit 9 clocks (dummy clocks) of SCL. During this time, the microprocessor sets the SDA line to high level. By this operation, the E2PROM interrupts the acknowledge output operation or data output, so input the start condition*1. When a start condition is input, the E2PROM is reset. To make doubly sure, input the stop condition to the E2PROM. Normal operation is then possible.Figure 22 Resetting E2PROM*1. After 9 clocks (dummy clocks), if the SCL clock continues to be output without a start condition being input, a write operation may be started upon receipt of a stop condition. To prevent this, inputa start condition after 9 clocks (dummy clocks).Remark It is recommended to perform the above reset using dummy clocks when the system is initialized after the power supply voltage has been raised.6. Acknowledge checkThe I2C Bus protocol includes an acknowledge check function as a handshake function to prevent a communication error. This function allows detection of a communication failure during data communication between the microprocessor and E2PROM. This function is effective to prevent malfunction, so it is recommended to perform an acknowledge check on the microprocessor side.7. Built-in power-on-clear circuitE2PROMs have a built-in power-on-clear circuit that initializes the E2PROM. Unsuccessful initialization may cause a malfunction. For the power-on-clear circuit to operate normally, the following conditions must be satisfied for raising the power supply voltage.7.1 Raising power supply voltageRaise the power supply voltage, starting at 0.2 V maximum, so that the voltage reaches the power supply voltage to be used within the time defined by t RISE as shown in Figure 23.For example, when the power supply voltage to be used is 5.0 V, t RISE is 200 ms as shown in Figure 24.The power supply voltage must be raised within 200 ms.V INIT (Max.) Power supply voltage (V CC) 0 V*1*1. 0 V means there is no difference in potential between the V CC pin and the GND pin of the E2PROM.*2. t INIT is the time required to initialize the E2PROM. No instructions are accepted during this time.Figure 23 Raising Power Supply VoltageRise time (t RISE ) Max.[ms]Power supply voltage(V CC ) [V]505.04.03.02.0100150 200 For example:If your E 2PROM supply voltage = 5.0 V, raise the power supply voltage to 5.0 V within 200 ms.Figure 24 Raising Time of Power Supply VoltageWhen initialization is successfully completed via the power-on-clear circuit, the E 2PROM enters the standby status.If the power-on-clear circuit does not operate, the following are the possible causes.(1) Because the E 2PROM has not been initialized, an instruction formerly input is valid or an instructionmay be inappropriately recognized. In this case, writing may be performed.(2) The voltage may have dropped due to power off while the E 2PROM is being accessed. Even if themicroprocessor is reset due to the low power voltage, the E 2PROM may malfunction unless the power-on-clear operation conditions of E 2PROM are satisfied. For the power-on-clear operation conditions of E 2PROM, refer to 7.1 Raising power supply voltage .If the power-on-clear circuit does not operate, match the phase (reset) so that the internal E 2PROM circuit is normally reset. The statuses of the E 2PROM immediately after the power-on-clear circuit operates and when phase is matched (reset) are the same.7.2 Wait for the initialization sequence to endThe E 2PROM executes initialization during the time that the supply voltage is increasing to its normal value. All instructions must wait until after initialization. The relationship between the initialization time (t INIT ) and rise time (t RISE ) is shown in Figure 25.Rise time (t RISE )[s]E 2PROM initialization time (t INIT ) Max.[s]100 m 10 m1.0 m 100 µ10 µ1.0 µ1.0 µ 10 µ 100 µ1.0 m 10 m 100 mFigure 25 Initialization Time of E 2PROM8. Data hold time (t HD. DAT= 0 ns)If SCL and SDA of the E2PROM are changed at the same time, it is necessary to prevent the start/stop condition from being mistakenly recognized due to the effect of noise. If a start/stop condition is mistakenly recognized during communication, the E2PROM enters the standby status.It is recommended that SDA is delayed from the falling edge of SCL by 0.3 µs minimum in the S-24C04BPHAL. This is to prevent time lag caused by the load of the bus line from generating the stop (or start) condition.Figure 26 E2PROM Data Hold Time9. SDA pin and SCL pin noise suppression timeThe S-24C04BPHAL includes a built-in low-pass filter to suppress noise at the SDA and SCL pins. This means that if the power supply voltage is 5.0 V (at room temperature), noise with a pulse width of 150 ns or less can be suppressed.The guaranteed for details, refer to noise suppression time (t I) in Table 9.Noise suppression time (t I) Max.[ns]2001003002 3 4 5Power supply voltage (V CC)[V]Figure 27 Noise Suppression Time for SDA and SCL Pins10. Trap: E2PROM operation in case that the stop condition is received during write operation beforereceiving the defined data value (less than 8-bit) to SCL pinWhen the E2PROM receives the stop condition signal compulsorily, during receiving 1 byte of write data, “write” operation is aborted.When the E2PROM receives the stop condition signal after receiving 1 byte or more of data for “page write”, 8-bit of data received normally before receiving the stop condition signal can be written.11. Trap: E2PROM operation and write data in case that write data is input more than defined page size at“page write”When write data is input more than defined page size at page write operation, for example, S-24C04BPHAL (which can be executed 16-byte page write) is received data more than 17 byte, 8-bit data of the 17th byte is over written to the first byte in the same page. Data over the capacity of page address cannot be written.12. Trap: Severe environments•Absolute maximum ratings: Do not operate these ICs in excess of the absolute max ratings, as listed on the data sheet. Exceeding the supply voltage rating can cause latch-up.•Operations with moisture on the E2PROM pins may occur malfunction by short-circuit between pins.Especially, in occasions like picking the E2PROM up from low temperature tank during the evaluation.Be sure that not remain frost on E2PROM pin to prevent malfunction by short-circuit.Also attention should be paid in using on environment, which is easy to dew for the same reason.Precautions•Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit.•SII claims no responsibility for any and all disputes arising out of or in connection with any infringement of the products including this IC upon patents owned by a third party.Precautions for WLP package•The side of device silicon substrate is exposed to the marking side of device package. Since this portion has lower strength against the mechanical stress than the standard plastic package, chip, crack, etc should be careful of the handing of a package enough. Moreover, the exposed side of silicon has electrical potential of device substrate, and needs to be kept out of contact with the external potential.•In this package, the overcoat of the resin of translucence is carried out on the side of device area. Keep it mind that it may affect the characteristic of a device when exposed a device in the bottom of a high light source.。
CW24C02_04_ 08_16 技术资料
2K位，4K位，8K位和16K位串行I2C总线EEPROM 1. 描述引脚排列CW24C02/02B/02C/04/04A/08/08B/08C/16/16A是电可擦除PROM，分别采用256/512/1024/2048×8-bit的组织结构以及两线串行接口。
电压可允许低至1.8V，待机电流和工作电流分别为1μA和1mA。
CW24C02/02B/02C/04/04A/08/08B/08C/16/16A 具有页写能力，每页分别为8/16/16/16字节。
2. 特点●宽工作电压：1.8V ~ 5.5V●低电压技术- 1mA典型工作电流- 1μA典型待机电流●存储器组织结构- CW24C02，256 X 8（2K bits）- CW24C04，512 X 8（4K bits）- CW24C08，1024 X 8（8K bits）- CW24C16，2048 X 8（16K bits）●2线串行接口，完全兼容I2C总线●I2C时钟频率为1 MHz（5V），400 kHz（1.8V，2.5V，2.7V）●施密特触发输入噪声抑制●硬件数据写保护●内部写周期（最大5 ms）●可按字节写●页写：8字节页（CW24C02），16字节页（CW24C04/08/16）●可按字节，随机和序列读●自动递增地址●ESD保护大于2.5kV（顶视）●高可靠性- 擦写寿命：100万次- 数据保持时间：100年●封装：DIP8L、SOP8L、TSSOP8、DFN8、SOT23-5、TSOT23-5 ●无铅工艺，符合RoHS标准3. 应用领域●智能化仪器仪表●工业控制●家用电器●汽车电子● 计算机/笔记本电脑 ● 通信设备4. 订购信息注：后缀A 或B 是新版本号“A ”版减小了待机电流“B ”版减小了待机电流和写周期 “C ”版同“B ”版5. 框图图1. 框图6. 引脚说明7. 最大额定参数8. 推荐工作条件（应在推荐工作条件下实现功能）9. 引脚电容10. 直流电气特性（推荐工作条件：T11. 交流电气特性图2. 总线时序图3. 写周期时序12. 存储结构13. 详细操作说明13.1 I2C数据总线和传输协议I2C总线接口CW24CXX支持I2C总线传输协议。
HC24C04数据手册_v0.01
此时器件进入内部定时的写周期（非易失性寄存器的写时间），TWR。所有的输入操作在该 写周期内均无效，而且只有在写周期结束后，器件才会对操作指令做出应答。（参见图 7）
图7 SCL：串行时钟输入，DSA：串行数据输入/输出
注：写周期TWR是指一个写序列最后一个有效停止命令到内部擦/写周期结束的时间。
一旦时钟将读/写位为高的器件地址送入，并得到器件应答后，就会串行输出当前地址的数 据。主控器件不对器件返回应答信号，而是产生一个紧随的停止命令。（参见图9）
图9 当前地址读
自由地址读：自由读需要通过假的字节写操作来获得数据地址。一旦器件地址和数据地址 字节被时钟送入并得到器件的应答后，主控器件必须产生另一个起始命令。主控器件通过发送 一个读/写选择位为高的器件地址来开启一次当前地址读。器件对器件地址做出应答后由时钟串 行输出数据。主控器件不对数据传输返回应答信号，而是产生一个紧随的停止命令。（参见图 10）
单位
kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Write Cycles
图 1 总线时序
-6-
HC24C04
器件操作
时钟及数据传输：SDA 引脚通常被外围器件拉高。SDA 引脚的数据应在 SCL 为低时变化（参 见图 2）；当数据在 SCL 为高时变化，将视为下文所述的一个起始或停止命令。
0.4
1.0
mA
2.0
3.0
mA
—
1.0
μA
—
3.0
μA
0.05
3.0
μA
—
VCC×0.3 V
— VCC＋0.3 V
—
0.4
V
HT24LC04中文资料
HT24LC044K 2-Wire CMOS Serial EEPROMBlock DiagramPin Assignment16th May ¢99Features·Operating voltage:2.4V~5.5V ·Low power consumption -Operation:5mA max.-Standby:5m A max.·Internal organization -4K (HT24LC04):512´8·2-wire serial interface·Write cycle time:5ms max.·Automatic erase-before-write operation·Partial page write allowed ·8-byte page write modes·Write operation with built-in timer ·Hardware controlled write protection ·40-year data retention·106erase/write cycles per word ·8-pin DIP/SOP/TSSOP package ·Commerical temperature range (0°C to +70°C)General DescriptionThe HT24LC04is a 4K-bit serial read/write non-volatile memory device using the CMOS floating gate process.Its 4096bits of memory are organized into 512words and each word is 8bits.The device is optimized for use in many in-dustrial and commercial applications wherelow power and low voltage operation are essen-tial.Up to four HT24LC04devices may be con-nected to the same two-wire bus.The HT24LC04is guaranteed for 1M erase/write cy-cles and 40-year data retention.Pin DescriptionAbsolute Maximum RatingsOperating Temperature (Commercial) ................................................................................. 0°C to 70°C Storage Temperature ....................................................................................................... –50°C to 125°C Applied V CC Voltage with Respect to VSS ........................................................................ –0.3V to 6.0V Applied Voltage on any Pin with Respect to VSS ..................................................................–0.3V to V CC+0.3VNote: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maxi-mum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.D.C. Characteristics Ta=0°C to 70°CNote: These parameters are periodically sampled but not 100% tested26th May ’99A.C. Characteristics Ta=0°C to 70°C* The standard mode means V CC=2.4V to 5.5VFor relative timing, refer to timing diagrams36th May ’99Functional Description•Serial clock (SCL)The SCL input is used for positive edge clock data into each EEPROM device and negative edge clock data out of each device.•Serial data (SDA)The SDA pin is bidirectional for serial data transfer. The pin is open-drain driven and may be wired-OR with any number of other open-drain or open collector devices.•A0, A1, A2The HT24LC04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is not connected. (The device addressing is discussed in detail under the Device Addressing section).•Write protect (WP)The HT24LC04 has a write protect pin that provides hardware data protection. The write protect pin allows normal read/write opera-tions when connected to the V SS. When the write protect pin is connected to Vcc, the write protection feature is enabled and operates asMemory organization•HT24LC04, 4K Serial EEPROMInternally organized with 512 8-bit words, random word addressing requires a 9-bit data word address.Device operations•Clock and data transitionData transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clockline is high. Changes in data line while the clock line is high will be interpreted as a START or STOP condition.•Start conditionA high-to-low transition of SDA with SCL highis a start condition which must precede any other command (refer to Start and Stop Defi-nition Timing diagram).•Stop conditionA low-to-high transition of SDA with SCL highis a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram).•AcknowledgeAll addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknow-ledge that it has received each word. This happens during the ninth clock cycle.Device addressingThe 4K EEPROM devices require an 8-bit de-vice address word following a start condition to enable the chip for a read or write operation.The device address word consist of a mandatory one, zero sequence for the first four most signifi-cant bits (refer to diagram showing the Device Address). This is common to all the EEPROM device.The next three bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM. These three bits must compare to their correspondinghard-wired input pins.46th May ’99The 4K EEPROM only use the A2 and A1 device address bits with the third bit as a memory page address bit. The two device address bits must compare to their corresponding hardwired input pins. The A0 pin is not connected.The 8th bit of device address is the read/write operation select bit. A read operation is initi-ated if this bit is high and a write operation is initiated if this bit is low.If the comparison of the device address succeed the EEPROM will output a zero at ACK bit. If not, the chip will return to a standby state.Write operations•Byte writeA write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this ad-dress, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. After receiving the 8-bit data word, the EEPROM will output a zero and the address-ing device, such as a microcontroller, must terminate the write sequence with a stop con-dition. At this time the EEPROM enters an internally-timed write cycle to the non-vola-tile memory . All inputs are disabled during this write cycle and EEPROM will not re-spond until the write is completed (refer to Byte write timing).•Page writeThe 4K device is capable of 16-byte page writes.A page write is initiated the same as byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM ac-knowledges the receipt of the first data word,the microcontroller can transmit up to fifteen more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition.The data word address lower four bits are internally incremented following the receipt of each data word. The higher data word ad-dress bits are not incremented, retaining the memory page row location (refer to Page write timing).•Acknowledge pollingSince the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately . This involves the master sending a start condition followed by the control byte for a write command (R/W=0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is completed, then the device will return the ACK and the master can then pro-ceed with the next read or write command.•Write protectThe HT24LC04 can be used as a serial ROM when the WP pin is connected to VCC. Pro-gramming will be inhibited and the entire memory will be write-protected.•Read operationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read opera-tions: current address read, random address read and sequential read.•Current address readThe internal data word address counter main-tains the last address accessed during the last read or write operation, incremented by one.This address stays valid between operations as long as the chip power is maintained. The address roll over during read from the last byte of the last memory page to the first byte of the first page. The address roll over during write from the last byte of the current page to the first byte of the same page. Once the de-vice address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but generates a following stop condition (refer to Current read timing).•Random readA random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the EEPROM. The microcontroller must then generate another start condition. The micro-controller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM ac-knowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does gener-ates a following stop condition (refer to Ran-dom read timing).Acknowledge polling flowHT24LC0466th May ’99Timing DiagramsNote: The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command.•Sequential readSequential reads are initiated by either a cur-rent address read or a random address read.After the microcontroller receives a data word,it responds with an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word ad-dress and serially clock out sequential datawords. When the memory address limit is reached, the data word address will roll over and the sequential read continues. The se-quential read operation is terminated when the microcontroller does not respond with a zero but generates a following stop condition(refer to Sequential read timing).Holtek Semiconductor Inc. (Headquarters)No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.Tel: 886-3-563-1999Fax: 886-3-563-1189Holtek Semiconductor Inc. (Taipei Office)5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.Tel: 886-2-2782-9635Fax: 886-2-2782-9636Fax: 886-2-2782-7128 (International sales hotline)Holtek Microelectronics Enterprises Ltd.RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong KongTel: 852-2-745-8288Fax: 852-2-742-865786th May ’99。
晶体管培训资料
日期:CATALOGUE目录•晶体管基础•晶体管的应用电路•晶体管的选型与检测•晶体管的实际应用与未来发展晶体管基础定义工作原理晶体管定义与原理晶体管由三个区域组成，分别是基区、发射区和集电区，各区域之间通过结隔离，形成三个电极，即基极、发射极和集电极。
晶体管类型与结构结构NPN型与PNP型电流放大系数饱和压降击穿电压最大耗散功率晶体管主要参数晶体管的应用电路常见类型共射放大电路、共基放大电路、共集放大电路等。
工作原理晶体管放大电路利用晶体管的放大效应，将输入信号放大后输出。
通过选择合适的电路参数，可以实现电压放大、电流放大或功率放大。
应用领域音频放大、射频放大、信号驱动等。
工作原理01常见类型02应用领域03常见类型应用领域晶体管的选型与检测工作电压和电流频率特性增益和功率封装和散热01020304晶体管的选型原则外观检查万用表检测功能性测试030201晶体管检测方法与步骤晶体管常见故障排除开路故障短路故障参数异常热稳定性问题晶体管的实际应用与未来发展放大器电路通过晶体管的导通与截止特性，可实现基本的逻辑门功能，如AND、OR、NOT门等，进而构建复杂的数字电路。
数字逻辑门电源管理晶体管在电子领域的应用实例体积小巧功耗低速度快晶体管与其他元器件的比较优势未来发展趋势与新技术应用展望碳化硅晶体管柔性晶体管集成电路中的晶体管微缩感谢观看。
24C0224C04中文资料
概述
CAT24WC01/02/04/08/16 是 一 个 1K/2K/4K/8K/16K 位 串 行 CMOS E2PROM
128/256/512/1024/2048 个 8 位字节 CATALYST 公司的先进 CMOS 技术实质上减少了器件的功耗 CAT24WC01 有一个 8 字节页写缓冲器 CAT24WC02/04/08/16 有一个 16 字节页写缓冲器 该器件通过 I2C 总线接口进行操作 有一个专门的写保护功能
目 录
1 CSI24WC0 1/02/04/08/16 ……………………………….2-10 2 CSI24WC32/64…………………………………………...11-18 3 CSI24WC128. ……………………………..…………….19-26 4 CSI24WC256. ………………………….….…………….27-34
6
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1 个 CAT24WC16 可单独被系统寻址 从器件 8 位地址的最低位 作为读写控制位 进行读操作 0 表示对从器件进行写操作
1 表示对从器件
图2
写周期时序
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图3 起始/停止时序
. w w
s u mc
n c . y
器件寻址
主器件通过发送一个起始信号启动发送过程 然后发送它所要寻址的从器件的地址 8 位从器件地 址的高 4 位固定为 1010 见图 5 接下来的 3 位 A2 A1 A0 为器件的地址位 用来定义哪个器件 以及器件的哪个部分被主器件访问 上述 8 个 CAT24WC01/02 4 个 CAT24WC04 2 个 CAT24WC08
常用晶体管三极管资料大全 (2)精品文档16页
*
NMOS场效应
IRFP054
60V
65A
180W
*
*
NMOS场效应
IRFI744
400V
4A
32W
*
*
NMOS场效应
IRFI730
400V
4A
32W
*
*
NMOS场效应
IRFD9120
100V
1A
1W
*
*
NMOS场效应
IRFD123
80V
1.1A
1W
*
*
NMOS场效应
IRFD120
100V
1.3A
40W
*
*
NPN
2SC4231
800V
2A
30W
*
*
NPN
2SC4119
1500V
15A
250W
*
*
NPN
2SC4111
1500V
10A
250W
*
*
NPN
2SC4106
500V
7A
50W
*
20MHZ
NPN
晶体管型号
反压Vbe0
电流Icm
功率Pcm
放大系数
特征频率
管子类型
2SC4059
600V
15A
130W
*
400MHZ
NPN
2SC3907
180V
12A
130W
*
30MHZ
NPN
2SC3893
1400V
8A
50W
*
8MHZ
NPN
2SC3886
1400V
TU24C04资料
CMOS I²C 2-WIRE BUS4K ELECTRICALLY ERASABLE PROGRAMMABLE ROM512 X 8 BIT EEPROM24C04PRODUCT INTRODUCTIONPIN DESCRIPTIONDESCRIPTION :The Turbo IC 24C04 is a serial 4K EEPROM fabricated with T urbo’s proprietary, high reliability, high performance CMOS technology. It’s 4K of memory is organized as 512 x 8 bits.The memory is configured as 32 pages with each page con-taining 16 bytes. This device offers significant advantages in low power applications.The Turbo IC 24C04 uses the I²C addressing protocol and 2-wire serial interface which includes a bidirectional serial data bus synchronized by a clock. It offers a flexible byte write and a faster 16-byte page write.The T urbo IC 24C04 is assembled in either a 8-pin PDIP or 8-pin SOIC package. Pin #1 is not connected (NC). Pin #2is the A1 device address input for the 24C04. Pin #3 is the A2 device address input for the 24C04, such that a total of four 24C04 devices can be connected on a single bus. Pin #4 is the ground (Vss). Pin #5 is the serial data (SDA) pin used for bidirectional transfer of data. Pin #6 is the serial clock (SCL) input pin. Pin #7 is the write protect (WP) pin used to protect hardware data. Pin #8 is the power supply (Vcc) pin.All data is serially transmitted in bytes (8 bits) on the SDA bus. To access the Turbo IC 24C04 (slave) for a read or write operation, the controller (master) issues a start condi-tion by pulling SDA from high to low while SCL is high. The master then issues the device address byte which consists of 1010 (A2) (A1) (B8) (R/W). The most significant bits (1010)are a device type code signifying an EEPROM device. A1and A2 are the device address select bits which has to match the A1 and A2 pin inputs on the 24C04 device. The B[8] bit is the most significant bit of the memory address. The read/write bit determines whether to do a read or write operation.After each byte is transmitted, the receiver has to provide an acknowledge by pulling the SDA bus low on the ninth clock cycle. The acknowledge is a handshake signal to the transmitter indicating a successful data transmission.FEATURES :• Power Supply VoltageSingle Vcc for Read and Programming (Vcc = 2.7 V to 5.5 V)• Low Power (Isb = 2µa @ 5.5 V)• I²C Bus, 2-Wire Serial Interface• Support Byte Write and Page Write (16 Bytes)• Automatic Page write Operation (maximum 10 ms)Internal Control TimerInternal Data Latches for 16 Bytes• High Reliability CMOS Technology with EEPROM CellEndurance : 1,000,000 Cycles Data Retention : 100 YearsSERIAL CLOCK (SCL)The SCL input synchronizes the data on the SDA bus. It is used in conjunction with SDA to define the start and stop conditions. It is also used in conjunction with SDA to transfer data to and from the Turbo IC 24C04.SERIAL DATA (SDA)SDA is a bidirectional pin used to transfer data in and out of the Turbo IC 24C04. The pin is an open-drain output. A pullup resistor must be con-nected from SDA to Vcc.PIN DESCRIPTIONDEVICE ADDRESS (A1 & A2)A1 and A2 are device address inputs that en-ables a total of four 24C04 devices to connect on a single bus. When the address input pin is left unconnected, it is interpreted as zero.WRITE PROTECT (WP)When the write protect input is connected to Vcc,the entire memory array is protected against write operations. For normal write operations, the write protect pin should be grounded. When the pin is left unconnected, WP is interpreted as zero.12345678NC A1A2GNDVCC WP SCL SDA8 pin PDIP12345678NC A1A2GNDVCC WP SCL SDA8 pin SOIC24C04PRODUCT INTRODUCTIONNote: The write cycle time t WC is the time from a valid stop condition of a write sequence to the end of the internal clear / write cycle.DESCRIPTION (Continued):For a write operation, the master issues a start condition, a device address byte, a memory address byte, and then up to 16 data bytes. The Turbo IC 24C04 acknowledges after each byte transmission. To terminate the transmission, the master issues a stop condition by pulling SDA from low to high while SCL is high.For a read operation, the master issues a start condition and a device address byte. The Turbo IC 24C04 acknowledges,and then transmits a data byte, which is accessed from the EEPROM memory. The master acknowledges, indicating that it requires more data bytes. The Turbo IC 24C04 transmits more data bytes, with the memory address counter auto-matically incrementing for each data byte, until the master does not acknowledge, indicating that it is terminating the transmission. The master then issues a stop condition.DEVICE OPERATION:BIDIRECTIONAL BUS PROTOCOL:The Turbo IC 24C04 follows the I²C bus protocol. The proto-col defines any device that sends data onto the SDA bus as a transmitter, and the receiving device as a receiver. The device controlling the transfer is the master and the device being controlled is the slave. The master always initiates the data transfers, and provides the clock for both transmit and receive operations. The Turbo IC 24C04 acts as a slave de-vice in all applications. Either the master or the slave can take control of the SDA bus, depending on the requirement of the protocol.START/STOP CONDITION AND DATA TRANSITIONS:While SCL clock is high, a high to low transition on the SDA bus is recognized as a START condition which precedes any read or write operation. While SCL clock is high, a low to high transition on the SDA bus is recognized as a STOP con-dition which terminates the communication and places the Turbo IC 24C04 into standby mode. All other data transitions on the SDA bus must occur while SCL clock is low to ensure proper operation.ACKNOWLEDGE:All data is serially transmitted in bytes (8 bits) on the SDA bus. The acknowledge protocol is used as a handshake sig-nal to indicate successful transmission of a byte of data. The bus transmitter, either the master or the slave (Turbo IC 24C04), releases the bus after sending a byte of data on the SDA bus. The receiver pulls the SDA bus low during the ninth clock cycle to acknowledge the successful transmission of a byte of data. If the SDA is not pulled low during the ninth clock cycle, the Turbo IC 24C04 terminates the data trans-mission and goes into standby mode.For the write operation, the Turbo IC 24C04 acknowledges after the device address byte, acknowledges after the memory address byte, and acknowledges after each subsequent data byte.For the read operation, the Turbo IC 24C04 acknowledges after the device address byte. Then the T urbo IC 24C04 trans-mits each subsequent data byte, and the master acknowl-edges after each data byte transfer, indicating that it requires more data bytes. The Turbo IC 24C04 monitors the SDA bus for the acknowledge. T o terminate the transmission, the mas-ter does not acknowledge, and then sends a stop condition.Write Cycle TimingSCLSDAWORD n8th BIT ACKSTOP CONDITION START CONDITIONt WC24C04PRODUCT INTRODUCTION Data ValidStart and Stop Definition Output Acknowledge SDASCLDATA STABLE DATA STABLEDATACHANGESDASCLSTART STOPSCLDATA INDATA OUTACKNOWLEDGE START24C04PRODUCT INTRODUCTIONDEVICE ADDRESSING:Following the start condition, the master will issue a device address byte consisting of 1010 (A2) (A1) (B8) (R/W) to ac-cess the selected Turbo IC 24C04 for a read or write opera-tion. A1 and A2 are the device address select bits which have to match the A1 and A2 pin inputs on the 24C04 device. The B[8] bit is the most significant bit of the memory address. The (R/W) bit is a high (1) for read and low (0) for write. DATA INPUT DURING WRITE OPERATION:During the write operation, the Turbo IC 24C04 latches the SDA bus signal on the rising edge of the SCL clock.DATA OUTPUT DURING READ OPERATION:During the read operation, the Turbo IC 24C04 serially shifts the data onto the SDA bus on the falling edge of the SCL clock.MEMORY ADDRESSING:The memory address is sent by the master in the form of 2 bytes. Device address A2 and memory address bits B[8], are included in the device address byte. The remaining memory address bits B[7:0] are included in the second byte. The memory address byte can only be sent as part of a write operation.BYTE WRITE OPERATION:The master initiates the byte write operation by issuing a start condition, followed by the device address byte 1010 (A2) (A1) (B8) 0, followed by the memory address byte, fol-lowed by one data byte, followed by an acknowledge, then a stop condition. After each byte transfer, the Turbo IC 24C04 acknowledges the successful data transmission by pulling the SDA bus low. The stop condition starts the internal EEPROM write cycle, and all inputs are disabled until the completion of the write cycle.PAGE WRITE OPERATION:The master initiates the page write operation by issuing a start condition, followed by the device address byte 1010 (A2) (A1) (B8) 0, followed by the memory address byte, fol-lowed by up to 16 data bytes, followed by an acknowledge, then a stop condition. After each byte transfer, the Turbo IC 24C04 acknowledges the successful data transmission by pulling SDA low. After each data byte transfer, the memory address counter is automatically incremented by one. The stop condition starts the internal EEPROM write cycle only if the stop condition occurs in the clock cycle immediately fol-lowing the acknowledge (10th clock cycle). All inputs are dis-abled until the completion of the write cycle.POLLING ACKNOWLEDGE:During the internal write cycle of a write operation in the T urbo IC 24C04, the completion of the write cycle can be detected by polling acknowledge. The master starts acknowledge poll-ing by issuing a start condition, then followed by the device address byte 1010 (A2) (A1) (B8) 0. If the internal write cycle is finished, the Turbo IC 24C04 acknowledges by pulling the SDA bus low. If the internal write cycle is still ongoing, the Turbo IC 24C04 does not acknowledge because it’s inputs are disabled. Therefore, the device will not respond to any command. By using polling acknowledge, the system delay for write operations can be reduced. Otherwise, the system needs to wait for the maximum internal write cycle time, tWC, given in the spec.POWER ON RESET:The Turbo IC 24C04 has a Power On Reset circuit (POR) to prevent data corruption and accidental write operations dur-ing power up. On power up, the internal reset signal is on and the Turbo IC 24C04 will not respond to any command until the VCC voltage has reached the POR threshold value.24C04PRODUCT INTRODUCTIONDevice AddressByte WriteSDA LINEDEVICES T O A C KA C KM S BL S B R /W A C KS T A R TW R I T EPage WriteSDA LINEDEVICES T O AC KA C KM S BL S B R /W A C KS T A R TW R I TE C K24C04Random ReadCURRENT ADDRESS READ:The internal memory address counter of the Turbo IC 24C04contains the last memory address accessed during the pre-vious read or write operation, incremented by one. To start the current address read operation, the master issues a start condition, followed by the device address byte 1010 (A2) (A1)(B8) 1. The Turbo IC 24C04 responds with an acknowledge by pulling the SDA bus low, and then serially shifts out the data byte accessed from memory at the location correspond-ing to the memory address counter. The master does not acknowledge, then sends a stop condition to terminate the read operation. It is noted that the memory address counter is incremented by one after the data byte is shifted out.RANDOM ADDRESS READ:The master starts with a dummy write operation (one with no data bytes) to load the internal memory address counter by first issuing a start condition, followed by the device address byte 1010 (A2) (A1) (B8) 0, followed by the memory address bytes. Following the acknowledge from the Turbo IC 24C04,the master starts the current read operation by issuing a start condition, followed by the device address byte 1010 (A2) (A1)(B8) 1. The Turbo IC 24C04 responds withan acknowledge by pulling the SDA bus low, and then seri-ally shifts out the data byte accessed from memory at the location corresponding to the memory address counter. The master does not acknowledge, then sends a stop condition to terminate the read operation. It is noted that the memory address counter is incremented by one after the data byte is shifted out.SEQUENTIAL READ:The sequential read is initiated by either a current address read or random address read. After the T urbo IC 24C04 seri-ally shifts out the first data byte, the master acknowledges by pulling the SDA bus low, indicating that it requires addi-tional data bytes. After the data byte is shifted out, the T urbo IC 24C04 increments the memory address counter by one.Then the Turbo IC 24C04 shifts out the next data byte. The sequential reads continues for as long as the master keeps acknowledging. When the memory address counter is at the last memory location, the counter will ‘roll-over’ when incremented by one to the first location in memory (address zero). The master terminates the sequential read operation by not acknowledging, then sends a stop condition.Current Address ReadSDA LINEDEVICE S T O PN O A C KM S BL S B R /W A C KS T A R TR E A DDATAPRODUCT INTRODUCTIONSDA LINEDEVICE S T O O A C KC KA C KM S BL S B R /W A C KS T A R TW R I T ER E A DEVICE WORD ADDRESS NDUMMY WRITE24C04Sequential ReadSDA LINEDEVICES T O A C KA C KA C KM S BL S B R /W A C KS T A R TR E A O A C KD.C. CHARACTERISTICSSymbol Parameter Condition Min Max Units I cc1Active Vcc Current READ at 100 KHZ 1.0MA I cc2Active Vcc Current WRITE at 100 KHZ 3.0MA I sb1Standby Current Vcc = 4.5 v 2.0uA Vcc = 5.5 v 2.0uA I il Input Leakage Current Vin=Vcc Max3uA I ol Output Leakage Current 3uA V il Input Low Voltage -1.00.8V V ih Input High Voltage Vccx0.7Vcc+0.5V V ol1Output LowVcc=4.5v Iol=2.1 mA0.4V* “Absolute Maximum Ratings” may cause permanent damage to the de-vice. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sec-tion of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.TEMPERATURE Storage:-65° C to 150° C Under Bias:-55° C to 125° CALL INPUT OR OUTPUT VOLTAGES with respect to Vss +6 V to -0.3 VRECOMMENDED OPERATING CONDITIONS Temperature Range :Commercial:0° C to 70° C Industrial:-40° C to 85° C Military:-55° C to 125° CVcc Supply Voltage : 2.7 to 5.5 VoltsEndurance:100,000 Cycles/Byte (T ypical)Data Retention :100 Y earsPRODUCT INTRODUCTIONABSOLUTE MAXIMUM RATINGS24C04TURBO IC PRODUCTS AND DOCUMENTS1.All documents are subject to change without notice. Please contact Turbo IC for the latest revision of documents.2.Turbo IC does not assume any responsibility for any damage to the user that may result from accidents or operation under abnormal conditions.3.Turbo IC does not assume any responsibility for the use of any circuitry other than what embodied in a Turbo IC product. No other circuits, patents, licenses are implied.4.Turbo IC products are not authorized for use in life support systems or other critical systems where component failure may endanger life. System designers should design with error detection and correction, redundancy and back-up features.Bus TimingtSU.STAtHD.STAt F tLOWt HIGHtLOWt HD.DATt SU.DATt RtSU.STOt BUFt DHt AASCLSDA INSDA OUTPart Numbers & Order Information TU24C04BS3I512 X 8Serial EEPROMPRODUCT INTRODUCTIONA.C. CHARACTERISTICSSymbol Parameter 2.7 volt5.5 volt MinMax MinMax Units SCL SCL Clock Frequency100400kHZ T Noise Suppression Time (1)10050ns t LOW Clock Low Period 4.7 1.2us t HIGH Clock High Period4.00.6us t AA SCL Low to SDA Data Out 0.1 4.50.10.9us t BUF Bus Free to New Start (1) 4.7 1.2us t HD.STA Start Hold Time 4.00.6us t SU.STA Start Set-up Time 4.70.6us t HD.DAT Data-in Hold Time 00us t SU.DAT Data-in Set-up Time200100ns t R SCL and SDA Rise Time (1) 1.00.3us t FSCL and SDA Fall Time (1)300300ns t SU.STO Stop Set-up Time 4.70.6us t DH Data-out Hold Time 10050ns t WCWrite Cycle Time1010msNote: 1 This parameter is characterized and not 100% tested.Temperature -Commercial I -IndustrialPackageP -PDIP S -SOICVoltage3 - 2.7V to 5.5V- 4.5V to 5.5 V2nd generation。
24晶体三极管04074-文档资料
截止 状态
Vce最大，Ic最小约为0， 则功耗较小
9V
a
Ib 基极电流(uA)
b
VO
截 止 区 放 大 区 饱 和 区
放大 状态
Vce较大，Ic也较大 则功耗最大
Ic Ib
0.2V 0V 1V 2V 3V 4V 5V
饱和 状态
Vce最小约为0.2V~0.3V， Ic最大，则功耗也较小
基极回路源电压Vb
+ U1
U2
RC电路输出 电压U1 三极管输出 电压U2 继电器状态
三极管中电流不足以 初始状态（上电瞬间） 维持继电器吸合
吸合
释放
t
简易时间继电器原理
② 按下按键
+Vcc
+ 电容放电时，限 制放电电流不至 过大而损坏电容
U1
电容两端压差降为零，三极管Q的输入端为高 电平(+Vcc)，三极管导通，继电器吸合。
简易时间继电器原理
RC电路
+Vcc
继电器驱动电路
① 电路上电
初始状态（上电瞬间）：电容中没有存储电荷， 两端压差为零，三极管Q的输入端为高电平(+Vcc)， 三极管导通。 随着电容中充入的电荷量越来越多，两端的压 差也越来越大，三极管输入端电压也将越来越低， 当三极管中电流不足以维持继电器吸合时，继电 器释放。
分 类
电磁式继电器
衔铁 触点
公共端COM
电气符号
输出
常闭端NC
弹簧
I
支架 电磁线圈
开关受控于 电感线圈
常开端NO
输入
通常，控制输入线圈的是低电压 mA级的信号，而输出触点与输入之间 当输入端1和2之间通过足够大的直流电时，电磁线圈产生磁力可 工 吸引衔铁，在公共触点4离开触点3而与触点5短接在一起； 作 是绝缘的，并且触点能够承受高电压A级的强电信号，输出功率与输入功率 原 当撤销输入端电流时，电磁线圈失去磁性，在弹簧的作用下触点4 理 之比可达千倍以上。 弹回触点3而与触点5断开。
BR24C04中文资料
•Features• Low power CMOS technology.• 2.7V to 5.5V Operation.• Two wire serial interface I2C bus™compatible.• Low power dissipation– 0.2mA (typ.) active current: 5V– 1.0µA (typ.) standby current: 5V• Automatic Word Address Incrementing– Sequential register read• Automatic erase-before-write.• Page write buffer for up to 4 bytes: BR24C01A / AFup to 4 bytes: BR24C02 / Fup to 16 bytes: BR24C04 / F • DATA security–Inhibit to write at low V CC.• Noise filters at SCL and SDA pins.• 8-pin DIP / 8-pin SOP packages.• 100,000 ERASE / WRITE cycles.• 10 years Data Retention.•Pin assignments•Pin descriptionsA0A1A2GND4321TESTSCLSDA5678BR24C01ABR24C01AFV CCBR24C02BR24C02FA0, A1, A2SCLSDATESTV CCGNDPin name FunctionSlave address setting pinSerial data clockSerial data input / outputGND connectionPower supplyGround•Pin assignmentsA0A1A2GND4321VccTESTSCLSDA5678BR24C04BR24C04F(NC)•Pin descriptionsA0SCLSDATESTGNDA1, A2V CCPin name FunctionN.C.Slave address setting pinSerial data clockSerial data input / outputGND connectionPower supplyGround•Over viewThe BR24C01A / AF, BR24C02 / F, and BR24C04 / F are 2-wire serial EEPROMs which are electrically programmable. The configurations are as follows:BR24C01A / AF: 128× 8 bit 1K serial EEPROMBR24C02 / F: 256× 8 bit 2K serial EEPROMBR24C04 / F: 512× 8 bit 4K serial EEPROM•Block diagram•Absolute maximum ratings (Ta = 25°C)ParameterSymbol Limits Unit – 0.3 ~ + 6.5V mW – 65 ~ + 125°C °C —V– 40 ~ + 85V CC – 0.3 ~ V CC + 0.3Pd Tstg Topr DIP8 pin SOP8 pin500∗1350∗2Applied voltage Power dissipation Storage temperature Operating temperature Input voltage∗1 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C.∗2 Reduced by 3.5mW for each increase in Ta of 1°C over 25°C.•Recommended operating conditions (Ta = 25°C)ParameterSymbol Limits Unit V V V INVV CC 0 ~ V CC2.7 ~ 5.5 (WRITE)2.7 ~ 5.5 (READ)Power supply voltage Input voltage•Electrical characteristics DC characteristics (unless otherwise noted, Ta = - 40 to + 85°C, VCC = 2.7 to 5.5V)ParameterSymbol Min.Typ.Max.Unit ConditionsV IH ——V V IL ——0.3V CC V V OL ——0.4V I LI – 10—10µA V IN = 0V ∼ V CC I LO – 10—10µA I CC —— 1.0mA I SB —— 2.0µA f SCL—————100kHZ0.7V CCI OL = 3.0mA (SDA)V OUT = 0V ∼ V CCV CC = 5.5V, f SCL = 100kHz V CC = 5.5V, SDA · SCL = V CCInput high level voltage Input low level voltage Output low level voltage Input leakage current Output leakage current Operating current dissipation Standby current SCL frequencyOperating timing characteristics (unless otherwise noted, Ta = – 40 to + 85°C, V CC = 2.7 to 5.5V)ParameterSymbol Min.Typ.Max.Unit t HIGH 4.0——µs t LOW 4.7——µs t R —— 1.0µs t F ——0.3µs t HD : STA 4.0——µs t SU : STA 4.7——µs t HD : DAT 0——ns t SU : DAT 250——ns t PD 0.3— 3.5µs t DH 0.3——µs t SU : STO 4.7——µs t BUF 4.7——µs t WR1——10ms t WR2——25ms tI——0.1µsData clock HIGH time Data clock LOW time SDA / SCL rise time SDA / SCL fall time Start condition hold time Start condition setup time Input data hold time Input data setup time Output data delay time Output data hold time Stop condition setup timeBus open time before start of transfer Internal write cycle time ∗1∗2Noise erase valid time (SCL / SDA pins)∗1 V CC = 4.5 to 5.5V ∗2 V CC = 2.7 to 4.5V᭺ Not designed for radiation resistance.•Timing chartsSDA SDA SCLSCLSDA(input)(output)• Data is read on the rising edge of SCL.• Data is output in synchronization with the falling edge of SCL.Fig.1 Synchronized data input / output timingSDASCLFig.2 Write cycle timing•Circuit operation (1) Start condition (recognition of start bit)Before executing any command, when SCL is HIGH, a start condition (start bit) is required to cause SDA to fall from HIGH to LOW. This IC is designed to constantly detect whether there is a start condition (start bit) for the SDA and SCL line, and no commands will be exe-cuted unless this condition is satisfied.(See Figure 1 for the synchronized data input / output timing.)(2) Stop condition (recognition of stop bit)To stop any command, a stop condition (stop bit) is required. A stop condition is achieved when SDA goes from LOW to HIGH while SCL is HIGH. This enables commands to be completed.(See Figure 1 for the synchronized data input / outputlows.R / W set to 0 ··· Write(Random read word address setting is also 0)R / W set to 1 ··· Read᭛With the BR24C04 / FMake sure the slave address is output from the master in continuation with the start condition.The upper four bits of the slave address are used to determine the device type. The device code for this IC is fixed at “1010”.The next two bits of the slave address (A2, A1 ···device address) are used to select the device. This IC can address up to four devices on the same bus. The next bit of the slave address (PS ··· Page Select) is used to select the page. As shown below, it can write to or read from any of the 256 words in the two pages in memory.PS set to 0 ··· Page 1 (000 to 0FF)PS set to 1 ··· Page 2 (100 to 1FF)A2A1A01010R / W(5) ACK signalThe acknowledge signal (ACK signal) is determined by software and is used to indicate whether or not a data transfer is proceeding normally. The transmitting device, whether the master or slave, opens the bus after an 8-bit data output (µ-COM when a write or read command of the slave address input; this IC when reading data).For the receiving device during the ninth clock cycle,SDA is set to LOW and an acknowledge signal (ACK signal) is sent to indicate that it received the 8-bit data (this IC when a write command or a read command of the slave address input, µ-COM when a read com-mand data output).This IC outputs a LOW acknowledge signal (ACK sig-nal) after recognizing the start condition and slave address (8 bits).When data is being written to this IC, a LOW acknowl-edge signal (ACK signal) is output after the receipt of each eight bits of data (word address and write data). When data is being read from the IC, eight bits of data (read data) are output and the IC waits for a returned LOW acknowledge signal (ACK signal). When an acknowledge signal (ACK signal) is detected and a stop condition is not sent from the master (µ-COM)side, the IC continues to output data. If an acknowl-edge signal (ACK signal) is not detected, the IC inter-rupts the data transfer and ceases reading operations after recognizing the stop condition (stop bit). The IC then enters the waiting or standby state.(See Figure 3 for acknowledge signal (ACK signal)response.)SCL SDASDAStart condition (start bit)(from µ(µFig.3 Acknowledge (ACK signal) response(during write and read slave address input)(6) Byte write• Data is written to the address designated by the word address (n address).• After eight bits of data are input, the data is written to the memory cell by issuing the stop bit.SCLSDAFig.4 Byte write cycle (BR24C01A / AF)SCLSDAFig.5 Byte write cycle (BR24C02 / F)Fig.6 Byte write cycle (BR24C04 / F)(7) Page write cycleBR24C01A / AF• A 4-byte write is possible using this command.• The page write command arbitrarily sets the upper five bits (WA6 to WA2) of the word address. The lower two bits (WA1 and WA0) can write up to four bytes of data with the address being incremented internally.• A 4-byte write is possible using this command.• The page write command arbitrarily sets the upper six bits (WA7 to WA2) of the word address. The lower two bits (WA1 and WA0) can write up to four bytes of data with the address being incremented internally.BR24C04 / F• A 16-byte write is possible using this command.• The page write command arbitrarily sets the upper four bits (WA7 to WA4) of the word address. The lower four bits (WA3 to WA0) can write up to 16 bytes of data with the address being incremented internally.(8) Current read•This IC increments the address by one position by using the internal circuit address count. It records the final word address (n address) of the executed write - read command.•This command reads the data of the next word address (n + 1 address) of the final write word address after the execution of the previous command.•When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next word address data can be read. [All words all read enabled](See Figures 16 to 18 for the sequential read cycles.)•This command is ended by inputting HIGH to the ACK signal after D0 and raising the SDA signal (stop condition)by setting SCL to HIGH.SCLSDAFig.10 Current read cycle (BR24C01A / AF)SCLSDAFig.11 Current read cycle (BR24C02 / F)Fig.12 Current read cycle (BR24C04 / F)(9) Random readFig.13 Random read cycle (BR24C01A / AF)Start condition(input)Fig.14 Random read cycle (BR24C02 / F)Fig.15 Random read cycle (BR24C04 / F)•This command can read the designated word address data.•When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next word address data can be read. [All words all read enabled](See Figures 16 to 18 for the sequential read cycles.)•This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop condition) by raising SCL to HIGH.1112(10) Sequential read•When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next word address data can be read. [All words can be read]•This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop condition) using the SCL signal HIGH.•Sequential reading can also be done with a random read.Stop conditionFig.16 Sequential read cycle (BR24C01A / AF)(Example: For a current read)Start conditionStop conditionFig.17 Sequential read cycle (BR24C02 / F)(Example: For a current read)SCLSDAStart conditionStop conditionFig.18 Sequential read cycle (BR24C04 / F)(Example: For a current read)13•Operation notes (1) During power riseDuring power rise, the V CC may rise passing through the low voltage domain in which the IC internal circuit does not work. For this reason, there is a risk of misoperation when the power rises without full IC internal reset.To prevent this, pay attention to the following points during a power rise.1) Set SCL = SDA = “HIGH”2) Raise the power so as to activate the Power On Reset (P. O. R) circuit.Follow the steps below as to operate the P. O. R. circuit properly.1) Set the power rise time (tR) to within 10ms.2) Set the OFF domain for once power has been cut to 100ms minimum.The SDA terminal is an open drain output. Consequently, it requires an external pull-up resistance. The appropriate pull-up resistace value is selected from the IC V OL -I OL features, which have been appended as measuring data, as well as V IL and I LI and other personal icons that control the IC in question.Recommended values 2.0k to 10k Ω0.2201816141210864200.1Ta = 25Note: All memory array data are set to “FF” status at time of shipping.0.30.40.5Ta = 85Ta = 25Ta = 85Ta = – 40Ta = – 400.220181614121086420.10.30.40.5CC = 4.5V V CC = 5.5V CC = 5.0V V CC = 4.5VV CC = 5.5VV CC = 2.7VV CC = 3.3V V CC = 3.0V V CC = 2.7VV CC = 3.3VOUTPUT VOLTAGE: V OL (V)V OL —I OL features (Note: Typ.)V OL —I OL features (Note: Typ.)O U T P U T C U R R E N T : I O L (m A )O U T P U T C U R R E N T : I O L (m A )External dimensions (Units: mm)。
24c04
24C04IntroductionThe 24C04 is a popular EEPROM (Electrically Erasable Programmable Read-Only Memory) which provides 4 kilobits (512 bytes) of non-volatile storage. It uses the I2C (Inter-Integrated Circuit) protocol for communication with the microcontroller or any other digital device. The 24C04 is widely used in various applications, including consumer electronics, automotive, and industrial systems.FeaturesThe key features of the 24C04 EEPROM include:1. 4 kilobits of storage capacity, organized into 512 bytes.2.I2C interface, supporting standard and fast-mode (up to 400 kHz)communication.3.Single supply voltage range of 1.7V to 5.5V, making it compatible witha wide range of microcontrollers and devices.4.Low power consumption, with an active current of only 3mA andstandby current of 1μA.5.Extended temperature range, from -40°C to 85°C, allowing foroperation in harsh environments.6.Built-in write protection to prevent accidental modification of data.7.High reliability and endurance, with a guaranteed minimum of 1million write cycles and 100 years of data retention.Pin ConfigurationThe 24C04 is available in different package options, such as the 8-pin DIP (Dual Inline Package) or SOIC (Small Outline Integrated Circuit) packages. The pin configuration for the 24C04 in the 8-pin DIP package is as follows:_______________| U |VCC -| 1 8 |-SDA -| 2 7 |-SCL -| 3 6 |-Write-| 4 5 |-GND -|______________|Where:•VCC: The supply voltage, typically in the range of 1.7V to 5.5V.•SDA: The data line for I2C communication.•SCL: The clock line for I2C communication.•Write: The write protection input, which can be used to control the write operations.•GND: The ground reference.I2C Communication ProtocolThe 24C04 uses the I2C protocol for communication with the microcontroller or any other digital device. The I2C protocol consists of two lines: SDA (data) and SCL (clock). Data transmission and reception occur over the SDA line while the SCL line provides the clock signal for synchronization.The communication protocol involves the following steps:1.Start condition: The master (microcontroller) initiates communicationby sending a start condition in which both SDA and SCL lines are pulled low.2.Device address: The master sends the 7-bit device address followedby the read/write bit. The device address is unique for each I2C device.3.Acknowledge: The device acknowledges the receipt of the deviceaddress by pulling the SDA line low.4.Memory address: The master sends the memory address bytes tospecify the location from where data will be read or written.5.Acknowledge: The device acknowledges the receipt of the memoryaddress by pulling the SDA line low.6.Data transmission/reception: The master sends or receives the datafrom/to the specified memory address.7.Acknowledge: After each data byte transfer, the receiver must pull theSDA line low to acknowledge the receipt of the data.8.Stop condition: The master terminates communication by sending astop condition in which both SDA and SCL lines are pulled high.Programming the 24C04To read from or write to the 24C04 EEPROM, the following steps are typically followed:1.Initialize the I2C master and configure the communication speed.2.Send the start condition.3.Send the device address and specify whether it is a read or writeoperation.4.Wait for the device to acknowledge.5.Send the memory address from where data needs to be read/written.6.Wait for the acknowledge.7.If it is a write operation, send the data to be written.–If it is a read operation, receive the data from the specified memory address.–Repeat these steps for each byte of data.8.Send the stop condition to terminate communication.It is important to note that the 24C04 EEPROM has a limited endurance (typically 1 million write cycles) and must be handled carefully to ensure data integrity and longevity.ConclusionThe 24C04 EEPROM is a versatile, reliable, and low-power non-volatile memory device that finds extensive use in various applications. Its compact size, ease of integration, and I2C interface make it an ideal choice for storing critical configuration data and other small chunks of information. By following the I2C communication protocol and understanding the pin configuration, developers can easily incorporate the 24C04 into their electronic designs and leverage its benefits for efficient and reliable data storage.。
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PAGE WRITE (up to 8 BYTES)
BYTE, RANDOM and SEQUENTIAL READ MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω). 3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).
DESCRIPTION (cont’d)
VCC
2 E1-E2
PRE SCL MODE/WC*
ST24x04 ST25x04
SDA
VSS
AI00851E
Note: WC signal is only available for ST24/25W04 products.
February 1999
1/16
ST24/25C04, ST24/25W04
SINGLE SUPPLY VOLTAGE:
– 3V to 5.5V for S Nhomakorabea24x04 versions
– 2.5V to 5.5V for ST25x04 versions
HARDWARE WRITE CONTROL VERSIONS: ST24W04 and ST25W04
PROGRAMMABLE WRITE PROTECTION TWO WIRE SERIAL INTERFACE, FULLY I2C BUS COMPATIBLE
–65 to 150
°C
TLEAD Lead Temperature, Soldering
(SO8 package)
40 sec
(PSDIP8 package) 10 sec
215 260
°C
VIO
Input or Output Voltages
–0.6 to 6.5
V
VCC VESD
Supply Voltage Electrostatic Discharge Voltage (Human Body model) (2) Electrostatic Discharge Voltage (Machine model) (3)
ST24C04, ST25C04 ST24W04, ST25W04
4 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection
1 MILLION ERASE/WRITE CYCLES with 40 YEARS DATA RETENTION
ENHANCED ESD/LATCH UP PERFORMANCES
8
1
PSDIP8 (B) 0.25mm Frame
8
1
SO8 (M) 150mil Width
Figure 1. Logic Diagram
DESCRIPTION
This specification covers a range of 4 Kbits I2C bus EEPROM products, the ST24/25C04 and the ST24/25W04. In the text, products are referred to as ST24/25x04, where "x" is: "C" for Standard version and "W" for hardware Write Control version.
1
8
2
7
3
6
4
5
AI01107E
VCC MODE/WC SCL SDA
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
TA
Ambient Operating Temperature
–40 to 125
°C
TSTG Storage Temperature
–0.3 to 6.5
V
4000
V
500
V
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Figure 2A. DIP Pin Connections
ST24x04 ST25x04
PRE 1 E1 2
8 VCC 7 MODE/WC
E2 3
6 SCL
VSS 4
5 SDA
AI00852E
Figure 2B. SO Pin Connections
PRE E1 E2
VSS
ST24x04 ST25x04
Table 1. Signal Names
PRE E1-E2 SDA SCL
MODE
WC VCC VSS
Write Protect Enable Chip Enable Inputs Serial Data Address Input/Output Serial Clock Multibyte/Page Write Mode (C version) Write Control (W version) Supply Voltage Ground