Synthesis, Place & Route
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GUI
Optimization
.tlf libraries
Netlist
CADENCE CONFIDENTIAL
Business Statistics
Conventional Synthesis
Cisco 3Com IBM Ericsson Lucent Philips Toshiba
ADI
HP
Fujitsu
CADENCE CONFIDENTIAL
Productive Design Plan with Cadence SP&R
• Verification Cockpit • NC Sim
RTL Development
Logic Synthesis, Datapath, Low Power
Physical Synthesis, Datapath, Low Power
Power Reduction
RTL Synthesis
Physical Synthesis Integrated Datapath, Low Power synthesis Placement, Clock-tree, Global routing,Timing Sign-off STA Closure Closure Static Timing Timing Pass 2 Pass 1 Analysis & Physical Synthesis
NEC
Sun
• Over 500 customers • More than 3000 active licenses worldwide
• Leading ASIC vendor support
AMI, Atmel, Chip Express, IBM, Kawasaki Steel, LSI, NEC, OKI, Toshiba, Faraday Technology, Lucent, Matsushita, VLSI Fujitsu, Mitsubishi,
Timing TimingClosure Closure & STA
• Integrated sign-off STA • Separate STA tool • < 3% Correlation • Multiple iterations • Early predictability • Unpredictable schedule • Integrated solution Timing Closure • SI analysis, repair ... Pass n • Fastest, proven Router • Complete Clock mgmt.
Place & Cross-Talk Power Clock Route Management Distribution Optimization, SignalAvoidance Integrity, P&R, Physical Implementation & Power Management, Clock-tree Physical Implementation &
Wireless, xDSL Graphics
Comde x CES DSLcon
CADENCE CONFIDENTIAL
Design Implementation Plan
RTL Logic Coding
Datapath Coding Mult., FIR filter源自RTL Development
Chip Integration
Chip Integration
Integration, Predictability, Excellent QoR
• Separate point tools • Signal, design integrity • Routing density, speed Time to Market • Clock skew
Logic Synthesis DataPath Synthesis
• Highest synthesis capacity, speed • Insufficient synthesis capacity, speed • Integrated single tool Datapath flow • Separate Datapath flow • Integrated, superior Power optimization • Inadequate power reduction
CADENCE CONFIDENTIAL
Productive Design Plan with Cadence SP&R
RTL Development
Logic Synthesis, Datapath, Low Power
Physical Synthesis, Datapath, Low Power
Ambit BuildGates
Datapath Option
gates, timing constraints, reports
What is it?
A logic synthesis tool Like conventional synthesis, with greater performance and capacity
Services: BG training course Adoption services
CADENCE CONFIDENTIAL
Integrated Chip Synthesis and STA
Block Synthesis
Separate Timing Tool
Ambit BuildGates
RTL synthesis TCL command Library mapping interface Scan test insertion Full-chip Sign-off timing engine
.lib libraries
• TCL - user interface
• SDF,GCF, PDEF • Sun, HP, IBM
LowPower Option RTL, gates, timing constraints, logical library Ambit BuildGates gates, timing constraints, reports
Datapath Option
What is it?
An option to Ambit BuildGates and PKS Enables less power consuming design
CADENCE CONFIDENTIAL
Productive Design Plan with Cadence SP&R
RTL Development
Logic Synthesis, Datapath, Low Power
Physical Synthesis, Datapath, Low Power
CADENCE CONFIDENTIAL
Productive Design Plan with Cadence SP&R
RTLRTL Logic Datapath Coding Coding Coding Mult., FIR filter Unified Control, Datapath
RTL Development RTL Development
Physical Implementation & Chip Integration Concept
• Separate point tools • Signal, design integrity • Routing density, speed Implementation • Clock skew
RTL Synthesis
Static Timing Timing Closure Timing Closure Pass 2 Pass 1 Analysis
...
Timing Closure Pass n
Timing Closure & STA
Place & Route Cross-Talk Power Clock Avoidance Management Distribution
Chip Synthesis Integrated Signoff Timing
Manual Constraints
Reduced Scripting, Iteration
Toshiba
TAEC Endorsement of Ambit BuildGates Static Timing Analysis in ASIC Design Flows
Logic Synthesis DataPath Synthesis Power Reduction
• Insufficient synthesis capacity, speed • Separate Datapath flow • Inadequate power reduction • Separate STA tool • Multiple iterations • Unpredictable schedule
Why is it Better?
Higher performance/capacity Superior QoR
Integrated Static Timing sign-off
Who is the Typical User?
Logic designers using ASIC or COT flows
Ambit BuildGates conventional synthesis
Physical Implementation & Chip Integration
LowPower DataPath
CADENCE CONFIDENTIAL
Low Power Synthesis Option
Quick Reference Card
Why is it Better?
Integrated, single tool solution
Superior power savings
/company/pr/020701_Toshiba.html
CADENCE CONFIDENTIAL
Ambit BuildGates: Comprehensive Synthesis
• Verilog, VHDL, EDIF
RTL Verilog Verilog parser
• Ambit BuildGates • Low Power Synthesis Option • Datapath Synthesis Option • PKS
Physical Implementation & Chip Integration
• Silicon Ensemble PKS • Integration Ensemble
RTL VHDL
VHDL parser
• Integrated, Sign-off timing engine
• Time Budgeting • Graphical UI • Distributed synthesis • AmbitWare • Test Synthesis
OLA/DCL libraries
Synthesis, Place & Route
Ketan Joshi Director of Marketing, SP&R
CADENCE CONFIDENTIAL
Design Concept to Implementation
6M+ Gates 300MHz 0.18u 1248 pins
ASIC or COT
Ambit BuildGates conventional synthesis
Physical Implementation & Chip Integration
CADENCE CONFIDENTIAL
Ambit BuildGates
Quick Reference Card
LowPower Option RTL, gates, timing constraints, logical library
Optimization
.tlf libraries
Netlist
CADENCE CONFIDENTIAL
Business Statistics
Conventional Synthesis
Cisco 3Com IBM Ericsson Lucent Philips Toshiba
ADI
HP
Fujitsu
CADENCE CONFIDENTIAL
Productive Design Plan with Cadence SP&R
• Verification Cockpit • NC Sim
RTL Development
Logic Synthesis, Datapath, Low Power
Physical Synthesis, Datapath, Low Power
Power Reduction
RTL Synthesis
Physical Synthesis Integrated Datapath, Low Power synthesis Placement, Clock-tree, Global routing,Timing Sign-off STA Closure Closure Static Timing Timing Pass 2 Pass 1 Analysis & Physical Synthesis
NEC
Sun
• Over 500 customers • More than 3000 active licenses worldwide
• Leading ASIC vendor support
AMI, Atmel, Chip Express, IBM, Kawasaki Steel, LSI, NEC, OKI, Toshiba, Faraday Technology, Lucent, Matsushita, VLSI Fujitsu, Mitsubishi,
Timing TimingClosure Closure & STA
• Integrated sign-off STA • Separate STA tool • < 3% Correlation • Multiple iterations • Early predictability • Unpredictable schedule • Integrated solution Timing Closure • SI analysis, repair ... Pass n • Fastest, proven Router • Complete Clock mgmt.
Place & Cross-Talk Power Clock Route Management Distribution Optimization, SignalAvoidance Integrity, P&R, Physical Implementation & Power Management, Clock-tree Physical Implementation &
Wireless, xDSL Graphics
Comde x CES DSLcon
CADENCE CONFIDENTIAL
Design Implementation Plan
RTL Logic Coding
Datapath Coding Mult., FIR filter源自RTL Development
Chip Integration
Chip Integration
Integration, Predictability, Excellent QoR
• Separate point tools • Signal, design integrity • Routing density, speed Time to Market • Clock skew
Logic Synthesis DataPath Synthesis
• Highest synthesis capacity, speed • Insufficient synthesis capacity, speed • Integrated single tool Datapath flow • Separate Datapath flow • Integrated, superior Power optimization • Inadequate power reduction
CADENCE CONFIDENTIAL
Productive Design Plan with Cadence SP&R
RTL Development
Logic Synthesis, Datapath, Low Power
Physical Synthesis, Datapath, Low Power
Ambit BuildGates
Datapath Option
gates, timing constraints, reports
What is it?
A logic synthesis tool Like conventional synthesis, with greater performance and capacity
Services: BG training course Adoption services
CADENCE CONFIDENTIAL
Integrated Chip Synthesis and STA
Block Synthesis
Separate Timing Tool
Ambit BuildGates
RTL synthesis TCL command Library mapping interface Scan test insertion Full-chip Sign-off timing engine
.lib libraries
• TCL - user interface
• SDF,GCF, PDEF • Sun, HP, IBM
LowPower Option RTL, gates, timing constraints, logical library Ambit BuildGates gates, timing constraints, reports
Datapath Option
What is it?
An option to Ambit BuildGates and PKS Enables less power consuming design
CADENCE CONFIDENTIAL
Productive Design Plan with Cadence SP&R
RTL Development
Logic Synthesis, Datapath, Low Power
Physical Synthesis, Datapath, Low Power
CADENCE CONFIDENTIAL
Productive Design Plan with Cadence SP&R
RTLRTL Logic Datapath Coding Coding Coding Mult., FIR filter Unified Control, Datapath
RTL Development RTL Development
Physical Implementation & Chip Integration Concept
• Separate point tools • Signal, design integrity • Routing density, speed Implementation • Clock skew
RTL Synthesis
Static Timing Timing Closure Timing Closure Pass 2 Pass 1 Analysis
...
Timing Closure Pass n
Timing Closure & STA
Place & Route Cross-Talk Power Clock Avoidance Management Distribution
Chip Synthesis Integrated Signoff Timing
Manual Constraints
Reduced Scripting, Iteration
Toshiba
TAEC Endorsement of Ambit BuildGates Static Timing Analysis in ASIC Design Flows
Logic Synthesis DataPath Synthesis Power Reduction
• Insufficient synthesis capacity, speed • Separate Datapath flow • Inadequate power reduction • Separate STA tool • Multiple iterations • Unpredictable schedule
Why is it Better?
Higher performance/capacity Superior QoR
Integrated Static Timing sign-off
Who is the Typical User?
Logic designers using ASIC or COT flows
Ambit BuildGates conventional synthesis
Physical Implementation & Chip Integration
LowPower DataPath
CADENCE CONFIDENTIAL
Low Power Synthesis Option
Quick Reference Card
Why is it Better?
Integrated, single tool solution
Superior power savings
/company/pr/020701_Toshiba.html
CADENCE CONFIDENTIAL
Ambit BuildGates: Comprehensive Synthesis
• Verilog, VHDL, EDIF
RTL Verilog Verilog parser
• Ambit BuildGates • Low Power Synthesis Option • Datapath Synthesis Option • PKS
Physical Implementation & Chip Integration
• Silicon Ensemble PKS • Integration Ensemble
RTL VHDL
VHDL parser
• Integrated, Sign-off timing engine
• Time Budgeting • Graphical UI • Distributed synthesis • AmbitWare • Test Synthesis
OLA/DCL libraries
Synthesis, Place & Route
Ketan Joshi Director of Marketing, SP&R
CADENCE CONFIDENTIAL
Design Concept to Implementation
6M+ Gates 300MHz 0.18u 1248 pins
ASIC or COT
Ambit BuildGates conventional synthesis
Physical Implementation & Chip Integration
CADENCE CONFIDENTIAL
Ambit BuildGates
Quick Reference Card
LowPower Option RTL, gates, timing constraints, logical library