专题4 精简8位CPU电路设计

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8位移位寄存器的电路设计与版图实现要点

8位移位寄存器的电路设计与版图实现要点8位移位寄存器的电路设计与版图实现摘要电⼦设计⾃动化，缩写为EDA，主要是以计算机为主要⼯具，⽽Tanner EDA则是⼀种在计算机windows平台上完成集成电路设计的⼀种软件，基本包括S-Edit，T-Spice，W-Edit，L-Edit与LVS等⼦软件，其S-Edit以及L-Edit为常⽤软件，前者主要实现电路设计，后者主要针对的是已知电路的版图绘制，⽽T-Spice主要可实现电路图及版图的仿真，可以⽤Tanner EDA实现电路的设计布局以及版图实现等⼀系列完整过程。

本⽂⽤Tanner EDA⼯具主要设计的是8位移位寄存器，移位寄存器主要是⽤来实现数据的并⾏和串⾏之间的转换以及对数据进⾏运算或专业处理的⼯具，主要结构构成是触发器，触发器是具有储存功能的，可以⽤来储存多进制代码，⼀般N 位寄存器就是由N个触发器构成，移位寄存器⼯作原理主要是数据在其脉冲的作⽤下实现左移或者右移的效果，输⼊输出的⽅式表现为串⾏及并⾏⾃由组合，本设计就是在Tanner EDA的软件平台上进⾏对8位移位寄存器的电路设计仿真，再根据电路图在专门的L-Edit 平台上完成此电路的版图实现，直⾄完成的结果和预期结果保持⼀致。

关键词：Tanner EDA；L-Edit；移位寄存器，S-Edit8 bits shift register circuit design and layoutAbstractElectronic design automation,referred to as EDA,it is based on computers as the main tool,and Tanner EDA is a kind of software that complete the integrated circuit design on Windows platforms.Its Sub-Softwares include S-Edit，T-Spice，W-Edit，L-Edit and LVS and so on.S-Edit and L-Edit are commonly used software,S-Edit is primarily designed to achieve circuit,the latter is aimed primarily known circuit layout drawing,T-Spice can achieve schematic and layout simulation.We can achieve layout of the circuit design and a series of complete process layout used Tanner EDA tools.In this paper, Tanner EDA tools are mainly designed an 8-bit shift register.The shift register is mainly used for data conversion between parallel and serial, and the data processing tool operation or professional,its main structure is the trigger composition,flip-flop is a storage function,it can be used to store more hexadecimal code,In general N-bits register is composed of N trigger.Working principle of the shift register data under the action of the pulse, mainly the effect of the shift to the left or right,input and output of the way of serial and parallel free combination.This design is in Tanner on the EDA software platform to 8 bits shift register circuit design and simulation,then according to the circuit diagram on special L - Edit platform to complete the circuit layout implementation,until the finish is consistent with the results and expected results.Keywords：Tanner EDA；L-Edit；Shift register，S-Edit⽬录1 前⾔ (1)1.1 课题的背景和⽬的 (1)1.2课题的设计内容 (1)2 设计软件简介 (2)2.1EDA技术的介绍 (2)2.2T ANNER EDA T OOLS的简述 (2)2.3T ANNER软件的组成及发展 (3)2.3.1 Tanner的设计流程 (4)2.3.2 Tanner软件的发展 (5)2.3.3 L-Edit软件的介绍 (6)2.48位移位寄存器的⼯作原理和设计要求 (9)2.4.1 ⼯作原理 (9)2.4.2 电路结构与设计 (11)3 8位移位寄存器的电路设计与版图实现过程 (13)3.1各个模块的设计与仿真 (13)3.1.1 带复位端D触发器的设计与版图实现 (13)3.1.2 与或⾮门的设计与版图实现 (16)3.28位移位寄存器的电路设计与版图实现 (18)3.2.1 8位移位寄存器的电路结构 (18)3.2.2 8位移位寄存器的版图实现 (19)3.2.3 LVS对⽐ (21)4 结束语 (21)参考⽂献 (22)巢湖学院2013届本科毕业论⽂(设计)1 前⾔1.1 课题的背景和⽬的随着科技的进步，近⼏个世纪寄存器技术不断成熟，在数字电路中，寄存器已经是⼀个经常被提出的概念，它主要指的是⽤来存放⼆进制数据或者代码的电路。

8bitCPU

正弦信号发生器实验报告88132639殷达1.实验内容（1）设计要求：设计一正弦信号发生器，采用ROM 宏功能模块进行一个周期数据存储，并通过地址发生器产生正弦信号。

（2）设计内容：地址6位；ROM ：6位地址8位数据；原理图完成顶层设计；2.实验原理（1）正弦波信号发生器是由地址发生器和正弦波数据存储器ROM 两块构成，输入为时钟脉冲，输出为8位二进制。

（2）地址发生器的原理: 地址发生器实质上就是计数器，ROM 的地址是6位数据，相当于64位循环计数器。

（3）只读存储器ROM 的设计、VHDL 编程的实现①基本原理：为每一个存储单元编写一个地址，只有地址指定的存储单元才能与公共的I/O 相连，然后进行存储数据的读写操作。

②逻辑功能：地址信号的选择下，从指定存储单元中读取相应数据。

（4）基于LPM 宏功能模块的存储器的设计①LPM ：Library of Parameterized Modules ，可参数化的宏功能模块库。

②Quartus II 提供了丰富的LPM 库，这些LPM 函数均基于Altera 器件的结构做了优化处理。

③在实际的工程中，设计者可以根据实际电路的设计需要，选择LPM 库中适当的模块，并为其设置参数，以满足设计的要求，从而在设计中十分方便的调用优秀的电子工程技术人员的硬件设计成果。

3．原理图，VHDL 设计(1)ROM 的单元数据（2）地址发生器的VHDL 语言的实现library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity addr_count isport(clk1kHz: in std_logic;qout: out integer range 0 to 63);end addr_count;architecture behave of addr_count issignal temp:integer range 0 to 63;beginprocess(clk1kHz)beginif(clk1kHz'event and clk1kHz='1') thenif(temp=63) thentemp<=0;elsetemp<=temp+1;end if;end if;qout<=temp;end process;end behave;（3）为了在示波器上得到更好的现象需要对FPGA模块进行分频处理分频的ＶＨＤＬ语言如下library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fenpin isgeneric(N: integer:=800);port(clkin: in std_logic;clkout: out std_logic);end fenpin;architecture behave of fenpin issignal cnt:integer range 0 to N-1;begin--fenpinprocess(clkin)beginif(clkin'event and clkin='1')thenif(cnt<N-1)thencnt<=cnt+1;elsecnt<=0;end if;end if;end process;process(cnt)beginif(cnt<n/2)thenclkout<='1';elseclkout<='0';end if;end process;end behave;（4）顶层设计原理图（5）仿真报告。

8位骨灰级CPU电路图

9 10
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2 1
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U 29A 12 74F 10
Y1
1 3 74F 02 U 24B 5 4 6 74F 02 U 24C 8 10 9 74F 02
R1 锁存
3 1 74F 86
DB 7 DB 6 DB 5 DB 4
DB 3 DB 2 DB 1 DB 0
DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0
19 16 15 12 9 6 5 2
U 10E 74F 04 10 12
U 10F 74F 04 8
2Y 4 2Y 3 2Y 2 2Y 1
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8
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B4 B3 B2 B1 2G
17 15 13 11 19
A LU _A7 A LU _A6 A LU _A5 A LU _A4 A LU _A3 A LU _A2 A LU _A1 A LU _A0
3 5 7 9
12 14 16 18
2
U 11B 74F 20
U 26A 74F 20
U 27 74F 30
U 26B 74F 20
U 28A 74F 20
U 23B 74F 00
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11
3
3 5 7 9
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累加器到 RA M 传送指令累加器到寄存器传送指令加法指令
8 13 12
8 10 74F 32
A4 A3 A2 A1 1G
执行1电平 2
执行 1脉冲3
U 4C 9
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3 5 7 9

8位CPU的设计与实现

计算机组成原理实验题目８位CPＵ得系统设计学号11151０6０4６姓名魏忠淋班级 11电子B 班指导老师凌朝东华侨大学电子工程系8位CＰＵ得系统设计一、实验要求与任务完成从指令系统到ＣＰU得设计,编写测试程序,通过运行测试程序对CPU设计进行正确性评定。

具体内容包括:典型指令系统(包括运算类、转移类、访存类)设计;CＰU结构设计;规则文件与调试程序设计;CＰU调试及测试程序运行。

1。

1设计指标能实现加减法、左右移位、逻辑运算、数据存取、有无条件跳转、内存访问等指令;1、2设计要求画出电路原理图、仿真波形图;二、CPＵ得组成结构三、元器件得选择1.运算部件(ALU)AＬＵ181得程序代码:LIBRARY ＩEEE;USＥＩEEE、ＳTD_LＯGＩC_1１64。

ALL;USＥIEEE、ＳTＤ＿LOGIＣ_UＮＳIGNＥD.ＡLＬ;ENTＩＴY ＡLU181 ＩSPORＴ(S: IN STD＿LＯＧIC＿VECTＯR(3 ＤＯＷNTO0 );A:ＩN STD_LOGIC_VＥCTOＲ(7 ＤOWNＴＯ0);B: IＮSTD＿ＬOGIC＿VEＣTOR(7DＯWNＴO ０);F : OUT STＤ_LOGIC_ＶECTOR(7 DOWＮTO 0);ﻩCOUＴ:ＯUＴSTD_ＬＯＧIC_ＶECTOR(3 DOＷＮＴO0);M :IＮＳTＤ_LOGＩC;CN : IN SＴD_LOGIＣ;CＯ,ＦZ:OUT STＤ_LOGIC );END AＬU１81;AＲCHIＴＥCTＵRE bｅhav OF ALＵ181 ＩSSIGＮＡＬA9 :STＤ_LＯGIC_VECTOR(８DOWNTO 0);SIＧNAL B9 : STD＿LOGIC_VＥCTOR(8 ＤOWNTＯ０);ＳIGNALＦ9: STD_LOGIC＿VECＴOＲ(8 DＯWNTO0);BＥGINＡ９<= ＇0＇& A; B9 ＜= ’0’&B;PRＯCESS(M,CＮ,A9,B９)BEGINＣASE S ISWHEN "0００0" =〉IF M=＇0’THEN F9＜=A9 + CN ; ＥLSE F9<=ＮOT Ａ９; E ＮＤIF;WHEN "00０1" ＝＞ＩF M='0’THEN F９<=(A9 oｒB９)+ CN ;ELSE F９〈=NOＴ(A9OR B9);END ＩF;ＷHEN ”0010＂=> IF M=’0’THEN F9〈=(A9 ｏｒ(ＮOT B9))+C Ｎ; ELSE F9＜=(NOT A9) ANDＢ9; ENＤIF;WＨＥN "００1１＂=> IF M='0’ＴHEN Ｆ9<= ”000000000"—CN ;ELSＥF9<＝"00000000０”;END IF;WHEN"0100”＝> IＦM='0＇THEＮＦ9<＝A9+(A9 ＡＮＤＮOT B9)+ CＮ; ELSE F9〈=NＯT(A9 ＡNＤB9);ＥND IＦ;WHEN ”01０1”=＞IＦM＝＇0' THＥNＦ9<=(A９oｒB9)+(A9 AＮD NOＴB９)+CN ;ＥＬＳＥF9<=NOT Ｂ9; EＮD IF;WHEN＂0110" =＞IＦＭ=’0’ＴHEN Ｆ9〈=(Ａ９- Ｂ9) －CN ;ELＳE F9〈＝Ａ9ＸOR B９; ＥNＤIF;WHEＮ”０111"=＞IF M='0' ＴＨEN F9〈=(Ａ9 ｏｒ(NＯT B9)) －CN ;ＥＬSE Ｆ9<=Ａ9 and (ＮOT B9); EＮD IF;WHEN＂１000" =＞IＦM='0＇THEN F9＜=Ａ９+ (A９ＡND B9)+CN ; ELＳE F9〈＝(NOＴA９)and B９; END IＦ;WHEN "１0０1”=> IF M=’０’ＴHEN F9〈=Ａ９+ B9 + CN ; ＥLSE F9<=NOT(Ａ9 ＸOR Ｂ9); EＮＤIF;WＨEN ”１010"=＞ＩF M=’0＇THEN F９〈＝(A9or(NOTＢ9))+(A ９AND B9)＋CN ; ＥLＳＥF９<=Ｂ9;EＮD ＩＦ;ＷHEN "１０11”=〉IF M='0'TＨEＮF9<=(A9 AND Ｂ9)- C Ｎ; ELSE F9<=A9 ANＤB９; ENＤIF;ＷHEN ”1100”=〉ＩF M=＇0＇ＴHＥＮＦ9<=(A9 +Ａ9) + CN; ＥLSＥF9〈="000000001"; END ＩF;ＷHEN ＂１101”=〉IF M='0' THEN Ｆ９〈＝(A９ｏr B９)+ A9 + CN;EＬSＥＦ9〈=A9 OR (ＮＯＴB9); END ＩF;WHＥN "1１１0"=＞IF M＝'０＇THEＮF9＜=((A9 or (ＮＯＴB9)) +A9) + CN; ＥLSE F９〈＝A9OR B9;ＥＮD IF;WＨEＮ”1１11”=〉IＦＭ=’０'ＴHEＮF9<＝Ａ9 —CN ;EＬSE F9<=Ａ9 ; END IＦ;WHEN OTHＥRS=> Ｆ9＜= ”０000０００00" ;ENＤＣASE;IＦ(A９=B９) TＨＥNＦＺ<=’0';END IF;ﻩEＮD ＰROCＥSS;Ｆ＜=F9(７DOWNＴO0) ;ＣＯ<= F9(8) ;ＣOUT<=＂０0０0＂WHEN F9(８)=’0＇EＬSＥ"0０01";EＮD behav;ALU得原理图:2、微控制器实现信息传送要靠微命令得控制,因此在CPU 中设置微命令产生部件,根据控制信息产生微命令序列,对指令功能所要求得数据传送进行控制,同时在数据传送至运算部件时控制完成运算处理。

8位CPU的设计与实现

计算机组成原理CPU 实验题目 8位的系统设计1115106046 号学魏忠淋姓名B 11电子班班级凌朝东指导老师华侨大学电子工程系8位CPU的系统设计一、实验要求与任务完成从指令系统到CPU的设计，编写测试程序，通过运行测试程序对CPU设计进行正确性评定。

具体内容包括：典型指令系统（包括运算类、转移类、访存类）设计；CPU结构设计；规则文件与调试程序设计；CPU调试及测试程序运行。

1.1设计指标能实现加减法、左右移位、逻辑运算、数据存取、有无条件跳转、内存访问等指令；1.2设计要求画出电路原理图、仿真波形图；二、CPU的组成结构三、元器件的选择1.运算部件(ALU)ALU181的程序代码：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ALU181 ISPORT (S : IN STD_LOGIC_VECTOR(3 DOWNTO 0 );A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);F : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);COUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);M : IN STD_LOGIC;CN : IN STD_LOGIC;CO,FZ: OUT STD_LOGIC );END ALU181;ARCHITECTURE behav OF ALU181 ISSIGNAL A9 : STD_LOGIC_VECTOR(8 DOWNTO 0);SIGNAL B9 : STD_LOGIC_VECTOR(8 DOWNTO 0);SIGNAL F9 : STD_LOGIC_VECTOR(8 DOWNTO 0);BEGINB9 <= '0' & B ; A9 <= '0' & A ;PROCESS(M,CN,A9,B9)BEGINCASE S ISWHEN ぜ?尰=> IF M='0' THEN F9<=A9 + CN ; ELSE F9<=NOT A9; END IF;WHEN IF M='0' THEN F9<=(A9 or B9) + CN ; ELSEF9<=NOT(A9 OR B9); END IF;WHEN 0 => IF M='0' THEN F9<=(A9 or (NOT B9))+ CN ; ELSEF9<=(NOT A9) AND B9; END IF;WHEN 1 => IF M='0' THEN F9<= ; ELSEF9<= END IF;WHEN 0 => IF M='0' THEN F9<=A9+(A9 AND NOT B9)+ CN ; ELSE F9<=NOT (A9 AND B9); END IF;WHEN 1 => IF M='0' THEN F9<=(A9 or B9)+(A9 AND NOT B9)+CN ; ELSE F9<=NOT B9; END IF;WHEN 0 => IF M='0' THEN F9<=(A9 - B9) - CN ; ELSE F9<=A9 XOR B9; END IF;WHEN 1 => IF M='0' THEN F9<=(A9 or (NOT B9)) - CN ; ELSE F9<=A9 and (NOT B9); END IF;WHEN @0 => IF M='0' THEN F9<=A9 + (A9 AND B9)+CN ; ELSE F9<=(NOT A9)and B9; END IF;WHEN @1 => IF M='0' THEN F9<=A9 + B9 + CN ; ELSE F9<=NOT(A9 XOR B9); END IF;WHEN A0 => IF M='0' THEN F9<=(A9 or(NOT B9))+(A9 AND B9)+CN ;ELSE F9<=B9; END IF;WHEN A1 => IF M='0' THEN F9<=(A9 AND B9)- CN ;ELSE F9<=A9 AND B9; END IF;WHEN H0 => IF M='0' THEN F9<=(A9 + A9) + CN ; ELSEF9<= END IF;WHEN H1 => IF M='0' THEN F9<=(A9 or B9) + A9 + CN ; ELSEF9<=A9 OR (NOT B9); END IF;WHEN I0 => IF M='0' THEN F9<=((A9 or (NOT B9)) +A9) + CN ; ELSEF9<=A9 OR B9; END IF;WHEN I1 => IF M='0' THEN F9<=A9 - CN ; ELSEF9<=A9 ; END IF;WHEN OTHERS => F9<=END CASE;IF(A9=B9) THEN FZ<='0';END IF;END PROCESS;F<= F9(7 DOWNTO 0) ; CO <= F9(8) ;COUT<=END behav;ALU的原理图：2.微控制器实现信息传送要靠微命令的控制，因此在CPU 中设置微命令产生部件，根据控制信息产生微命令序列，对指令功能所要求的数据传送进行控制，同时在数据传送至运算部件时控制完成运算处理。

专题4-精简8位CPU电路设计

将9H内存的内容值加载累加器
将BH的内存内容值和累加器内容值相加,再存放运算结果回累加器将EH的内存内容值和累加器内容值相减,再存放运算结果回累加器
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零位寻址法(Zero Addressing)
指令 OUT HLT
运算码 1110 1111
范例 OUT HLT
说明
将累加器内容输出至“输出寄存器” 结果CPU执行
CLR
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CP EP LM CE LI EI LA EA SU EU LB LO
图1: SAP-1结构
2.输入与MAR(Memory Access Register)
这个方块应分成两个部分,一个是接受由“输入”部分输入到RAM内存的外部
程序和数据,另一部分“MAR”是用来在CPU执行上述所加载的程序时,暂存下一
图1: SAP-1结构
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8位CPU的设计-VHDL语言-综合性实验实验报告

综合性实验报告计算机组成原理年级专业班级：10级软工R3班小组号： 5完成日期：2012-06-06【分工包括：、、执行(ALU相关)、通用寄存器组、存储器等】（一）实验类型：验证性+设计性（二）实验类别：综合性专业基础实验（三）实验学时数：8学时（四）实验目的理解和验证参考代码，并在其基础上，通过适当改造，尝试设计一个简单的CPU，并测试其结果。

（五）实验内容设计一个能验证计算机CPU工作原理的实验系统，包括取指部分、指令译码部分、执行部分、通用寄存器组以及存储器，并测试其结果。

（六）实验要求根本目标：缩小到8位的数据通路，也即是4位OP和4位的地址码。

（参考代码是16位数据通路，也即8位OP和8位的地址码）(参见实践报告.doc中的9-11页的指令系统总体说明)学生按照实验要求，在实验平台上实现具有存储与运算功能的计算机系统，并能通过测试，以验证其正确性。

具体要求如下：（1）取指及调试(组长兼任)。

熟悉指令取指过程，并把16位的部分改为8位。

使用DebugController和系统中的调试模块(reg_testa.vhd，reg_test.vhd)。

（2）熟悉电原理图的连接，以通用寄存器组部分为例。

实现上，用实验4所用的简单通用寄存器组（4个寄存器+1个2-4译码器+2个4选1多路开关）设计方法，替代参考代码中的通用寄存器组部分。

（3）学习和掌握控制逻辑。

设计一套指令集（可在原参考代码指令集的基础上做删减，从中选取16条基本的指令），并修改控制器中指令集的译码部分。

（4）执行部件，ALU的改造。

可在原参考代码的基础上，改变某些运算功能的实现方式，比如加、减、增1、减1等算术运算。

实现上，原参考代码采用了最少编码量的“+”、“-”号实现。

可以改用通过port map语句调用系统自带的加法器，也可以进一步自己编写加法器，然后用port map语句调用。

（5）存储器部分的加入。

原参考代码采用的带外部存储器的模式。

CPU设计实践教程8-8位7段数码管控制的设计

实验内容
使用Verilog HDL实现一个1位7段数码管的编码控制器hexseg，可以在Minisys实验板的数码管上显示1位16进制数。
2021/9/5 P.4
实验1. 1位7段数码管控制器的设计
实验预习
请根据2.4.4节自行列出各个数字的7段数码管真值表，并按照真值表设计7段数码管编码器。
计算机系统能力培养系列
CPU设计实践教程 ——从数电到计算机组成
数字逻辑电路实验
2021/9/5 P.1
计算机系统能力培养系列
8. 8位7段数码管控制的设计
2021/9/5 P.2
实验1. 1位7段数码管控制器的设计
实验目的
学会控制1位7段数码管的显示。
2021/9/5 P.3
实验1. 1位7段数码管控制器的设计
实验3.六十进制数字时钟的设计
实验内容
使用Verilog HDL结合实验1和实验2设计的hexseg 与hexseg8实现一个数字时钟clock60
要求能有秒、分和小时的计数与输出
用数码管A1,A0显示秒值数码管A2,A3显示分值数码管A4,A5显示小时数码管A6,A7不显示。
实验目的
学会控制8位7段数码管的显示巩固计数器的设计。
2021/9/5 P.8
实验2. 8位7段数码管控制器的设个实验设计的hexseg的改造版本，实现一个8位十六进制数显示的数码管显示控制模块hexseg8。
要求能同时稳定地显示各个位的数字，并能定义8 位数码管哪些位需要显示，哪些位不需要显示。（比如要显示十六进制数0x387A6D，就只需要图2-7 中A4~A0这5位数码管显示，而A7~A5这3位不显示）
思考与拓展
4.4.1节设计了一个8位的加法器，考虑将该加法器的运算结果输出到数码管上。

一个简单的8位处理器完整设计过程及verilog代码

一个简单的8位处理器完整设计过程及verilog代码来源： EETOP BBS 作者：weiboshe一个简单的8位处理器完整设计过程及verilog代码,适合入门学习参考，并含有作者个人写的指令执行过程（点击下方阅读原文到论坛可下载源码）1. CPU定义我们按照应用的需求来定义计算机，本文介绍一个非常简单的CPU的设计，它仅仅用来教学使用的。

我们规定它可以存取的存储器为64byte，其中1byte=8bits。

所以这个CPU就有6位的地址线A[5：0]，和8位的数据线D[7：0]。

我们仅定义一个通用寄存器AC（8bits寄存器），它仅仅执行4条指令如下：Instruction Instruction Code OperationADD00AAAAAA AC<—AC+M[AAAAAA]AND01AAAAAA AC<—AC^M[AAAAAA]JMP10AAAAAA GOTO AAAAAAINC11XXXXXX AC<—AC+1除了寄存器AC外，我们还需要以下几个寄存器：地址寄存器 A[5：0]，保存6位地址。

程序计数器 PC[5：0]，保存下一条指令的地址。

数据寄存器 D[7：0]，接受指令和存储器来的数据。

指令寄存器 IR[1：0]，存储指令操作码。

2. 取指设计在处理器执行指令之前，必须从存储器取出指令。

其中取指执行以下操作：1〉通过地址端口A[5：0]从地址到存储器2〉等待存储器准备好数据后，读入数据。

由于地址端口数据A[5：0]是从地址寄存器中读出的，所以取指第一个执行的状态是Fetch1： AR<—PC接下来cpu发出read信号，并把数据从存储器M中读入数据寄存器DR中。

同时pc加一。

Fetch2： DR<—M，PC<—PC+1接下来把DR[7：6]送IR，把DR[5：0]送ARFetch3： IR<—DR[7：6]，AR<—DR[5：0]3. 指令译码Cpu在取指后进行译码一边知道执行什么指令，对于本文中的CPU来说只有4条指令也就是只有4个执行例程，状态图如下：4. 指令执行对译码中调用的4个例程我们分别讨论：4.1 ADD指令ADD指令需要CPU做以下两件事情：1〉从存储器取一个操作数2〉把这个操作数加到AC上，并把结果存到AC所以需要以下操作：ADD1： DR<—MADD2： AC<—AC+DR4.2 AND指令AND指令执行过程和ADD相似，需要以下操作：AND1： DR<—MAND2： AC<—AC^DR4.3 JMP指令JMP指令把CPU要跳转的指令地址送PC，执行以下操作JMP1： PC<—DR[5：0]4.4INC指令INC指令执行AC+1操作INC1： AC<—AC+1总的状态图如下：5 建立数据路径这一步我们来实现状态图和相应的寄存器传输。

VHDL-8位CPU设计-包含程序

Computer Organization and ArchitectureCourse DesignThe Experiment ReportOfCPUI . PurposeThe purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need consider the following items: Read/Write Registers, Read/Write Memory and Execute the instructions.At least four parts constitute a simple CPU: the control unit, the internal registers, the ALU and instruction set, which are the main aspects of our project design and will be studied.II . Instruction SetSingle-address instruction format is used in our simple CPU design. The instruction word contains two sections: the operation code (opcode), which defines the function of instructions (addition, subtraction, logic operations, etc.); the address part, in most instructions, the address part contains the memory location of the datum to be operated, we called it direct addressing. In some instructions, the address part is the operand, which is called immediate addressing.For simplicity, the size of memory is 256×16 in the computer. The instruction word has 16 bits. The opcode part has 8 bits and address part has 8 bits. The instruction word format can be expressed in Figure 1:The opcode of the relevant instructions are listed in Table 1.In Table 1, the notation [x] represents the contents of the location x in the memory. For example, the instruction word 00000011101110012 (03B916) means that the CPU adds word at location B916 inmemory into the accumulator (ACC); the instructionword 00000101000001112 (050716) means if the sign bit of the ACC (ACC [15]) is 0, the CPU will use the address part of the instruction as the address of next instruction, if the sign bit is 1, the CPU will increase the program counter (PC) and use its content as the address of the next instruction.Table 1 List of opcode of the relevant instructionsA program is designed to test these instructions:Calculate the sum of all integers from 1 to 100.(1), programming with C language:sum=0;temp=100;loop :sum=sum+temp;temp=temp-1;if temp>=0 goto loop;end(2), Assume in the RAM_DQ:sum is stored at location A4,temp is stored at location A3,the contents of location A0 is 0,the contents of location A1 is 1,the contents of location A2 is 10010=6416.We can translate the above C language program with the instructions listed in Table 1 into the instruction program as shown in Table 2.Table 2 Example of a program to sum from 1 to 100III. Internal Registers and MemoryMAR (Memory Address Register)MAR contains the memory location of the word to be read from the memory or written into the memory. Here, READ operation is denoted as the CPU reads from memory, and WRITE operation is denoted as the CPU writes to memory. In our design, MAR has 8 bits to access one of 256 addresses of the memory.MBR (Memory Buffer Register)MBR contains the value to be stored in memory or the last value read from memory. MBR is connected to the address lines of the system bus. In our design, MBR has 16 Bits.PC (Program Counter)PC keeps track of the instructions to be used in the program. In our design, PC has 8 bits.IR (Instruction Register)IR contains the opcode part of an instruction. In our design, IR has 8 bits.BR (Buffer Register)BR is used as an input of ALU, it holds other operand for ALU. In our design, BR has16 bits.LPM_RAM_DQLPM_RAM_DQ is a RAM with separate input and output ports. It works as a memory, and its size is 256×16. Although it’s not an internal register of CPU, we need it to simulate and test the performance of CPU.LPM_ROMLPM_ROM is a ROM with one address input port and one data output port, and its size of data is 32bits which contains control signals to execute micro-operations.IV.ALUALU (Arithmetic Logic Unit) is a calculation unit which accomplishes basic arithmetic and logic operations. In our design, some operations must be supported which are listed as follows:Table 3 ALU OperationsV. Micro-programmed Control UnitIn the Microprogrammed control, the microprogram consists of some microinstruction and the microprogram is stored in control memory that generates all the control signals required to execute the instruction set correctly. The microinstruction contains some micro-operations which are executed at the same time.Figure 2 shows the key elements of such an implementation.The set of microinstructions is stored in the control memory. The control address register contains the address of the next microinstructions to be read. When a microinstruction is read from the control memory, it is transferred to a control buffer register. The register connects to the control lines emanating from the control unit. Thus, reading a microinstruction from the control memory is the same as executing that microinstruction. The third element shown in the figure is a sequencing unit that loads the control address register and issues a read command.Figure 2 Control Unit Micro-architecture (I)Total control signals for instructions are listed as follows:Table 4 Control signals for the micro-operations(II)The contents in rom.mif and the corresponding microprograms are listed as follows:0 : 00810000; R←1, CAR←CAR+11 : 00A00000; OP←MBR[15..8],CAR←CAR+12 : 02000000; CAR←CAR+OP3 : 01000014; CAR←14H4 : 01000019; CAR←19H5 : 0100001E; CAR←1EH6 : 01000023; CAR←23H7 : 01000041; CAR←41H8 : 01000028; CAR←28H9 : 0100002D; CAR←2DHa : 01000032; CAR←32Hb : 01000037; CAR←37Hc : 0100003C; CAR←3CHd : 01000046; CAR←46He : 0100004B; CAR←4Hf : 00000000;………14 : 00840000; MAR←MBR[7..0], CAR←CAR+1 ------STORE15 : 00920200; MBR←ACC, PC←PC+1,W←1,CAR←CAR+116 : 04080000; CAR←017 : 00000000;18 : 00000000;19 : 00840000; MAR←MBR[7..0], CAR←CAR+1 ------LOAD 1a : 00810A00; PC←PC+1,R←1,ACC←0,CAR←CAR+11b : 00C03000; BR←MBR,ACC←ACC+BR, CAR←CAR+11c : 04080000; CAR←01d : 00000000;1e : 00840000; MAR←MBR[7..0], CAR←CAR+1 ----------ADD 1f : 00810200; PC←PC+1,R←1,CAR←CAR+120 : 00C03000; BR←MBR,ACC←ACC+BR, CAR←CAR+121 : 04080000; CAR←022 : 00000000;23 : 00840000; MAR←MBR[7..0], CAR←CAR+1 ----------SUB24 : 00810200; PC←PC+1,R←1,CAR←CAR+125 : 00C04000; BR←MBR,ACC←ACC-BR, CAR←CAR+126 : 04080000; CAR←027 : 00000000;28 : 00840000; MAR←MBR[7..0], CAR←CAR+1 ---------AND29 : 00810200; PC←PC+1,R←1,CAR←CAR+12a : 00C06000; BR←MBR,ACC←ACC AND BR,CAR←CAR+1 2b : 04080000; CAR←02c : 00000000;2d : 00840000; MAR←MBR[7..0], CAR←CAR+1 ---------OR 2e : 00810200; PC←PC+1,R←1,CAR←CAR+12f : 00C07000; BR←MBR,ACC←ACC OR BR, CAR←CAR+130 : 04080000; CAR←031 : 00000000;32 : 00840000; MAR←MBR[7..0], CAR←CAR+1 ----------NOT33 : 00808200; PC←PC+1, ACC←NOT ACC,CAR←CAR+134 : 04080000; CAR←035 : 00000000;36 : 00000000;37 : 00840000; MAR←MBR[7..0], CAR←CAR+1 ----------SHIFTR38 : 08092000; PC←PC+1, ACC←SHIFT ACC to Right 1 bit,CAR←CAR+139 : 04080000; CAR←03a : 00000000;3b : 00000000;3c : 00840000; MAR←MBR[7..0], CAR←CAR+1 -----------SHIFTL3d : 0080A200; PC←PC+1, ACC←SHIFT ACC to Left 1 bit,CAR←CAR+1 3e : 04080000; CAR←03f : 00000000;40 : 00000000;41 : 00840000; MAR←MBR[7..0], CAR←CAR+1 -----------JMPGEZ42 : 00805000; CAR←CAR+1,43 : 04080000; CAR←044 : 00000000;45 : 00000000;46 : 00840000; MAR←MBR[7..0], CAR←CAR+1 ------------MPY47 : 00810200; PC←PC+1,R←1,CAR←CAR+148 : 00C0B000; BR←MBR,ACC←ACC*BR, CAR←CAR+149 : 04080000; CAR←04a : 00000000;4b : 0100004B; CAR←4BH ------------------------------HALT 4c : 00000000;(III)The simulation waveforms of some operates1, load, add, store, halt (22+10)The contents in RAM:0 : 022A; Load 2A1 : 032B; ADD 2B2 : 012C; Store 2C3 : 0C00; Halt2a : 0016;2b : 000A;The content in RAM addressed of 2b is 0020(H).The waveform of the operate:2, load, SUB, store, halt (22-10)The contents in RAM:0 : 022A; Load 2A1 : 042B; SUB 2B2 : 012C; Store 2C3 : 0C00; Halt2a : 0016;2b : 000A;The content in RAM addressed of 2c is 000C(H). The waveform of the operate:3, load, mpy, add, store, halt (13*10+22)The contents in RAM:0 : 022A; Load 2A1 : 0B2B; MPY 2B2 : 032C; ADD 2C3 : 012D; Store 2D4 : 0C00; Halt2a : 000D;2b : 000A;2c : 0016;The content in RAM addressed of 2d is 0098(H). The waveform of the operate:4, S um from 1 to 100The contents in RAM are shown in table2.The content in RAM addressed of A4 is 13BA(H).The waveform of the operate:The clock cycle of CAR is 400 ns.From the waveform, it takes 2.314ms to execute the operate. So the number of the executing cycles is 2.134/0.0004=5335.VI. Appendix:(I)The GDF of CPU:(II) The code of the CPU program:1, MBR (Memory Buffer Register) library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity MBR isport( clk, reset, MBR_OPc, ACC_MBRc,R,W:in std_logic;ACC_MBR :in std_logic_vector(15 downto 0);RAM_MBR :in std_logic_vector(15 downto 0);MBR_RAM :out std_logic_vector(15 downto 0);MBR_BR :out std_logic_vector(15 downto 0);MBR_OP :out std_logic_vector(7 downto 0);MBR_MAR :out std_logic_vector(7 downto 0);MBR_PC :out std_logic_vector(7 downto 0));end MBR;architecture behave of MBR isbeginprocess(clk)variable temp:std_logic_vector(15 downto 0);beginif(clk'event and clk='0')thenif reset='1' thenif ACC_MBRc='1' then temp:=ACC_MBR; end if;if R='1' then MBR_BR<=RAM_MBR; end if;if W='1' then MBR_RAM<=temp; end if;MBR_MAR<=RAM_MBR(7 downto 0);MBR_PC<=RAM_MBR(7 downto 0);if MBR_OPc='1' then MBR_OP<=RAM_MBR(15 downto 8); end if;else MBR_BR<=x"0000";MBR_MAR<="00000000";MBR_OP<="00000000";MBR_PC<="00000000";end if;end if;end process;end behave;2, BR (Buffer Register)library ieee;use ieee.std_logic_1164.all;entity BR isport( MBR_BRc:in std_logic;MBR_BR:in std_logic_vector(15 downto 0);BRout:out std_logic_vector(15 downto 0));end BR;architecture behave of BR isbeginprocessbeginif MBR_BRc='1' then BRout<=MBR_BR; end if; end process;end behave;3, MAR (Memory Address Register)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity MAR isport( clk,PC_MARc,MBR_MARc:in std_logic;PC,MBR_MAR:in std_logic_vector(7 downto 0);MARout:out std_logic_vector(7 downto 0));end MAR;architecture behave of MAR isbeginprocess(clk)beginif(clk'event and clk='1')thenif PC_MARc='1' then MARout<=PC; end if;if MBR_MARc='1' then MARout<=MBR_MAR; end if;end if;end process;end behave;4, PC (Program Counter)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity PC isport( clk,PCjmp,PCc1,PCinc,PCc3,reset:in std_logic;CONTRalu :in std_logic_vector(3 downto 0);MBR_PC :in std_logic_vector(7 downto 0);PCout :buffer std_logic_vector(7 downto 0));end PC;architecture behave of PC isbeginprocess(clk)beginif(clk'event and clk='0')thenif reset='1' thenif CONTRalu="0101" thenif PCjmp='1' then PCout<=MBR_PC;elsif PCjmp='0' then PCout<=PCout+1;end if;end if;if PCc1='1' then PCout<="00000000"; end if;if PCinc='1' then PCout<=PCout+1; end if;if PCc3='1' then PCout<=MBR_PC; end if;else PCout<="00000000";end if;end if;end process;end behave;5, IR (Instruction Register)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity IR isport( opcode :in std_logic_vector(7 downto 0);IRout :out std_logic_vector(7 downto 0));end IR;architecture behave of IR isbeginIRout<=opcode;end behave;6, CAR (Control Address Register)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity CAR isport( clk,reset :in std_logic;CARc :in std_logic_vector(3 downto 0);CAR,OP :in std_logic_vector(7 downto 0);CARout:buffer std_logic_vector(7 downto 0));end CAR;architecture behave of CAR isbeginprocess(clk)beginif(clk'event and clk='1')thenif reset='1' thenif CARc="1000" then CARout<="00000000"; end if;if CARc="0100" then CARout<=OP+CARout; end if;if CARc="0010" then CARout<=CAR; end if;if CARc="0001" then CARout<=CARout+1; end if;else CARout<="00000000";end if;end if;end process;end behave;7, CONTRALR (Control Buffer Register)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity CONTROLR isport(control :in std_logic_vector(31 downto 0);R,W, RW, PCc1,PCinc,PCc3:out std_logic;ACCclear,MBR_MARc,PC_MARc:out std_logic;ACC_MBRc,MBR_OPc,MBR_BRc:out std_logic;CONTRout:out std_logic_vector(3 downto 0);CARc :out std_logic_vector(3 downto 0);CAR :out std_logic_vector(7 downto 0)); end CONTROLR;architecture behave of CONTROLR isbeginprocessbeginCAR<=control(7 downto 0);PCc1<=control(8);PCinc<=control(9);PCc3<=control(10);ACCclear<=control(11);CONTRout<=control(15 downto 12);R<=control(16);W<=control(17);MBR_MARc<=control(18);PC_MARc<=control(19);ACC_MBRc<=control(20);MBR_OPc<=control(21);MBR_BRc<=control(22);CARc<=control(26 downto 23);RW<=control(17);end process;end behave;8, ALU (Arithmetic Logic Unit) library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ALU isport( clk,reset,ACCclear:in std_logic;aluCONTR :in std_logic_vector(3 downto 0);BR :in std_logic_vector(15 downto 0);PCjmp :out std_logic;ACC :buffer std_logic_vector(15 downto 0));end ALU;architecture behave of ALU isbeginprocess(clk)beginif(clk'event and clk='0')thenif reset='0' then ACC<=x"0000";elseif ACCclear='1' then ACC<=x"0000"; end if;if aluCONTR="0011" then ACC<=BR+ACC; end if; --ADDif aluCONTR="0100" then ACC<=ACC-BR; end if; --SUBif aluCONTR="0110" then ACC<=ACC and BR; end if; --ANDif aluCONTR="0111" then ACC<=ACC or BR; end if; --ORif aluCONTR="1000" then ACC<=not ACC; end if; --NOTif aluCONTR="1001" then --SRRACC(14 downto 0)<=ACC(15 downto 1); ACC(15)<='0';end if;if aluCONTR="1010" then --SRL ACC(15 downto 1)<=ACC(14 downto 0); ACC(0)<='0';end if;if aluCONTR="1011" then ACC<=ACC*BR; end if; --MPYend if;end if;if ACC>0 then PCjmp<='1';else PCjmp<='0';end if;end process;end behave;如有侵权请联系告知删除，感谢你们的配合！如有侵权请联系告知删除，感谢你们的配合！。

基于VHDL语言的8位RISC-CPU的设计终稿

毕业设计说明书基于VHDL语言的8位RISC-CPU的设计学院：专业：学生姓名：学号：指导教师：201 年月中文摘要摘要RISC即精简指令集计算机（Reduced Instruction Set Computer）的缩写。

RISC-CPU与一般的CPU相比，通过简化指令系统使计算机的结构更加简单合理，从而提高了运算速度。

本文对RISC-CPU的架构进行了分析，并使用VHDL 语言设计了8位RISC-CPU IP软核。

RISC-CPU由八大基本模块构成：时钟发生器、指令寄存器、累加器、算术逻辑单元、数据输出控制器、地址多路器、程序计数器、状态控制器。

本设计中借助MAX+PLUSⅡ软件平台对各模块进行时序仿真，并最终给出了指令执行的仿真波形，验证了CPU的功能。

设计仿真结果表明，该8位RISC-CPU能够完成既定的任务指标，而且在运行效率上有一定程度改善。

关键词：RISC-CPU、VHDL、MAX+PLUSⅡ、IP软核、时序仿真AbstractRISC reduced instruction set computer that (Reduced Instruction Set Computer) acronym. RISC-CPU and CPU in general compared to instruction by simplifying the structure of the computer is more simple and reasonable, thereby increasing processing speed. In this paper, RISC-CPU architecture is analyzed, and by using the VHDL language, I designed an 8-bit RISC-CPU IP soft core.RISC-CPU is based on 8 modules: clock generator, instruction register, accumulator, arithmetic logic unit, data output controller, address multiplexer, program counter, state controller. In the design, each module are timing simulated on MAX+PLUSⅡ software platform, and finally the simulated waveform of instruction execution that verifies the CPU features is given.Design and simulation results show that the 8-bit RISC-CPU can complete the tasks, and also has a certain degree of improvement on operational efficiency. Keywords: RISC-CPU, VHDL, MAX+PLUSⅡ, IP soft core, Timing Simulation目录摘要 (I)ABSTRACT（英文摘要） (II)目录 ............................................................................................................................................. I II 第一章引言 .. (1)1.1课题背景与发展现状 (1)1.1.1课题背景 (1)1.1.2RISC-CPU的发展现状 (1)1.2RISC-CPU优势与现实意义 (1)1.2.1RISC-CPU具备的优势 (1)1.2.2本课题的现实意义 (2)1.3本设计的主要内容 (2)第二章RISC-CPU的架构设计 (3)2.1RISC-CPU基本架构 (3)2.2RISC-CPU模块的划分 (4)第三章八位RISC-CPU各模块设计与仿真 (6)3.1时钟发生器 (6)3.2指令寄存器 (7)3.3累加器 (10)3.4算术逻辑单元 (11)3.5数据输出控制器 (13)3.6地址多路器 (14)3.7程序计数器 (15)3.8状态控制器 (17)第四章RISC-CPU的综合及操作时序 (25)4.1RISC-CPU各模块综合 (25)4.2CPU复位启动操作时序 (29)结论 (30)参考文献 (31)致谢 (32)第一章引言1.1 题背景与发展现状1.1.1 课题背景CPU是Central Processing Unit——中央处理器的缩写，它是计算机中最重要的一个部分。

ASIC实验报告(8位CPU的设计)

ASIC设计实验报告学院：电子工程学院学号：2014*******姓名：***指导老师：***2014年11月13日一、实验目的：通过对ASIC实验课的学习，应当学会以下几点：1.熟悉Linux操作系统的应用环境，基本命令行的应用，以及对vi编辑器熟练应用。

2.熟练掌握Verilog编程语言，包括基本组合逻辑电路的实现方法，基本时序逻辑电路的实现方法，怎样使用预定义的库文件，利用always块实现组合逻辑电路的方法已经着重了解assign与always 两种组合逻辑电路实现方法之间的区别，深入了解阻塞赋值与非阻塞赋值的概念以及应用的差别，有限状态机（FSM）实现复杂时序逻辑的方法，以及学会在Linux 系统环境当中应用Synopsys工具VCS进行仿真。

3.熟悉电路设计当中的层次化、结构化的设计方法。

4.熟悉CPU当中有哪些模块组成，模块之间的关系，以及其基本的工作原理。

5.学会利用汇编语言设计程序，注意代码规范性要求。

二、实验要求：按照实验指导书上的要求即：CPU各个模块的Verilog语言代码的编写、编译及仿真正确，并在规定的时间内完成。

要求对CPU进行语言级系统仿真结果正确之后，利用该实验当中采用的八个汇编关键字，编写一个能够实现某种功能的小程序。

然后对其中的控制器电路进行综合，并检查Timing 和Power,进行门级仿真。

三、实验内容：设计一个8位RISC_CPU 系统。

（RISC: Reduced Instruction Set Computer）,它是一种八十年代才出现的CPU，与一般的CPU相比，不仅只是简化了指令系统，而且通过简化指令系统使计算机的结构更加简单合理，从而提高了运算速度。

从实现的方法上，它的时序控制信号部件使用了硬布线逻辑，而不是采用微程序控制方式，故产生控制序列的速度要快的多，因为省去了读取微指令的时间。

此CPU所具有的功能有：（1）取指令：当程序已在存储器中时，首先根据程序入口地址取出一条程序，为此要发出指令地址及控制信号。

综合实验：8位CPU设计与实现

设计思路
◦ 在设计时，可以先考虑比较粗的结构 ◦ 然后再逐渐细化 ◦ 例子说明
串行指令CPU整体结构图
CLK FLAG RegSel<寄存器选择>
SelSrc SelOpr SelDst
<数据运算 ,传送 >
控制器
运算器( 含寄存器堆)
SCI <进位 > SST <设置状态 > SA ,SB <寄存器选择 >
王春桃

回顾冯· 诺依曼CPU结构及工作原理 16位实验CPU的设计与实现将16位实验CPU的改造成8位的实验CPU 评分标准

存储器
输入
运算器
输出
控制器数据信号控制信号地址信号
2015/12/12
3
1. CPU的功能
取指令执行指令
操作控制、时间控制
◦ 指令控制（程序的顺序控制）
FLAG ALU输出 AIsel <控制AR,IR接收 > BusSel <选择总线数据来源>
AR(地址寄存器)
IR( 指令寄存器) 符号扩展
Bus
寄存器数据<调试用>
MUX
地址总线
wrMem <内存读写>
数据总线
/WR
（来自数据总线）
MEM_DATA (15...0)
送往地址总线
ADR (15...0)
◦ 因此，此时的控制信号集合为：
001
节拍
指令编码
Sci SST I7I6 00 11 00
I5I4I3
000Βιβλιοθήκη I2I1I0000
/WR REC

8位逻辑计算机设计

3）指令种类和数量
4）内部寄存器的种类和数量
助记符
机器码1
机器码2
注释
_FETCH
00
00000
取指令
寄存器R？的值加到A上
图1.0 8位微型计算机开发设计过程
图1.1逻辑框图
表1.0功能设计
模块名称
模块功能
时钟发生器CLKGEN
产生一系列时钟信号，送往CPU其他部件
指令寄存器IR
寄存指令
累加器ACCUM
存放当前的运算结果
算术逻辑运算单元ALU
实现基本运算和操作
数据控制单元DATACTL
控制累加器数据输出
地址多路器ADDR
选择输出的地址是程序地址计数地址还是数据端口
程序计数器PC
提供指令地址
状态机MACHБайду номын сангаасNE
CPU控制核心，产生一系列控制信号，控制某些部件的启动或停止
对系统所需硬件做出初步的估计和选择
1.0对外围设备要求不高。只考虑现实、键盘、和串行口通信
2.0微处理器的考虑因素：
1）字长8位
2）寻址范围和寻址方式

VHDL_8位CPU设计_包含程序

实用文档Computer Organization and ArchitectureCourse DesignThe Experiment ReportOfCPUI . PurposeThe purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need consider the following items: Read/Write Registers, Read/Write Memory and Execute the instructions.At least four parts constitute a simple CPU: the control unit, the internal registers, the ALU and instruction set, which are the main aspects of our project design and will be studied.II . Instruction SetSingle-address instruction format is used in our simple CPU design. The instruction word contains two sections: the operation code (opcode), which defines the function of instructions (addition, subtraction, logic operations, etc.); the address part, in most instructions, the address part contains the memory location of the datum to be operated, we called it direct addressing. In some instructions, the address part is the operand, which is called immediate addressing.For simplicity, the size of memory is 256× 16 in the computer. The instruction word has 16 bits. The opcode part has 8 bits and address part has 8 bits. The instructionFigure 1 the instruction formatThe opcode of the relevant instructions are listed in Table 1.In Table 1, the notation [x] represents the contents of the location x in the memory. For example, the instruction word (03B916) means that the CPU adds word at location B916 in memory into the accumulator (ACC); the instruction word (050716) means if the sign bit of the ACC (ACC [15]) is 0, the CPU will use the address part of the instruction as the address of next instruction, if the sign bit is 1, the CPU will increase the program counter (PC) and use its content as the address of the next instruction.Table 1 List ofCalculate the sum of all integers from 1 to 100.(1), programming with C language:sum=0;temp=100;loop :sum=sum+temp;temp=temp-1;if temp>=0 goto loop;end(2), Assume in the RAM_DQ:sum is stored at location A4,temp is stored at location A3,the contents of location A0 is 0,the contents of location A1 is 1,the contents of location A2 is 10010=6416.We can translate the above C language program with the instructions listed in Table 1 into the instruction program as shown in Table 2.Table 2 Example of a program to sum from 1 to 100III. Internal Registers and MemoryMAR (Memory Address Register)MAR contains the memory location of the word to be read from the memory or written into the memory. Here, READ operation is denoted as the CPU reads from memory, and WRITE operation is denoted as the CPU writes to memory. In our design, MAR has 8 bits to access one of 256 addresses of the memory.MBR (Memory Buffer Register)MBR contains the value to be stored in memory or the last value read from memory. MBR is connected to the address lines of the system bus. In our design, MBR has 16 Bits.PC (Program Counter)PC keeps track of the instructions to be used in the program. In our design, PC has 8 bits.IR (Instruction Register)IR contains the opcode part of an instruction. In our design, IR has 8 bits.BR (Buffer Register)BR is used as an input of ALU, it holds other operand for ALU. In our design, BR has16 bits.LPM_RAM_DQLPM_RAM_DQ is a RAM with separate input and output ports. It works as a memory, and its size is 256×16. Although it’s not an internal register of CPU, we need it to simulate and test the performance of CPU.LPM_ROMLPM_ROM is a ROM with one address input port and one data output port, and its size of data is 32bits which contains control signals to execute micro-operations.IV.ALUALU (Arithmetic Logic Unit) is a calculation unit which accomplishes basic arithmetic and logic operations. In our design, some operations must be supported which are listed as follows:Table 3 ALU OperationsV. Micro-programmed Control UnitIn the Microprogrammed control, the microprogram consists of some microinstruction and the microprogram is stored in control memory that generates all the control signals required to execute the instruction set correctly. The microinstruction contains some micro-operations which are executed at the same time.Figure 2 shows the key elements of such an implementation.The set of microinstructions is stored in the control memory. The control address register contains the address of the next microinstructions to be read. When a microinstruction is read from the control memory, it is transferred to a control buffer register. The register connects to the control lines emanating from the control unit. Thus, reading a microinstruction from the control memory is the same as executing that microinstruction. The third element shown in the figure is a sequencing unit that loads the control address register and issues a read command.Figure 2 Control Unit Micro-architecture(I)Total control signals for instructions are listed as follows:Table 4 Control signals for the micro-operationsfollows:0 : 00810000; R←1, CAR←CAR+11 : 00A00000; OP←MBR[15..8],CAR←CAR+12 : 02000000; CAR←CAR+OP3 : 01000014; CAR←14H4 : 01000019; CAR←19H5 : 0100001E; CAR←1EH6 : 01000023; CAR←23H7 : 01000041; CAR←41H8 : 01000028; CAR←28H9 : 0100002D; CAR←2DHa : 01000032; CAR←32Hb : 01000037; CAR←37Hc : 0100003C; CAR←3CHd : 01000046; CAR←46He : 0100004B; CAR←4Hf : 00000000;………14 : 00840000; MAR←MBR[7..0], CAR←CAR+1 ------STORE15 : 00920200; MBR←ACC, PC←PC+1,W←1,CAR←CAR+116 : 04080000; CAR←019 : 00840000; MAR←MBR[7..0], CAR←CAR+1 ------LOAD1a : 00810A00; PC←PC+1,R←1,ACC←0,CAR←CAR+11b : 00C03000; BR←MBR,ACC←ACC+BR, CAR←CAR+11c : 04080000; CAR←01d : 00000000;1e : 00840000; MAR←MBR[7..0], CAR←CAR+1 ----------ADD1f : 00810200; PC←PC+1,R←1,CAR←CAR+120 : 00C03000; BR←MBR,ACC←ACC+BR, CAR←CAR+121 : 04080000; CAR←022 : 00000000;23 : 00840000; MAR←MBR[7..0], CAR←CAR+1 ----------SUB24 : 00810200; PC←PC+1,R←1,CAR←CAR+125 : 00C04000; BR←MBR,ACC←ACC-BR, CAR←CAR+126 : 04080000; CAR←027 : 00000000;28 : 00840000; MAR←MBR[7..0], CAR←CAR+1 ---------AND29 : 00810200; PC←PC+1,R←1,CAR←CAR+12a : 00C06000; BR←MBR,ACC←ACC AND BR,CAR←CAR+12b : 04080000; CAR←02c : 00000000;2d : 00840000; MAR←MBR[7..0], CAR←CAR+1 ---------OR2e : 00810200; PC←PC+1,R←1,CAR←CAR+12f : 00C07000; BR←MBR,ACC←ACC OR BR, CAR←CAR+130 : 04080000; CAR←031 : 00000000;32 : 00840000; MAR←MBR[7..0], CAR←CAR+1 ----------NOT33 : 00808200; PC←PC+1, ACC←NOT ACC,CAR←CAR+134 : 04080000; CAR←035 : 00000000;36 : 00000000;37 : 00840000; MAR←MBR[7..0], CAR←CAR+1 ----------SHIFTR38 : 08092000; PC←PC+1, ACC←SHIFT ACC to Right 1 bit,CAR←CAR+139 : 04080000; CAR←03a : 00000000;3b : 00000000;3c : 00840000; MAR←MBR[7..0], CAR←CAR+1 -----------SHIFTL3d : 0080A200; PC←PC+1, ACC←SHIFT ACC to Left 1 bit,CAR←CAR+1 3e : 04080000; CAR←03f : 00000000;40 : 00000000;41 : 00840000; MAR←MBR[7..0], CAR←CAR+1 -----------JMPGEZ42 : 00805000; CAR←CAR+1,43 : 04080000; CAR←046 : 00840000; MAR←MBR[7..0], CAR←CAR+1 ------------MPY47 : 00810200; PC←PC+1,R←1,CAR←CAR+148 : 00C0B000; BR←MBR,ACC←ACC*BR, CAR←CAR+149 : 04080000; CAR←04a : 00000000;4b : 0100004B; CAR←4BH ------------------------------HALT 4c : 00000000;(III)The simulation waveforms of some operates1, load, add, store, halt (22+10)The contents in RAM:0 : 022A; Load 2A1 : 032B; ADD 2B2 : 012C; Store 2C3 : 0C00; Halt2a : 0016;2b : 000A;The content in RAM addressed of 2b is 0020(H).The waveform of the operate:2, load, SUB, store, halt (22-10)The contents in RAM:0 : 022A; Load 2A1 : 042B; SUB 2B2 : 012C; Store 2C3 : 0C00; Halt2a : 0016;2b : 000A;The content in RAM addressed of 2c is 000C(H).The waveform of the operate:3, load, mpy, add, store, halt (13*10+22)The contents in RAM:0 : 022A; Load 2A1 : 0B2B; MPY 2B2 : 032C; ADD 2C3 : 012D; Store 2D4 : 0C00; Halt2a : 000D;2b : 000A;2c : 0016;The content in RAM addressed of 2d is 0098(H). The waveform of the operate:4, S um from 1 to 100The contents in RAM are shown in table2.The content in RAM addressed of A4 is 13BA(H).The waveform of the operate:The clock cycle of CAR is 400 ns.From the waveform, it takes 2.314ms to execute the operate. So the number of the executing cycles is 2.134/0.0004=5335.VI. Appendix:(I)The GDF of CPU:(II) The code of the CPU program:1, MBR (Memory Buffer Register)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity MBR isport( clk, reset, MBR_OPc, ACC_MBRc,R,W:in std_logic;ACC_MBR :in std_logic_vector(15 downto 0);RAM_MBR :in std_logic_vector(15 downto 0);MBR_RAM :out std_logic_vector(15 downto 0);MBR_BR :out std_logic_vector(15 downto 0);MBR_OP :out std_logic_vector(7 downto 0);MBR_MAR :out std_logic_vector(7 downto 0);MBR_PC :out std_logic_vector(7 downto 0));end MBR;architecture behave of MBR isbeginprocess(clk)variable temp:std_logic_vector(15 downto 0);beginif(clk'event and clk='0')thenif reset='1' thenif ACC_MBRc='1' then temp:=ACC_MBR; end if;if R='1' then MBR_BR<=RAM_MBR; end if;if W='1' then MBR_RAM<=temp; end if;MBR_MAR<=RAM_MBR(7 downto 0);MBR_PC<=RAM_MBR(7 downto 0);if MBR_OPc='1' then MBR_OP<=RAM_MBR(15 downto 8); end if; else MBR_BR<=x"0000";MBR_MAR<="00000000";MBR_OP<="00000000";MBR_PC<="00000000";end if;end if;end process;end behave;2, BR (Buffer Register)library ieee;use ieee.std_logic_1164.all;entity BR isport( MBR_BRc:in std_logic;MBR_BR:in std_logic_vector(15 downto 0);BRout:out std_logic_vector(15 downto 0));end BR;architecture behave of BR isbeginprocessbeginif MBR_BRc='1' then BRout<=MBR_BR; end if;end process;end behave;3, MAR (Memory Address Register)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity MAR isport( clk,PC_MARc,MBR_MARc:in std_logic;PC,MBR_MAR:in std_logic_vector(7 downto 0);MARout:out std_logic_vector(7 downto 0));end MAR;architecture behave of MAR isbeginprocess(clk)beginif(clk'event and clk='1')thenif PC_MARc='1' then MARout<=PC; end if; if MBR_MARc='1' then MARout<=MBR_MAR; end if;end if;end process;end behave;4, PC (Program Counter)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity PC isport( clk,PCjmp,PCc1,PCinc,PCc3,reset:in std_logic;CONTRalu :in std_logic_vector(3 downto 0);MBR_PC :in std_logic_vector(7 downto 0);PCout :buffer std_logic_vector(7 downto 0));end PC;architecture behave of PC isbeginprocess(clk)beginif(clk'event and clk='0')thenif reset='1' thenif CONTRalu="0101" thenif PCjmp='1' then PCout<=MBR_PC;elsif PCjmp='0' then PCout<=PCout+1;end if;end if;if PCc1='1' then PCout<="00000000"; end if; if PCinc='1' then PCout<=PCout+1; end if; if PCc3='1' then PCout<=MBR_PC; end if; else PCout<="00000000";end if;end if;end process;end behave;5, IR (Instruction Register)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity IR isport( opcode :in std_logic_vector(7 downto 0);IRout :out std_logic_vector(7 downto 0));end IR;architecture behave of IR isbeginIRout<=opcode;end behave;6, CAR (Control Address Register)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity CAR isport( clk,reset :in std_logic;CARc :in std_logic_vector(3 downto 0);CAR,OP :in std_logic_vector(7 downto 0);CARout:buffer std_logic_vector(7 downto 0));end CAR;architecture behave of CAR isbeginprocess(clk)beginif(clk'event and clk='1')thenif reset='1' thenif CARc="1000" then CARout<="00000000"; end if; if CARc="0100" then CARout<=OP+CARout; end if; if CARc="0010" then CARout<=CAR; end if; if CARc="0001" then CARout<=CARout+1; end if; else CARout<="00000000";end if;end if;end process;end behave;7, CONTRALR (Control Buffer Register)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity CONTROLR isport(control :in std_logic_vector(31 downto 0); R,W, RW, PCc1,PCinc,PCc3:out std_logic;ACCclear,MBR_MARc,PC_MARc:out std_logic; ACC_MBRc,MBR_OPc,MBR_BRc:out std_logic;CONTRout:out std_logic_vector(3 downto 0); CARc :out std_logic_vector(3 downto 0); CAR :out std_logic_vector(7 downto 0)); end CONTROLR;architecture behave of CONTROLR isbeginprocessbeginCAR<=control(7 downto 0);PCc1<=control(8);PCinc<=control(9);PCc3<=control(10);ACCclear<=control(11);CONTRout<=control(15 downto 12);R<=control(16);W<=control(17);MBR_MARc<=control(18);PC_MARc<=control(19);ACC_MBRc<=control(20);MBR_OPc<=control(21);MBR_BRc<=control(22);CARc<=control(26 downto 23);RW<=control(17);end process;end behave;8, ALU (Arithmetic Logic Unit)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ALU isport( clk,reset,ACCclear:in std_logic;aluCONTR :in std_logic_vector(3 downto 0);BR :in std_logic_vector(15 downto 0);PCjmp :out std_logic;ACC :buffer std_logic_vector(15 downto 0));end ALU;architecture behave of ALU isbeginprocess(clk)beginif(clk'event and clk='0')thenif reset='0' then ACC<=x"0000";elseif ACCclear='1' then ACC<=x"0000"; end if;if aluCONTR="0011" then ACC<=BR+ACC; end if; --ADD if aluCONTR="0100" then ACC<=ACC-BR; end if; --SUB if aluCONTR="0110" then ACC<=ACC and BR; end if; --AND if aluCONTR="0111" then ACC<=ACC or BR; end if; --OR if aluCONTR="1000" then ACC<=not ACC; end if; --NOT if aluCONTR="1001" then --SRR ACC(14 downto 0)<=ACC(15 downto 1); ACC(15)<='0';end if;if aluCONTR="1010" then --SRL ACC(15 downto 1)<=ACC(14 downto 0); ACC(0)<='0';end if;if aluCONTR="1011" then ACC<=ACC*BR; end if; --MPY end if;end if;if ACC>0 then PCjmp<='1';else PCjmp<='0';end if;end process;end behave;。

8位CPU的设计

8位CPU的设计一、设计的任务与要求计算机的核心部件cpu通常包含运算器和控制器两大部分。

组成cpu的基本部件有运算部件，寄存器组，微命令产生部件和时序系统等。

这些部件通过cpu内部的总线连接起来，实现它们之间的信息交换。

1.设计目的（1）．深入细致认知基本模型计算机的功能、共同组成科学知识；（2）．深入细致自学计算机各类典型指令的继续执行流程；（3）．自学微程序控制器的设计过程和有关技术，掌控lpm_rom的布局方法。

（4）．在掌控部件单元电路实验的基础上，进一步将单元电路共同组成系统，结构一台基本模型计算机。

（5）．定义五条机器指令，并编写相应的微程序，上机调试，掌握计算机整机概念。

掌握微程序的设计方法，学会编写二进制微指令代码表。

（6）．通过熟识较完整的计算机的设计，全面介绍并掌控微程序控制方式计算机的设计方法。

2.设计原理在部件实验过程中，各部件单元的掌控信号就是人为演示产生的，而本实验将能够在微过程控制下自动产生各部件单元掌控信号，同时实现特定的功能。

实验中，计算机数据通路的掌控将由微过程控制器去顺利完成，cpu从内存中抽出一条机器指令至指令继续执行完结的一个指令周期，全部由微指令共同组成的序列去顺利完成，即为一条机器指令对应一个微程序。

11该cpu主要由算术逻辑单元alu，数据存贮寄存器dr1、dr2，数据寄存器r0～r2，程序计数器pc，地址寄存器ar,程序/数据存储器memoray，指令寄存器ir，微控制器uc，输出单元input和输入单元output所共同组成。

图中虚线框内部分包含运算器、控制器、程序存储器、数据存储器和微程序存储器等，量测时，它们都可以在单片fpga中同时实现。

虚线框外部分主要就是输出/输入装置，包含键盘、数码管、lcd显示器等，用作向cpu输出数据，或cpu向外输入数据，以及观测cpu内部工作情况及运算结果。

二、单元电路设计1、运算部件运算部件的任务就是对操作数展开加工处置。

专题4 精简8位CPU电路设计

8位移位寄存器的电路设计与版图实现要点

8bitCPU

8位骨灰级CPU电路图

8位CPU的设计与实现

8位CPU的设计与实现

专题4-精简8位CPU电路设计

8位CPU的设计-VHDL语言-综合性实验实验报告

CPU设计实践教程8-8位7段数码管控制的设计

一个简单的8位处理器完整设计过程及verilog代码

VHDL-8位CPU设计-包含程序

基于VHDL语言的8位RISC-CPU的设计 终稿

ASIC实验报告(8位CPU的设计)

综合实验：8位CPU设计与实现

8位逻辑计算机设计

VHDL_8位CPU设计_包含程序

8位CPU的设计

基于VHDL语言的8位RISC-CPU的设计终稿