基于STC89C52单片机的太阳能智能充电系统外文翻译毕业论文
AT89S52单片机应用中英文翻译
本科毕业设计（论文）AT89S52单片机应用中英文翻译专业名称：电气工程及其自动化年级班级：学生姓名：指导老师：二O一二年六月九日AT89S52 MCU ApplicationsFunction Characteristic DescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.Pin DescriptionVCC ：Supply voltage.GND ：Ground.Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. External pull-ups are required during program verification.Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 outputbuffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-ing table 1. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification.Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that areexternally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52, as shown in the fol-lowing table 2.RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/PROG：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-ing each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSEN：Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during eachaccess to exter-nal data memory.EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2：Output from the inverting oscillator amplifier.Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data. Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #data. Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.Watchdog TimerThe WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-flows, it will drive an output RESET HIGH pulse at the RST pin.In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information o n the timers’ operation, please click on the document link below:/dyn/resources/prod_documents/DOC4316.PDFTimer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 6-1. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscil-lator frequency.In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-sponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.InterruptsThe AT89S52 has a total of six interrupt vectors: two external interrupts (INT0and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that bit position IE.6 is unimplemented. User software should not write a 1 to this bit position, since it may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven,. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clock-ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Power-down ModeIn the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be heldactive long enough to allow the oscillator to restart and stabilize.Idle ModIn idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions regis-ters remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.AT89S52单片机应用功能特征描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。
at89c52单片机简介中英文对照外文翻译文献
at89c52单片机简介中英文对照外文翻译文献中英文资料对照外文翻译A T89C52 Single-chip microprocessor introductionSelection of Single-chip microprocessor1. Development of Single-chip microprocessorThe main component part of Single-chip microprocessor as a result of by such centralize to be living to obtain on the chip，In immediate future middle processor CPU。
Storage RAM immediately﹑memoy read ROM﹑Interrupt system、Timer /'s counter along with I/O's rim electric circuit awaits the main microcomputer section，The lumping is living on the chip。
Although the Single-chip microprocessor r is only a chip，Yet through makes up and the meritorous service be able to on sees，It had haveed the calculating machine system property，calling it for this reason act as Single-chip microprocessor r minisize calculating machine SCMS and abbreviate the Single-chip microprocessor。
STC89C52处理芯片-毕业论文外文翻译
中文翻译STC89C52处理芯片电气工程的研究和解决方案中心（ceers）艾哈迈德为吉.波特首要性能：与MCS-51单片机产物兼容、8K字节在系统可编程视频存储器、1000次擦拭周期，全静态操作：0Hz~33Hz、三级加密程序存储器，32个可编程I/O接口线、三个16位定时器（计数器），八个中断源、低功能耗空闲和掉电模式、掉电后间断可唤醒，看门狗定时器、双数值指针，掉电标示符。
关键词：单片机，UART串行通道，掉电标示符等前言可以说，二十世纪跨越了三个“点”的时代，即电气时代，电子时代和现已进入的电脑时代。
不过，这种电脑，通常指的是个人计算机，简称PC机。
还有就是把智能赋予各种机械的单片机（亦称微控制器）。
顾名思义，这种计算机的最小系统只用了一片集成电路，即可进行简单的运算可控制。
因为它体积小，通常都是藏在被控机械的内部里面。
它在整个装置中，起着有如人类头脑的作用，他出了毛病，整个装置就会瘫痪。
现在，单片机的种类和适用领域已经十分广泛，如智能仪表、实施工控、通讯设备、导航系统、家用电器等。
各种产品一旦用上了单片机，就你能起到产品升级换代的功效，常在产品名称前冠以形容词——“智能型”，如智能洗衣机等。
接下来就是关于国产STC89C52单片机的一些基本参数。
功能特性描述:STC89C52单片机是一种低功耗、高性能CMOS8位微控制器，具有8K在系统可编程视频播放存贮器使用高密度非易失性存储器技术制造，与工业80C51 产物指令和引脚完全兼容。
片上反射速度允许程序存储器在系统可编程，也适用于常规的程序编写器。
在其单芯片上，拥有灵敏小巧的八位中央处理器和在线系统可编程反射，这些使用上STC89C52微控制器为众多嵌入式的控制应用系统提供高度矫捷的、更加有用的解决方案。
STC89C52微控制器具有以下的标准功效：8K字节的反射速度，256字节的随机存取储存器，32位I/O串口线，看门狗定时器，2个数值指针，三个16为定时器、计数器，一个6向量2级间断结构，片内晶振及钟表电路。
plc单片机 毕业论文文献翻译 中英文对照
外文翻译：The monolithic In order to prevent without authorization the visit or the copy monolithic integrated circuit machine in the procedure, the majority of monolithic integrated circuits all has the encryption to lock the localization or the encryption byte, by protects the internal procedure. If in programming time encrypts locks the localization to enable (locking), is unable with the ordinary programming directly reading in the monolithic integrated circuit the procedure, this is the so-called copy protection or says the fixed function. In fact, such protective measures are very frail, is very easily explained. The monolithic integrated circuit aggressor with the aid of the special purpose equipment or the self-made equipment, using the monolithic integrated circuit chip design in loophole or the software flaw, through the many kinds of technical method, may withdraw the essential information from the chip, gains in the monolithic integrated circuit the procedure. Therefore, has the newest technology extremely as electronic products project engineer which the essential understanding current monolithic integrated circuit attacks, achieves knows oneself and the other side, knows fairly well, can effectively prevent oneself spends the product which the massive moneys and the time laboriously designs the matter occurrence which is counterfeited by a others night between.monolithic integrated circuits attacks technology：At present, attacks the monolithic integrated circuit mainly to have four kind of technologies, respectively is:This technical usual use processor correspondence connection and in the use agreement, the encryption algorithm or these algorithm security loophole carries on the attack. The software attack obtains the success a case in point is to early A T M E L A the T 89 C series monolithic integrated circuit attack. The aggressor has used in this series monolithic integrated circuit cleaning operation succession design loophole, uses from arranges the procedure to lock the localization after the cleaning encryption, stops the next step of cleaning internal program memory data the operation, thus makes to add the dense monolithic integrated circuit not to turn the encryption monolithic integrated circuit, then use programming read-out internal procedure.This technology usually monitors the processor by the high time resolution when the normal operation all power sources and the connection connection simulation characteristic, and through monitors its electromagnetic radiation characteristic to implement the attack. Because the monolithic integrated circuit is an active electronic device, when it carries out the different instruction, the corresponding mains input consumption also correspondingly changes. Like this analyzes and examines these changes through the use special electronic surveying instrument and mathematics statistical method, then gains in the monolithic integrated circuit the specific essential information.the mistake has the technology This technical use exceptionally working condition causes the processor to make a mistake, then provides the extra visit to carry on the attack. Uses the most widespread mistake to have the attack method including the voltage impact and the clock impact. The low voltage and the high voltage attack may usefor to forbid the protection circuit work or to fortected the information. The power source and the clock transient state jump may affect the single scroll instruction in certain processors the decoding and the ece the processor to carry out the misoperation. Perhaps the clock transient state jump can reposition the protection circuit but not to be able to destroy is proxecution.This technology is the direct exposed chip interior segment, then the observation, holds controls, disturbs the monolithic integrated circuit by to achieve the attack goal.In order to facilitate in order to, the people divide into above four kind of attacks technology two kinds, a kind is the invasion attack (physical attack), this kind of attack needs to destroy the seal, then with the aid of the semiconductor test facility, the microscope and the micro locator, several hours even several week time can complete on the special laboratory flower. All micro probes technology all belongs to the invasion attack. Moreover three methods belong to the non- invasion attack, the monolithic integrated circuit which attacks cannot by the physical damage. In certain situation non- invasion attacks is specially dangerous, this is because the non- invasion attack needs the equipment usually to be possible the self-restraint and the promotion, therefore is extremely inexpensive.The majority of non- invasions attack needs the aggressor to have the good processor knowledge and the software knowledge. Is opposite with it, the invasion probe attack then does not need too many initial knowledge,moreover usually may use the one whole set similar technology to cope with the width scope the product. Therefore, the attack often starts to the monolithic integrated circuit from the invasion reverse engineering, the accumulation experience is helpful to the development more inexpensive and the fast non- invasion attack technology.Last step will be seeks the protection melt silk the position and protects the melt silk to expose under the ultraviolet ray. With enlargement factor at least 100 time of microscopes, inputs the foot from the programming voltage the segment to track generally, seeks the protection melt silk.This technical use exceptionally working condition causes the processor to make a mistake, then provides the extra visit to carry on the attack. Uses the most widespread mistake to have the attack method including the voltage impact and the clock impact. The low voltage and the high voltage attack may use for to forbid the protection circuit work or to force the processor to carry out the misoperation. Perhaps the clock transient state jump can reposition the protection circuit but not to be able to destroy is protected the information. The power source and the clock transient state jump may affect the single scroll instruction in certain processors the decoding and the execution.(4) probe technologyThis technology is the direct exposed chip interior segment, then the observation, holds controls, disturbs the monolithic integrated circuit by to achieve the attack goal.In order to facilitate in order to, the people divide into above four kindof attacks technology two kinds, a kind is the invasion attack (physical attack), this kind of attack needs to destroy the seal, then with the aid of the semiconductor test facility, the microscope and the micro locator, several hours even several week time can complete on the special laboratory flower. All micro probes technology all belongs to the invasion attack. Moreover three methods belong to the non- invasion attack, the monolithic integrated circuit which attacks cannot by the physical damage. In certain situation non- invasion attacks is specially dangerous, this is because the non- invasion attack needs the equipment usually to be possible the self-restraint and the promotion, therefore is extremely inexpensive.The majority of non- invasions attack needs the aggressor to have the good processor knowledge and the software knowledge. Is opposite with it, the invasion probe attack then does not need too many initial knowledge,moreover usually may use the one whole set similar technology to cope with the width scope the product. Therefore, the attack often starts to the monolithic integrated circuit from the invasion reverse engineering, the accumulation experience is helpful to the development more inexpensive and the fast non- invasion attack technology.3 invasions attacks general process：The invasion attack first step uncovers the chip seal. Some two methods may achieve this goal: The first kind is dissolves the chip seal completely, the exposed metal segment. The second kind is only moves above the silicon nucleus plastic seal. The first method needs the chip to tests on the jig, with the aid of Taiwan to operate. The second method except needs to have the aggressor certain knowledge and Wants outside skill, but also needs individual wisdom and the patience, but operates relatively quite is convenient.Above the chip plastic may use the knife to open, around the chip epoxy resin may use the aqua fortis perish. The hot aqua fortis can dissolve the chip seal but not to be able to affect the chip and the segment. This process carries on generally under the extremely dry condition, because the water existence possibly can corrode already the aluminum wire connection which exposes.Then first uses the acetone in the supersonic pond to clean this chip by except the remaining nitric acid, then cleans with the clear water by and is dry except the salinity. Not the supersonic pond, jumps over generally this step. In this kind of situation, the chip surface can a little dirty, but not too affects the ultraviolet ray to the chip operation effect.Last step will be seeks the protection melt silk the position and protects the melt silk to expose under the ultraviolet ray. With enlargement factor at least 100 time of microscopes, inputs the foot from the programming voltage the segment to track generally, seeks the protection melt silk.If does not have the microscope, then uses the chip different partially exposes to the ultraviolet ray under and the observed result way carries on the simple search. When operation applies not the opaque slip of paper cover chipby to protect the program memory not by the ultraviolet ray cleaning. Will protect the melt silk to expose in the ultraviolet ray next 5 ~ 10 minutes can broken the protection position protective function, afterwards, will use the simple programming to be possible the direct readout program memory content.Regarding used the protective layer to protect E E P R O the M unit the monolithic integrated circuit to say that, the use ultraviolet ray repositioned the protection circuit is not feasible. Regarding this kind of type monolithic integrated circuit, uses the micro probe technology reading the memory content generally. Opens after the chip seal, puts in the chip under the microscope to be able very easy finding中文翻译单片机为了防止未经授权访问或拷贝单片机的机内程序，大部分单片机都带有加密锁定位或者加密字节，以保护片内程序。
STC89C52处理芯片——单片机类毕业设计外文翻译、中英文翻译
STC89C52处理芯片——单片机类毕业设计外文翻译、中英文翻译外文资料翻译STC89C52 processing chip Prime features: With MCS - 51 SCM product compatibility, 8K bytes in the system programmable Flash memory, 1000 times CaXie cycle, the static operation: 0Hz ~ 33Hz, triple encryption program memory, 32 programmed I/O port, three 16 timer/counter, the eight uninterrupted dual-career UART serial passage, low power consumption, leisure and fall after fall electric power mode can be awakened and continuous watchdog timer and double-number pointer, power identifier. Efficacy: characteristics STC89C52 is one kind of low power consumption, high CMOS8 bit micro-controller, 8K in system programmable Flash memory. Use high-density nonvolatile storage technology, and industrial 80C51 product instruction and pin fully compatible. The Flash memory chips allows programs in the system, also suitable for programmable conventional programming. In a single chip, have clever 8 bits CPU and online system programmable Flash, increase STC89C52 for many embedded control system to provide high vigorous application and useful solutions. STC89C52 has following standard efficacy: 8k byte Flash RAM, 256 bytes, 32 I/O port, the watchdog timer, two, three pointer numerical 16timer/counter, a 6 vector level 2 continuous structure, the serial port, working within crystals and horological circuit. In addition, 0Hz AT89S52 can drop to the static logic operation, support two software can choose power saving mode. Idle mode, the CPU to stop working, and allows the RAM, timer/counters, serial, continuous to work. Protection asana pattern, RAM content is survival, vibrators frozen, SCM, until all the work under a continuous or hardware reset. 8-bit microcontrollers 8K bytes in the system programmable Flash AT89S52 devices. Mouth: P0 P0 mouth is a two-way open drain I/O. As export, each can drive eight TTL logic level. For P0 port to write "1", foot as the high impedance input. When access to external programs and numerical memory, also known as low P0 mouth eight address/numerical reuse. In this mode, with the internal P0 resistor. In the flash when programming, also used for P0 mouth; absorb instruction bytes In the process, the output command byte calibration. When the program requires external, calibration on pull-up resistors. Mouth: P1 mouth P1 is an internal resistance of the eight two-way I/O buffers can drive, P1 output four TTL logic level. To write "1" P1 port, the internal resistance to port, can push as input mouth. When used as input, external and internal foot because of low resistance, will output current (IIL). In addition, P1.0 and P1.2 respectively timer/counter 2 external counting input (P1.0 / T2) and when the trigger editor/counter P1.1 input (2), specific T2EX/are shown below. In programming and calibration, flash P1mouth absorb eight address low byte. Efficacy: the foot. P1.0 T2 (timer/counter T2 external counting input), clock output P1.1 T2EX (timer/counter T2 capture/overloaded triggered signals and direction control), P1.5 MOSI (with) online system programming, P1.6 MISO (with) online system programming, P1.7 SCK (with) online system programming, Mouth: P2 P2 mouth is an internal resistance of the eight two-way I/O buffers and P2 output can drive four TTL logic level. To write "1" P2 port, the internal resistance to port, can push as input mouth. When used as input, external and internal foot because of low resistance, will output current (IIL). In the external program memory access or use 16bit external numerical memory address read (for example MOVX execution DPTR @), P2 mouth send out high 8 address. In this application, P2 mouth on the internal use strong pull send 1. In using 8-bit address (such as MOVX @ RI) access to external numerical memory, P2 mouth output P2 latches content. In programming and calibration, flash P2 mouth also absorb high eight address byte and some control signal. P3: a P3 mouth on the inside of the eight two-way pull-up resistors I/O buffers can drive, p2 output four TTL logic level. For P3 port to write "1", the internal resistance to port, can push as input mouth. When used as input, external and internal foot because of low resistance, will output current (IIL). P3 mouth AT89S52 special functions (also as the second efficacy), are shown below. In programming and calibration, flash also absorb some P3 mouth controlsignals. Port pin second efficacy: P3.0 RXD (serial input) P3.1 TXD (serial export), P3.2 INTO the discontinuous (0) P3.3 INT1 (1) the discontinuous P3.4 (time/counter TO 0) P3.5 T1 (1) time/counter, P3.6 WR (external numerical memory write for) P3.7 RD (external numerical memory read for) In addition, also absorb some used in mp3 mouth FLASH memory programming and calibration of program control signals. RST, reset input: when the vibrator, RST pin appeared two machine cycle above high level will be reset the chip. ALE/PROG - when access to external program memory or numerical memory, ALE (address latch allow) output pulses are used to latch address of low eight bytes. Normally, ALE with clock frequencies are 1/6 output pulse si。
基于单片机智能充电器的外文文献翻译--(英文+中文)
基于单片机智能充电器的外文文献翻译--（英文+中文）译文电池充电器集成电路的改进跟上移动手机功能快速增长的速度在全球无线连接的时代，几乎没有什么比让一个智能手机或移动互联网设备保持带电更重要了。
便携式和手持设备功能的扩展性不断提高成为电池充电器集成电路设计者的一个重大挑战。
高分辨率的屏幕和更大的储存能力并加上新的功能赋予电池，这就需要对电池充电器的技术要求，不仅要更有效率，同时要具有配电管理的能力。
通过优化电源消耗来延长电池的寿命是掌上型电源管理的驱动力。
但是当把手持的设备插入墙上，期望对他们进行充电时有有效地变化。
最新一代采用高效率开关设计的充电器会代替传统的线性充电器。
今天的客户仍旧需求更短的充电周期对其电池充电。
相比传统的线性充电器，采用开关充电器的好处，除了效率高之外，还有一个很大的优点是通过电源提供能够促进充电电流。
特别重要的是，当供电结束时接口处的电流可以实现被限制在小于。
更高的充电电USB500mA 流等于充电周期更短，这就满足了客户的期望。
当今有两种被大多数手持设备使用的电池充电器线性充电器和开关充电--- 器。
线性充电器有一段较长的历史。
他们通常提供了相对高效，简单的方式对便携设备充电，同时产生噪音极小且不需要很多的外部元器件。
但是，随着便携式设备变得更加复杂和添加新的功能层，他们就需要更大的电池容量。
由于功能损耗，线性充电器呈现出不足，这很容易知道，假如用户想要对设备充电，且在同一时间又使用。
同时使用设备和对其进行充电产生的热量会损坏系统或电池。
这将会导致不好的结果。
另一种选择是开关充电器，或者是开关模式电池充电器集成电路，它可以提供更高的电流水平，但却需要尽可能少的功率。
历史上，这些类型的集成电路经常存在一些噪音的问题。
此外，一些早期的几代开关模式的设备需要一些外部元件。
1然而，开关模式的电池拓扑结构的好处是显而易见的。
它们包括提高效率和降低功耗，以及快速的充电周期。
这些器件也都能够由高的输入电压进行充电，这就可以允许使用较低成本无管制的适配器。
基于单片机的太阳能自动对光跟踪系统_学士学位论文(设计)
成都学院（成都大学）学士学位论文（设计）学士学位论文（设计）基于单片机的太阳能电池板自动对光跟踪系统摘要：本文是以A T89C52单片机为核心，设计了一个太阳能电池板自动对光跟踪系统。
系统主要包括光敏传感器、模数转换部分、单片机微处理器、步进电机和电机的驱动电路等，传感器采用光敏二极管作为光-电转换器件，将三个完全相同的光敏二极管分别放置于电池板三个方向分别对光照强度采集，然后由光敏传感器电路将光照强度转换为电压信号，再由ADC0809将电压信号转换为数字信号送入单片机，最后单片机将数字信号进行对比控制电机转动。
该系统精度为4°，系统结构简单、操作方便、测量精度高、速度快。
关键词：太阳能自动跟踪；A/D转换；光敏二极管；单片机微处理器；步进电机Solar Panel Automatically Tracking System Based onMicrocontrollerAbstract: Solar Panel Automatically Tracking System is designed based on AT89C52 microcontroller in this paper.The system includes photosensitive sensor, A/D converter, SCM,stepping motor , drive circuit of motor and so on. Photodiode as a light sensor - power conversion devices, the three identical photodiodes were placed in three directions panels were collected on the light intensity, then the light intensity will be converted to V oltage signal by the light sensor circuit, V oltage signal is put into SCM by the ADC0809 to convert digital signals,the SCM compare digital signals with digital signals to control motor rotation. The system accuracy of 4 °, the system is simple , easy operation , high accuracy, high speed.Keywords：Automatic tracking solar ; A / D conversion; Photodiode ;SCM;Stepping motor目录第1章绪论 (1)1.1 课题背景 (1)1.1.1 能源现伏及发展 (1)1.1.2 我国太阳能资源 (1)1.1.3 目前太阳能的开发和利用 (1)1.1.4 太阳能的特点 (2)1.2 课题研究的目的 (2)1.3 课题研究的意义 (2)1.3.1 新环保能源 (2)1.3.2 提高太阳能的利用率 (3)1.4 太阳能光伏发电国内外的现状 (3)1.5 太阳能追踪系统国内外研究现状 (4)1.6 论文的研究内容 (4)1.7 论文结构 (5)第2章太阳能自动跟踪系统总体设计 (6)2.1 太阳运行的规律 (6)2.2 跟踪器机械执行部分 (6)2.2.1 立柱转动式要跟踪器 (6)2.2.2 陀螺仪式跟踪器 (7)2.2.3 齿圈转动式跟踪器 (7)2.3 太阳能跟踪设计 (9)2.3.1 常用太阳能跟踪方案 (9)2.3.2 太阳能跟踪方案的确定 (10)2.4 太阳能跟踪传感器的设计 (10)2.4.1 光线和影子的关系 (10)2.4.2 跟踪传感器的跟踪精度 (11)2.4.3 太阳跟踪方案的确定 (12)2.4.4 太阳光照强度的检测 (14)2.4.5 太阳能跟踪传感器的设计制作 (15)2.4.6 太阳能传感器电路设计 (19)第3章系统硬件设计 (21)3.1 太阳能自动跟踪控制 (21)3.2 电源 (21)3.3 信号采集电路 (22)3.4 控制器 (24)3.4.1 单片机简介 (24)3.4.2 单片机外围电路设计 (25)3.5 模数转换 (25)3.5.1 ADC0809说明 (26)3.6 步进电机及驱动 (28)3.6.1 驱动电路 (28)3.6.2 步进电机 (29)第4章系统软件设计 (32)4.1 A/D转换部分 (32)4.2 光敏二极管比较法 (33)4.3 系统流程图 (35)第5章总结 (37)5.1 结论 (37)5.2 展望 (37)致谢 (38)参考文献 (40)附录1 系统硬件电路图 (42)附录2 程序清单 (43)第1章绪论1.1 课题背景1.1.1 能源现伏及发展能源是人类社会赖以生存和发展的物质基础。
太阳能光伏系统蓄电池充电毕业论文中英文资料对照外文翻译文献综述
中英文资料对照外文翻译文献综述Design of a Lead-Acid Battery Charging and Protecting IC in Photovoltaic System1.IntroductionSolar energy as an inexhaustible, inexhaustible source of energy more and more attention. Solar power has become popular in many countries and regions, solar lighting has also been put into use in many cities in China. As a key part of the solar lighting, battery charging and protection is particularly important. Sealed maintenance-free lead-acid battery has a sealed, leak-free, pollution-free, maintenance-free, low-cost, reliable power supply during the entire life of the battery voltage is stable and no maintenance, the need for uninterrupted for the various types of has wide application in power electronic equipment, and portable instrumentation. Appropriate float voltage, in normal use (to prevent over-discharge, overcharge, over-current), maintenance-free lead-acid battery float life of up to 12 ~ 16 years float voltage deviation of 5% shorten the life of 1/2. Thus, the charge has a major impact on this type of battery life. Photovoltaic, battery does not need regular maintenance, the correct charge and reasonable protection, can effectively extend battery life. Charging and protection IC is the separation of the occupied area and the peripheral circuit complexity. Currently, the market has not yet real, charged with the protection function is integrated on a single chip. For this problem, design a set of battery charging and protection functions in one IC is very necessary.2.System design and considerationsThe system mainly includes two parts: the battery charger module and the protection module. Of great significance for the battery as standby power use of the occasion, It can ensure that the external power supply to the battery-powered, but also in the battery overcharge, over-current and an external power supply is disconnected the battery is to put the state to provide protection, the charge and protection rolled into one to make the circuit to simplify and reduce valuable product waste of resources. Figure 1 is a specific application of this Ic in the photovoltaic powergeneration system, but also the source of this design.Figure1 Photovoltaic circuit system block diagramMaintenance-free lead-acid battery life is usually the cycle life and float life factors affecting the life of the battery charge rate, discharge rate, and float voltage. Some manufacturers said that if the overcharge protection circuit, the charging rate can be achieved even more than 2C (C is the rated capacity of the battery), battery manufacturers recommend charging rate of C/20 ~ C/3. Battery voltage and temperature, the temperature is increased by 1 °C, single cell battery voltage drops 4 mV , negative temperature coefficient of -4 mV / ° C means that the battery float voltage. Ordinary charger for the best working condition at 25 °C; charge less than the ambient temperature of 0 °C; at 45 °C may shorten the battery life due to severe overcharge. To make the battery to extend the working life, have a certain understanding and analysis of the working status of the battery, in order to achieve the purpose of protection of the battery. Battery, there are four states: normal state, over-current state over the state of charge, over discharge state. However, due to the impact of the different discharge current over-capacity and lifetime of the battery is not the same, so the battery over discharge current detection should be treated separately. When the battery is charging the state a long time, would severely reduce the capacity of the battery and shorten battery life. When the battery is the time of discharge status exceeds the allotted time, the battery, the battery voltage is too low may not be able to recharge, making the battery life is lower.Based on the above, the charge on the life of maintenance-free lead-acid batteries have a significant impact, while the battery is always in good working condition, battery protection circuit must be able to detect the normal working condition of the battery and make the action the battery can never normal working state back to normal operation, in order to achieve the protection of the battery.3.Units modular design3.1The charging module Chip, charging module block diagram shown in Figure 2. The circuitry includes solar battery array Charge controller controller Discharge controller DC load accumulatorcurrent limiting, current sensing comparator, reference voltage source, under-voltage detection circuit, voltage sampling circuit and logic control circuit.Figure2 Charging module block diagramThe module contains a stand-alone limiting amplifier and voltage control circuit, it can control off-chip drive, 20 ~30 mA, provided by the drive output current can directly drive an external series of adjustment tube, so as to adjust the charger output voltage and current . V oltage and current detection comparator detects the battery charge status, and control the state of the input signal of the logic circuit. When the battery voltage or current is too low, the charge to start the comparator control the charging. Appliances into the trickle charge state when the cut-off of the drive, the comparator can output about 20 mA into the trickle charge current. Thus, when the battery short-circuit or reverse, the charger can only charge a small current, to avoid damage to the battery charging current is too large. This module constitutes a charging circuit charging process is divided into two charging status: high-current constant-current charge state, high-voltage charge status and low-voltage constant voltage floating state. The charging process from the constant current charging status, the constant charging current of the charger output in this state. And the charger continuously monitors the voltage across the battery pack, the battery power has been restored to 70% to 90% of the released capacity when the battery voltage reaches the switching voltage to charge conversion voltage Vsam charger moves to the state of charge. In this state, the charger output voltage is increased to overcharge pressure driverV oltage amplifierV oltage sampling comparatorStart amplifier State level control Charging indicator Logical module Undervoltage detection circuit R- powerCurrent sampling comparator Limiting amplifier Power indicatorV oc is due to the charger output voltage remains constant, so the charging current is a continuous decline. Current down to charge and suspend the current Ioct, the battery capacity has reached 100% of rated capacity, the charger output voltage drops to a lower float voltage VF.3.2 Protection ModuleChip block diagram of the internal protection circuit shown in Figure 3. The circuit includes control logic circuit, sampling circuit, overcharge detection circuit, over-discharge detection comparator, overcurrent detection comparator, load short-circuit detection circuit, level-shifting circuit and reference circuit (BGR).Figure3 Block diagram of battery protectionThis module constitutes a protection circuit shown in Figure 4. Under the chip supply voltage within the normal scope of work, and the VM pin voltage at the overcurrent detection voltage, the battery is in normal operation, the charge and discharge control of the chip high power end of the CO and DO are level, when the chip is in normal working mode. Larger when the battery discharge current will cause voltage rise of the VM pin at the VM pin voltage at above the current detection voltage Viov, then the battery is the current status, if this state to maintain the tiov overcurrent delay time, the chip ban on battery discharge, then the charge to control the end of CO is high, the discharge control side DO is low, the chip is in the current mode, general in order to play on the battery safer and more reasonable protection, the chip will battery over-discharge current to take over the discharge current delay time protection. The general rule is that the over-discharge current is larger, over the Sampling circuitOver discharge detection comparator Control logic circuitLevel conversion circuit Overcharge detection comparator Over-current detection comparator2 Over-current detection comparator1Over-current detection circuitLoad short detection circuitshorter the discharge current delay time. Above Overcharge detection voltage, the chip supply voltage (Vdd> Vcu), the battery is in overcharge state, this state is to maintain the corresponding overcharge delay time tcu chip will be prohibited from charging the battery, then discharge control end DO is high, and charging control terminal CO is low, the chip is in charging mode. When the supply voltage of the chip under the overdischarge detection voltage (Vdd <Vdl,), then the battery is discharged state, this state remains the overdischarge delay time tdl chip will be prohibited to discharge the battery at this time The charge control side CO is high, while the discharge control terminal DO is low, the chip is in discharge mode.ProtectionmoduleFigure4 Protection circuit application schematic diagram4.Circuit DesignTwo charge protection module structure diagram, the circuit can be divided into four parts: the power detection circuit (under-voltage detection circuit), part of the bias circuit (sampling circuit, the reference circuit and bias circuit), the comparator (including the overcharge detection /overdischarge detection comparator, over-current detection and load short-circuit detection circuit) and the logic control part.This paper describes the under-voltage detection circuit (Figure 5), and gives the bandgap reference circuit (Figure 6).Figure5 Under-voltage detection circuitFigure6 A reference power supply circuit diagramBattery charging, voltage stability is particularly important, undervoltage, overvoltage protection is essential, therefore integrated overvoltage, undervoltage protection circuit inside the chip, to improve power supply reliability and security. And protection circuit design should be simple, practical, here designed a CMOS process, the undervoltage protection circuit, this simple circuit structure, process and easy to implement and can be used as high-voltage power integrated circuits and other power protection circuit.Undervoltage protection circuit schematic shown in Figure 5, a total of five components: the bias circuit, reference voltage, the voltage divider circuit, differential amplifier, the output circuit. The circuit supply voltage is 10V; the M0, M1, M2, R0 is the offset portion of the circuit to provide bias to the post-stage circuit, the resistance, Ro, determine the circuit's operating point, the M0, M1, M2 form a current mirror; R1 M14 is the feedback loop of the undervoltage signal; the rest of the M3, M4 and M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, composed of four amplification comparator; M15, DO, a reference voltage, the comparator input with the inverting Biasing circuit Reference circuit Bleeder circuit difference amplifier Output circuitAmplifierAmplifierinput is fixed (V+), partial pressure of the resistance R1, R2, R3, the input to the inverting input of the comparator, when the normal working of the power supply voltage, the inverting terminal of the voltage detection is lost to the inverting terminal voltage of the comparator is greater than V+. Comparator output is low, M14 cutoff, feedback circuit does not work; undervoltage occurs, the voltage divider of R1, R2, R3, reaction is more sensitive, lost to the inverting input voltage is less than V when the resistor divider, the comparator the output voltage is high, this signal will be M14 open, the voltage across R into M at both ends of the saturation voltage close to 0V, thereby further driving down the R1> R2, the partial pressure of the output voltage, the formation of the undervoltage positive feedback. Output, undervoltage lockout, and plays a protective role.5. Simulation results and analysisThe design of the circuit in CSMC 0.6 μm in digital CMOS process simulation and analysis of the circuit. In the overall simulation of the circuit, the main observation is that the protection module on the battery charge and discharge process by monitoring Vdd potential and Vm potential leaving chip CO side and DO-side changes accordingly. The simulation waveform diagram shown in Figure 7, the overall protection module with the battery voltage changes from the usual mode conversion into overcharge mode, and then return to normal working mode, and then into the discharge mode, and finally back to normal working mode. As the design in the early stages of the various parameters to be optimized, but to provide a preliminary simulation results.Figure7 Overvoltage and under-voltage protection circuit simulation waveform6.ConclusionDesigned a set of battery charging and protection functions in one IC. This design not only can reduce the product, they can reduce the peripheral circuit components. The circuit uses the low-power design. This project is underway to design optimization stage, a complete simulation can not meet the requirements, but also need to optimize the design of each module circuit.光伏系统中蓄电池的充电保护IC电路设计1.引言太阳能作为一种取之不尽、用之不竭的能源越来越受到重视。
(完整版)基于STC89C52单片机的太阳能智能充电系统外文翻译毕业论文
毕业论文(设计)文献翻译本翻译源自于：维基百科wikiMicrocontroller毕业设计名称:基于STC89C52单片机的太阳能智能充电系统外文翻译名称：微控制器学生姓名：张钱勇院 (系)：电子信息学院专业班级：电气10803 指导教师：唐桃波辅导教师：唐桃波时间： 2012年4月15日至 2012年4月24日微控制器英特尔8742的核心, 片上集成12 MHz的CPU, 128字节的RAM, 2048字节EPROM, 以及IO设备。
微控制器，也称单片机（有时缩写为μC，UC或MCU）是一种在单个集成电路上包含一个控制器核心，内存和可编程输入输出外设的小型计算机。
类型为NOR Flash或OTP ROM的存储器也往往包括在芯片上，以及通常少量的RAM。
微控制器(MCU)是专为嵌入式应用，而相比之下，个人电脑或其他一般用途的应用中使用微控制器(CPU)。
微控制器用于自动控制产品和设备，如汽车发动机控制系统，植入式医疗设备，遥控器，办公设备，家用电器，电动工具，玩具。
比起使用一个单独的微控制器，内存和输入输出设备，微控制器通过降低尺寸和成本来更经济地数控更多的设备和流程。
混合信号微控制器是很常见的，整合了需要控制非数字电子系统的模拟组件。
有些微控制器可使用四位字长，操作频率的时钟速率低至4 kHz来实现低功耗（毫瓦或微瓦）。
他们通常在等待一个事件，如按一个按钮或其它中断时进入节能状态，处于节能状态（CPU时钟和大部分的外设关闭）时功耗可能只有纳瓦级别，使得他们很适合用电池供电长期工作。
其他微控制器，像数字信号控制器（DSP），可能需要注重性能，他们有更大的计算量，更高的时钟速度和更大的功耗。
历史在1971年第一款单片机4位英特尔4004被发布, 在随后的数年时间里英特尔8008和其它功能更为强大微控制器也开始出现。
然而,控制器需要外部芯片来实现某工作方式,这就提高了整个系统的成本,使它不能成为经济的电子器件。
基于AT89S52单片机控制的太阳能充电器(硬件)设计附外文文献及译文
中国矿业大学本科生毕业设计附外文文献及翻译基于MC-SILICON的双面太阳能电池在工业环境中的实现姓名：学号：学院：信息与电气工程学院专业：电气工程与自动化设计题目：单片机控制的太阳能充电器（硬件）专题：指导教师：职称：副教授摘要在污染和能源口趋紧张的背景下，太阳能作为一种新型的绿色可再生能源，具有储量大、利用经济、清洁环保等优点。
因此，太阳能的利用越来越受到人们的重视。
本文试图设计一种切实可行的太阳能充电控制器，通过对蓄电池充电，满足小功率的用户需求。
本文重点研究了用AT89S52实现太阳能充电控制技术。
详细介绍了100瓦太阳能电池板向12伏蓄电池充电的太阳能控制器硬件系统，包括系统的硬件电路设计、各部分电路的功能、工作原理和电子元器件型号的选取。
硬件系统由直流稳压电源电路，A/D实现对蓄电池端电压的动态监测及转换、AT89S52控制以及输出继电器开关电路四个部分组成，完成了整个太阳能充电控制器电路原理图的设计和制作。
用PROTEUS仿真软件进行了电路仿真，并且制作了相应的电路板。
但是由于时间关系，没能完成实物的实验测试。
本文还对太阳能电池的结构原理、太阳能电池板的伏安特性、常用的铅酸蓄电池原理及工作情况作了详细介绍，并在此基础上介绍常用的蓄电池充电方法。
关键词：太阳能；蓄电池；充电控制；AT89S52；ADC0809ABSTRACTAgainst the background of energy shortage and its pollution, solar energy as a new kind of energy has a lot of advantages such as large reserves, economic, cleanliness and so on. So, people begin to pay more attention to the use of solar energy. The paper designs a feasible solar energy charging controller and storage batteries are charged to meet the needs of low-power users.This article focuses on the use of single-chip realization of solar charge control technology. 100-watt solar panels to 12-volt solar battery charge controller hardware system is detailed, including system hardware circuit design, the various parts of the circuit functions, working principles and models of selected electronic components. Hardware system is composed of four parts, which are DC regulated power supply circuit, A / D to achieve on the battery terminal voltage of the dynamic monitoring and conversion, AT89S52 relay control and output switching circuit. And finish the entire solar charge controller circuit schematic design and production. PROTEUS simulation with circuit simulation software was accomplished, and a corresponding circuit board was produced. However, due to time constraints, failed to complete the kind of experimental test.In this paper, also the structure of the principle of solar cells, solar panels of the Volta metric characteristics of lead-acid batteries commonly used in the work of principle was detailed, and the basis of methods commonly used on rechargeable batteries was introduced.Key words: solar; battery; charge control; AT89S52; ADC0809目录摘要 (i)ABSTRACT (ii)1 绪论 (1)1.1 课题研究背景 (1)1.1.1 当前面临的能源和环境问题 (1)1.1.2 太阳能的开发和利用 (2)1.1.3 光伏发电的特点 (3)1.2 蓄电池充电系统 (3)1.2.1充电器的发展及其简单的类型 (3)1.2.2 太阳能充电器 (4)1.3 本课题研究的主要内容 (5)2 太阳能电池的研究和分析 (6)2.1 太阳能电池的原理 (6)2.2 太阳能电池的分类 (6)2.3 太阳能电池的等效电路 (7)2.4 太阳能电池板的输出特性及影响因素 (8)2.4.1光伏电池的主要参数 (8)2.4.2太阳的光照强度对光伏电池转换效率的影响 (10)2.4.3 温度对光伏电池输出特性的影响 (10)2.4.4 本系统所采用的光伏电池 (11)2.5 本章小结 (12)3 蓄电池 (13)3.1 蓄电池的概念及其一般特性 (13)3.1.1 电池的定义 (13)3.1.2 主要参数指标 (13)3.1.3 充放电特性 (15)3.2 铅酸蓄电池 (16)3.2.1 铅酸蓄电池的电极反应 (17)3.2.2 铅酸蓄电池的充放电特性 (18)3.3 太阳能----蓄电池充电技术研究 (20)3.3.1 恒流充电 (20)3.3.2 恒压充电 (21)3.3.3 恒压限流充电 (22)3.3.4 两阶段、三阶段充电 (22)3.3.5 快速充电 (22)3.3.6 智能充电 (23)3.4 本章小结 (23)4 太阳能充电控制器的研究及设计 (24)4.1太阳能充电器原理 (24)4.1.1 主控芯片的设计 (24)4.1.2 模数转换模块ADC0809简介 (28)4.1.3 电源模块的设计 (30)4.1.4 分频器的设计 (30)4.1.5 外围电路的设计 (30)4.1.6ADC0809与AT89S52接口 (32)4.1.7 74LS00 (33)4.2 单片机的防干扰技术 (35)4.2.1干扰分析 (35)4.2.2硬件抗干扰方法 (36)4.3 系统的软件设计概述 (37)4.4 本章小结 (39)5 结论 (40)5.1 全文工作总结 (40)5.2 进一步工作设想 (40)致谢 (42)参考文献 (43)翻译部分 (45)中文译文 (45)英文原文 (53)1 绪论1.1 课题研究背景1.1.1 当前面临的能源和环境问题[1,2,3,4]能源犹如人体的血液。
毕业设计(论文)_基于单片机的太阳能充电系统的设计
Design ofSolar-Electric Charging System Based on MCU
Abstract:With the depletion of fossil energy, people pay more and more attention to environmental protection. Looking for clean alternative energy becomes more urgent. Solar energy as a renewable energy it has an inexhaustible and clean and safe and so on，so have a broad application prospects. Therefore, this thesis, a solar charging system, the entire system consist of the power conversion circuit, sampling circuit, processor, pulse width modulation controller and battery pack composition. This design solar by way of panels convert solar energy into electricity, through DC / DC converter circuit processing, charging the battery. The process of charging the battery is controlled by pulse width modulation, thereby output power of the solar cell and battery’ life are improved, extend the battery service life.
基于单片机的智能手机充电器的设计(英文版)(doc 11页)
基于单片机的智能手机充电器的设计(英文版)(doc 11页)conventional linear chargers, one of the great advantages of using switching chargers solution is the capability to boost the charge current from what supplied by the source. This is especially important when powering off of a USB port where the current available might be limitedto less than 500mA. Higher charge currents equate to shorter charge cycles thus satisfying customer expectations.There are two kinds of battery chargers used in most handhelds now –linear chargers and switching devices. Linear chargers have a longer history. They have typically provided a relatively efficient, simple wayto charge portable devices, creating minimal noise without many external components. But as portable devices become more complex and add layersof new features, they need higher battery capacity. Linear chargers present liabilities due to power dissipation, which become clear if a user wants to charge a device while using at the same time. The heat generated while simultaneously using and charging can damage the systemor battery. Not a good outcome.The alternative is a switching device, or switch mode battery charger IC, that can deliver higher current levels to a battery while requiringas little power as possible. Historically, there have been some noise issues with these kinds of ICs. In addition, some early generations of switch mode devices have required several external components.However, the benefits of the switched mode battery topology are clear. They include higher efficiency and lower power dissipation, along with fast charging cycles. These devices also are capable of charging from higher input voltages, which allows the use of lower cost unregulated adapters. They can increase the charging current from current restricted sources.The noise from switching chargers usually comes during light load operation, particularly during preconditioning. As it decreases, many switching chargers move into an operation known as pulse skipping. In pulse skipping, the PWM frequency changes asynchronously. There have been battery charger ICs developed that supply high charge current with minimal thermal impact to the system using a switching charger, then switch into a linear charger during low current charging modes to minimize noise. This type of PWM switch mode charger with a linear mode has beena good development, providing high efficiency at the full constant current (fast charge) rate. The switching charger controls large constant current charge (up to 2A) with a PWM switching regulator. It automatically moves to linear mode while the battery is preconditioning and near the end of constant voltage taper charge mode, which lowers the noise whilethe switch mode speeds up charging. Once the charge current level dips below 300 mA, the linear mode kicks in completely and noise generated by the switching converter is eliminated.But now there are further advances. For example, an ideal solution for new handhelds is a complete charger for single cell Li+/ Polymer batteries with up to 1A charge current and advanced indication capabilities for full charge system monitoring. USB Compliant 100mA/500mA charge current settings are beneficial as are programmable pre-charge and fast charge. Many products also include battery temperature monitoring, which ensures safe charging.Companies such as Intersil are leading the development effort for new generations of charger ICs. These fully integrated solutions serve compact applications and provide charge controllers for higher power applications. Charge voltage accuracy is now at 0.5 percent, an improvement over just a few years ago, when an accuracy rating of 1 percent was considered good. Switching frequencies are up to 3 MHz and new switching chargers now provide up to 2A charge current, with one recent example being the ISL9220, which is suitable for both 1 and 2 cells Li Ion applications.In addition, new designs restrict leakage -- there is no less than 0.5uA typical leakage current off the battery when no input power is attached. These improvements also have become available in smaller and smaller packages, such as 4 x 4mm QFNs or 2 x 2mm CSPs, which save real estate in space-constrained handheld equipment.The latest battery charger ICs also are able to monitor the input voltage, the battery voltage, and the charge current. When any of the three parameters exceeds specific limits, the IC turns off an internalN-channel MOSFET to remove the power from the charging system to the battery. This kind of flexible efficiency is another of the improvements now available in these important devices, which are vital to the continuing growth and feature set expansion of mobile, handheld products.【作者】Marino, Giampaolo; Schmitz, Tamara【刊名】Electronic Component News 【出版日期】2010【卷号】Vol.54【期号】No.1【页码】16DESIGN AND IMPLEMENTATION OF A MICROCOMPUTER 8051 SYSTEM POWERED BY DUAL BATTERIES CHARGED BYSOLAR CELLSAbstractSingle-chip microcomputer systems are becoming increasingly popular in current control and information applications. However, due to their battery energy limitations, these systems have a very restricted operation time or recharge cycle if a single rechargeable battery supplies their power. We propose a design and implementation for the software and hardware of a microcomputer 8051 system powered by a dual rechargeable battery that is charged by solar cells. From a feasibility analysis of the queueing model for the stochastic charging and discharging process of the dual battery system, due to the random characteristics of weather conditions and users' operational behavior, we confirm that the average operation time for this model can be much longer than that of a single rechargeable battery power supply. The experimental results of our design also show approximately the same results as our model. With a two-thirds utilization ratio, we can obtain an average operation time four times as long in theoretical results, and three and half times as long in experimental results than with a single rechargeable battery power supply. In addition, the technology trend shows that the power consumption rate for a typical microcomputer system is decreasing and the power generation efficiency for typical solar cells is increasing. Hence, solar cells as the power charging sources for a microcomputer 8051 system supplied by a dual rechargeable battery can be feasible in the near future.Over the past few years, microcomputer system design researchers have been working with different levels of low-power technology. In terms of system, circuits, and device power saving, the results show that every year from 1992 to 1997 the average power consumption of a microcomputer computer decreased more than 20%,and from 1998 to 2001 it decreased by 10%.Reducing power consumption is important because of its potential toextend the recharge period of portable information applications. The longer the battery operation time before a recharge is needed, the more convenient it is for mobile users to operate a portable microcomputer system.Eventually, the power consumption of a single-chip microcomputer system will be small enough to be supplied or recharged by other power sources. One of the proposed power sources is mechanical vibration. Among others, we previously proposed solar cells that can be used as power supply sources. Although current mc-Si solar cell power generation efficiency is not high enough, their efficiency increased from 14.2% to 16.8%from 1990 to 1997.This improvement can reduce the gap between the charging and discharging rate of the power supply of a microcomputer system, so the probability of power exhaustion within a certain operational time is reduced each year.To prolong the battery operation time before recharging, in this article we present the software and hardware module for a single-chip microcomputer 8051 system with a dual battery charged by solar cells. Based on its design and implementation, this work also presents the estimation for power exhaustion probability and the experimental measurement for operation time that depends on the power generation efficiency of solar cells and the power consumption rate of a microcomputer. In addition, due to the overlapping of the charging and the discharging period, if the ratio between the charging and discharging rate is two thirds, then the operation time can potentially be prolonged four times in comparison with a single rechargeable battery.The rest of this is organized as follows. In Section 2, the technology trends with respect to the power consumption of a microcomputer and the power generation efficiency of solar cells are discussed. In Section 3, the queueing model for the stochastic charging and discharging behavior for the dual rechargeable battery in a single-chip microcomputer system is presented. In addition, the feasibility estimation for the dual rechargeable battery in a single chip microcomputer system is given. In Sections 4 and 5, the design and implementation of the software and hardware modules for this system are provided. In Section 6, the experimental results of this system are given. The last section presents conclusions.7. ConclusionsWe have presented the design and implementation of a microcomputer 8051 system powered by dual batteries charged by solar cells. The hardware components used are very common and are of low cost. The control programdesigned uses a common variety of assembly language. The experimental system has shown a very stable operation. From our observation of the theoretical and experimental results, we conclude that this dual-battery design has the potential to extend the average operation time of such a microcomputer by 200%. For a two-thirds utilization ratio in our design, we can gain four times the average operation time of a single-battery design from the theoretical results, and three and a half times the average operation time from experimental results. The difference between the theoretical results and the experimental results is a result of error in the battery-charging process. In addition, when our system operates in strong sunshine, it can work continually without battery exhaustion because the energy generation by the solar cells is greater than the energy consumption of 8051 system.【作者】Y.-W. Bai; C.-L. Chang【刊名】International Journal of Power & Energy Systems【出版日期】2002【卷号】Vol.22【期号】NO.3【页码】125-135译文电池充电器集成电路的改进跟上移动手机功能快速增长的速度在全球无线连接的时代，几乎没有什么比让一个智能手机或移动互联网设备保持带电更重要了。
基于AT89C52单片机的LED显示屏控制系统的设计外文原文和中文翻译
Design of LED Display Control System Based onAT89C52 Single Chip MicrocomputerInstitute of Machinery, on 5 February 2004Maurice WilkesABSTRACT ：THIS paper introduces display design process about hardware and softwarebased on AT89C52 single chip microcomputer. We use a simple external circuit to control the display screen,which size is 32 ×192. The display screen also can display the size of the six 32 × 32 dot matrix Chinese characters by a dynamic scan mode, and can be divided into two small display screens, which can display twenty-four Chinese characters whose size is 16×16. We can modify the code to change the content of the display, subtitles can achieve scrolling function and the scroll speed can be adjusted according to requirements, subtitles can also achieve pause function. The Chinese character code stored in external data memory, the capacity of data memory is expanded according to the requirements of Chinese characters we want to show. This display screen has advantages of small volume, few hardware and simple circuit structure.KEY WORDS: LED, Chinese Character Display, AT89C52I. INTRODUCTIONLED display has become an important symbol of the city lighting, modernization and informationsociety with continuous improvement and beautificatio n of people’s living environment. LED lights can be seen in the large shopping malls, railway station, docks, underground station, and a variety of management window and so on. LED business has become a fast-growing new industry, a huge market space and bright prospects. The text, pictures, animation and video are displayed by LED’s light, and content can be changed. Some components are the display devices of the modular structure, and which usually consists of a display module, control system and power system. The display module is constituted by the lattice structure which consists of LED, and is responsible for light-emitting display; the screen can display text, pictures, video and so on by control system which can control light or dark of LED in the corresponding region; Power system is responsible for transforming input voltage an d current into voltage and current which the screen needs. LED dot matrix display extracted display character font through PC, and sent to the microcontroller, then displayed in the dot matrix screen, which mainly used for display of indoor and outdoor characters. LED dot matrix display can be divided into graphic display, image display and video display by displayed content. Compared with the image display，the characteristics of graphic display is no difference in gray color whether it is monochrome or color display. Therefore, graphic display also fails to reflect the richness of color, and video display can not only show exercise, clear and full-color images but also show television and computer signals. Although there are some differences between the three, but the most basic principles are similar.II. System Overall Structure DesignSingle Chip Microcomputer (SCM) models were selected according to the target, function,reliability, cost, accuracy and speed of the control system. According to the actual situation of the subject, the choice of SCM models mainly considered from the following two aspects: First, SCM has strong anti-interference ability; Second, SCM has a higher cost-effective. Due to MCS-51 is widely used in China, has more information and can compatible with the more peripheral chips too, in particular, ATMEL Corporation, introduced a new generation microcontroller in 2003, that is 89S series, and its typical products with high performance and low cost microcontroller is AT89C52. AT89C52 is a low voltage, high-performance CMOS 8-bit microcontroller, the chip includes 8 KB read-only program memory (PEROM) which erase can be repeated, 256byte random access data memory (RAM), devices adopt high-density nonvolatile memory technology to produce, compatible with the standard MCS-51 instruction set and the 8052 products, while the chip built-in general-purpose 8-bit central processing (CPU). Flash storage unit, can be applied to the more complex control applications.The system was realized by the circuitry which is made up of AT89C52 chip, Clock circuit, reset circuit, column scan driver circuit, line drive circuit and the six 32×32 LED dot matrix, the overall structure of LED characters display is shown in Fig.1. A display unit is composed of dot matrix and two 74HC154. Line data signal is divided into two parts, which is given by the two 8255A respectively, but the 8255A data are from the P0 port the master controller AT89C52. The column scanning signal of each character was given by the two 74HC154, the 74HC154 12 pieces and was divided into six groups. The input signal of 74HC154 was given by the P1.0 ~P1.3 of AT89C52. External data memory 6264 connected with the AT89C52 the P0 port.III. SYSTEM HARDW ARE CIRCUIT DESIGNA .Circuit Design of MCU Control SystemThe size of Chinese characters is 32 ×32, but microcontroller has 32 I/O port, and can’t meet design requirements, so the I/O port must expand, the data port expansion was implemented by two 8255A. The data port expansion is shown in Fig.2, 74HC373 is the address latch, and latch low eight address, the low eight address signals of 6264 provided by it, but the high eight address signals of 6264 provided by P2.0 ~P2.4, Internal port of 8255A was chosen by A0 and A1. 74HC139 is 2-4 decoder, whose input signals are provided by P2.6 and P2.7 of SCM, and provided strobe for the external I / O devices, because the system has more than one external device, make sure that they can not be gated, so that their addresses is the only and do not repeat. The clock circuit of AT89C52 composed of 18, 19feet from the clock side (XTALI and XTAL2), and 12MHz crystal, capacitor C1 and C2.B .The Circuit Design of Display Memory UnitThe size of Chinese characters is 32×32 in the design, each character composed of four parts which each part composed of four LED matrix which the size is 8 × 8, circuit decomposition map of display unit. In addition because the Chinese character for each display needs 128 bytes storage space, but AT89C52 microcontroller chip is only 256 bytes data memory, it is far less than the design requirements, so we the expanded storage space by 8K × 8 external data memory 6264. C. The communicate Design of PcInte1 8255A is a universal programmable parallel input/output interface chip. Its function can be set through the software program, and has a strong versatility. It can be directly through the CPU data bus connected to external devices, easy to use and flexible. Inte18255A interface chip has three 8-bit parallel input and output ports, programming methods can be used to set three ports asinput ports or output ports. Chips work have the basic input and output, strobe input/output and bi-directional input / output. When the data were transmitted by data bus of CPU, its can choose to unconditionally transfer, query transmission or interrupt transmission. During Inte18255A chip three-port, the port C can be used as not only the data port, but also the control port. When the port C is taken as a data port, it can be used as not only 8-bit data port, but also separately as two 4-bit data port, and each bit of the port C can be operated, can set a particular bit to input or output, so provide convenient conditions for bits control.D. Serial Communication Interface CircuitPC and SCM are linked via a serial communication interface. In order to implement serial communication function between MCU and PC, and serial interface level of SCM will be changed into standard RS-232C level. MCU and PC, taking into account the short distance communication, and microcontroller is mainly responsible for receiving commands and data, so the PC is directly connected with the microcontroller, this is the simplest connection method. the signals which is from Pac’s TXD-side were changed into a current signal through the communication circuit, the infrared light emitting diodes of optocouper have current when a signal occurs, the light signals which is emitted by diode projected onto the and photo transistor, converted to electric signal, then input to the microcontroller RXD side so photoelectric conversion is implemented, and electrical is completely isolated to avoid the feedback and interference which is produced by output side.IV. SOFTW ARE DESIGNThe entire software design mainly composes of display program and communication program. The Chinese characters to be displayed on the screen, character and other data for transmission control and display functions were achieved by dynamic scan. Real time communication parts which communicate with PC receive data information by SCM serial disruption, so real-time data information transmission with PC was implemented. The host computer software was implemented by Visual Basic. In the standard serial communication, MSCOMM which is the power communication control is provided by VB, it can set the serial communication of data sent and received, and the serial communication port.Status, message formats and protocols are set, directly send data by Pac’s RS-232/RS-485 serial ports. In order to realized to PC reliable communication with SCM, and ensure that both sides have the same data format and baud rate, this design uses RS-232 communications, a 10 bits data format, 9600bit / s baud rate. Software program composed of the beginning, initialization, display program, front, which the main.Character code stored in the static memory 6264, and the SCM will wait for signal is given, that is, the input signal of SCM pin P3.0. When P3.0 is from low to high, display program begin to be run. First, control words written to 8255A control port, 8255A work in the form of mode 0 in the design. After control word was finished, the data will be displayed which is transferred to the 8255A from the 6264, the display data is output for four times because the line width of the characters screen is 32, a row of data is input and transported from top to bottom each, signal of the first rows which is controlled by SCM is gated after data transmission is over, so the first column data is displayed, then call delay procedures to display the contents of the stable. The next column of data is read after delay procedures is over, and the next row is gated, so that the second column of data is also displayed, and so on, because the serene size is 32 ×192, 192 row are shown, and 192 rows constitute an image. Then, scanning begin from the first column, and thestarting address of display date backward shift on the basis of the original, which has an address overflow issues, it will assign start address to the address pointer when the data address is overflow, the display data content will be constantly repeated. Flow chart of communication with PC and 4 SCM is shown in Figure 10. Real-time communication parts which communicate with PC receive data information by SCM serial disruption, so real-time data information transmission with PC was implemented.CONCLUSIONLED display system that was designed adopted the host computer and slave structure, the host computer is PC, and communicated with slave computer display system through the serial communication interface, which can implement string modification, display mode settings, time setting and other functions; The slave mainly implement display of LED dot matrix display screen. This was controlled by SCM. Chinese character display is 32×32 dot matrix model, and to achieve real-time screen display changes, and have to display the current time and date functions. The design of LED dot matrix display control system has a simple circuit, stability, low power consumption, long life, easy to display characteristics, and include the LED display basic principles and procedures. As long as the microcontroller I/O interface is expanded, and increase the number of LED dot matrix and related chips, you can design a larger are and more tricks of the LED display. This article has some reference value of theory and practice. As the core control unit of the system, that it AT89C52, has lower frequency, in the future, in order to achieve LED video display in real time, and the display image can be compressed, which will increase the burden on the system. We can take advantage of high-speed DSP as the core control unit, and solve the above mentioned problems.基于AT89C52单片机的LED显示屏控制系统的设计机械研究所，2004年2月毛里斯威尔克斯摘要：本文介绍了显示器的硬件与软件设计过程基于AT89C52单片机。
单片机89C52中英文对照翻译(经典版)
AT89C52 internal structure analysis DescriptionThe AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8Kbytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash ona monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,and clock circuitry. In addition, the AT89S52 is designed with static logic for operationdown to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, andinterrupt system to continue functioning. The Power-down mode saves the RAM contentsbut freezes the oscillator, disabling all other chip functions until the next interruptor hardware reset.Pin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as highimpedanceinputs.Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification.External pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups.ThePort 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, asshown in the following table.Port 1 also receives the low-order address bytes duringFlash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups.ThePort 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetchesfrom external program memory and during accesses toexternal data memory that use 16-bit addresses (MOVX DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups.ThePort 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table.Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillat or is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO,the RESET HIGH out feature is enabled.ALE/PROGAddress Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has noeffect if the microcontroller is in external execution mode.PSENProgram Store Enable (PSEN) is the read strobe to externalprogram memory.When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Special Function RegistersA map of the on-chip memory area called the Special FunctionRegister (SFR) space is shown in Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip.Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate er software should not write 1s to these unlisted locations,since they may be used in future products to invokenew features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers:Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt Registers:The individual interrupt enable bits are in the IE register. Two priorities can be set for each ofthe six interrupt sources in the IP register.Memory OrganizationMCS-51 devices have a separate address space for Program and DataMemory. Up to 64K bytes each of external Program and Data Memory can be addressed.Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory.On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location aboveaddress 7FH, the address mode used in the instructionspecifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space.Instructions which use direct addressing access of the SFR space.For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #dataInstructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV R0, #dataNote that stack operations are examples of indirectaddressing, so the upper 128 bytes of data RAM are availableas stack space.Watchdog Timer(One-time Enabled with Reset-out)The WDT is intended as a recovery method in situationswhere the CPU may be subjected to software upsets. The WDT consists of a 13-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external cloc k frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.Using the WDTTo enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H).When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow.The 13-bit counter overflows when it reaches 8191(1FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 8191 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.WDT During Power-down and IdleIn Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior toentering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT fromresetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It issuggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode.To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues tocount if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.UARTThe UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52. For further information on the UART operation, refer to the ATMEL Web site (:// atmel ). From the home page, select ‘Products’,then ‘8051-Architecture Flash Microcontroller’, then‘Product Overview’.Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same wayas Timer 0 and Timer 1 in t he AT89C51 and AT89C52. Forfurther information on the timers’ operation, refer to the ATMEL Web site (:// atmel ). From the home page, select ‘Products’, then ‘8051-Architecture Flash Microcontroller’, then ‘Product Overview’.Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits inT2CON, as shown in Table 3. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, thecount is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency.To ensure that a given level is sampled at least once before it changes, the level should be held for at leastone full machine cycle.Capture ModeIn the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON.This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1- to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H andRCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 5.Auto-reload (Up or Down Counter)Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.Figure 6 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options areselected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down,as shown in Figure 6. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers,TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.译文：89C52的内部结构分析功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。
(完整word版)基于单片机外文翻译
河南理工大学毕业设计（论文）说明书Presented in this paper is a design of pulse measuring instrument based on MCU, as the circuit module plays an important role in the system, such as heart rate acquisition circuit, display circuit and STC89C52 microcontroller through the serial portto realize the connection. This design with STC89C52 microcontroller as the central control unit, through ST188 as infrared photoelectric sensor to collect the pulse signal, after the lm358 for op amp; again through before and after filtering, magnifying, shaping, and get stable signal; functions to achieve the rapid detection of heart. Youcan also through the button to set the pulse value scope; buzzer driver module In the range beyond the scope of the alarm prompt, the measurement results in the liquid crystal display.Experimental results show that the test results of the design and practical requirements are basically the same, STC89C52 MCU strong anti-interference ability and LCD1602 display control the advantages of more convenient so that thesefeatures can be successfully completed. The production cost less than 100 yuan,with low price, easy manipulation, low power consumption, high reliability, very applicable to families and individuals.Heart rate) in professional terms is used to describe the human heart beat cycle. Pulse of modern Chinese will be interpreted as "heart beating frequency value; so the heart rate can also said in a unit of time, heart rhythm speed.Everyone's heart rate signals mostly contains rich physiological and psychological information. This is due to the health of internal organs of the body can reflect in the pulse information. This discovery has gradually attracted the attention of many clinicians. In our country, pulse diagnosis has been regarded as the essence of Chinese medicine; so far the clinical practice has about 2600 years. However due to the use of fingers often there will be some sweat glands refers to pulse diagnosis in the presence of errors can not be ignored; and leads to inaccurate measurement. Then perhaps you would say and the ear vein measurement, instead of the previous is often used. Although by measuring ear ripple come to pulse signal relatively comparison Clean, but because the ear pulse signal is weak, especially when the seasonal changes, the measurement signal is vulnerable to the influence of environmental temperature,resulting in inaccurate measurement values.With the development and progress of world science and technology and economy, cherish life, health care has become a common pursuit of mankind throughout the world. According to the Health Bureau statistics, every year because of cardiovascular and cerebrovascular diseasesdeath of the highest number of human deaths first, not only the high cost of health care, back to the family, the government and the society caused great burden. In recent years, due to the accelerated pace of life, unreasonable eating habits and many junk food impact and other reasons, the incidence of cardiovascular and cerebrovascular is showing a trend of rising year by year. How to scientifically and harmless reduce cardiovascular disease morbidity and mortality, effectively reduce cardiovascular and cerebrovascular diseasesand social Family burden, has become a very serious problem faced by human beings all over the world.World first lever type pulse scanner is Vierordt was founded in 1854. It is a lever and a pressure drum scanner uses the notation to record the pulse waveform, also is the human for the first time through non invasion of recording the human body pulse, then caused a great sensation. However the starting point for the development of domestic relatively is relatively low, in the early 50s of the 20th century Zhu Yancaiwill pulse instrument reference to objective study on the pulse diagnosis in traditional Chinese medicine. In recent years, non invasive vascular function detection gradually attracted the eyes of the medical professionals. Since about 1980, no traumavascular function detection by using the small range, its principle is roughly Based on hemodynamic rheology theory and elastic chamber theory. Characterized in it by the module temperature, blood pressure cuff module, blood oxygen module of multi physiological signal acquisition module combination by of brachial artery blocking opening in the process of finger end temperature signal, oxygen saturation and pulse wave signal changes of the parameters of the, again according to the clinical trial data acquisition and through the method of signal processing and statistical analysis, establishment of vascular function quantitative evaluation formula and blood vessel function evaluation. It has noninvasive, simple operation, accurate, good repeatability and convenient for clinical application and automatically generates diagnosis ofcardiovascular function, health status analysis and gives related medical solution Release.Now pulse testing is no longer confined to the traditional manual testing or stethoscope test, only use electronic devices can be obtained more accurate data. In today's society, most of electronic measuring instruments has been directed towards the digitization, automation development direction. Pulse measuring instrument is not only good performance, simple structure, and has good value of application and popularization. In general, the pulse measurement instrument development is mainly the following trends: first, in the absence of human can automatically analyze the measurement of pulse value; the pulse of the traditional instrument need after experienced doctor pulse signal of the first initial analysis and then make a comprehensive analysis to final To confirm the results, this method of total said tonot only waste a lot of manpower and by factitious error is relatively large. The second: the wide application of digital technology and other advanced technology; pulse measuring instrument integration to want to achieve a higher degree, and are more convenient to carry must rely on the rapid development of digital science and technology; at the same time digital signal processing application will enable interference becomes smaller measurement result ismore accurate. The third: multi function of more and more obvious. The fourth: cheap, easy to carry and application and popularization value better, to the general public convenience.Has always been in the hospital for basis for clinical diagnosis and treatment of most source extracted from the human pulse wave in physiological and pathological information. In China, feeling the pulse is old doctor of traditional Chinese medicineis the most commonly used to diagnose disease, has been in use ever since. The pulse signal emitted by human body contains the velocity of heart rate, full waveform, period and amplitude, a full range of integrated information, in a large extent can reflect human body each part information (for example blood viscosity, blood velocity). Although these biological signals exist in the human body, the signal intensity relative to said is relatively weak; if in a noisy environment effect is more obvious.This graduation design principle is the use of single-chip microprocessorSTC89C52 as the center processor; pulse signal is collected by the sensor, through the microcontroller chip in the interior of the system timer to set the time; finally get the heart rate beat numerical by STC89C52 microcontroller to signal accumulation can be. Normal heartbeat is about 60-100 per minute times, circuit diagram of key module can through the button to set the scope of people's heart rate, above or below the setting range of possible heart there will be risks, buzzer driver module will drive buzzer alarm; the final measurement results Will be displayed on the LCD. The design can by viewing the IR indicates whether the lights and flashing, if sustained, stable flashing that test results are correct and error is small. With the assumption that the display results back and forth rock and numerical difference between the larger, there may exist error. Through the above steps, can roughly determine the body's own health, and is particularly suitable to be used to the individual or family, is also sometimes used in nursing homes and healthcare center.The design of the selection of SCM is STC89C52。
一种基于单片机控制的新型光伏电池 毕业论文外文翻译
附录AMicroprocessor-Controlled New Class of OptimalBattery Chargers for Photovoltaic ApplicationsAbstractA simple, fast and reliable technique for charging batteries by solar arrays is proposed. The operating point of a battery is carefully for cednear the maximum power point of solar cells under all environmental (e.g., insolation, temperature, degradation) conditions. Optimal operation of solar arrays is achieved using the V oltage-Based Maximum Power Point Tracking (VMPPT) technique and the charger operating point is continuously adjusted by changing the charging current. An optimal solar battery charger is designed, simulated and constructed. Experimental and the oretical results are presented and analyzed. The main advantages of the proposed solar battery charger as compared with conventional ones are shorter charge time and lower cost.Index Terms—Charger, microprocessor, maximum power point tracking (MPPT), photovoltaic.I.INTRODUCTIONThe field of photovoltaic systems is quite broad with many stand-alone and grid-connected configurations. Applications of solar energy include water pumping , refrigeration and vaccine storage, air conditioning, light sources, electric vehicles ,PV power plants ,hybrid systems , military and space applications.Reference[8]has divided photovoltaic applications into four categories: large-scale grid connected systems, small remote photovoltaic plants, low power stand-alone systems, and a combination of solar systems with other alternative energy sources. These categories may also be viewed in terms of load characteristics. There are three load types:a DC load, a “dead” AC load, and a “live” AC load(e.g.,a utility system).Most of these applications use batteries as backup energy systems and/or matchingdevices for balancing their energy flow during peak load or poor environmental conditions (e.g., low insolation, high temperature or high degradation).The main drawbacks of PV systems are high fabrication cost, low energy conversion efficiency, and nonlinear characteristics. For increasing conversion efficiency, many Maximum Power Point Tracking (MPPT) techniques have been proposed and implemented. They can be categorized as:A)“Look-up table”methods [12],[13]—The nonlinear and time varying nature of solar cells and their great dependency on radiation and temperature levels as well as degradation(aging,dirt,snow) effects, make it difficult to record and store all possible system conditions.B)“Perturbation and observation(P&O)”methods [14],[15] —Measured cellcharacteristics (current, voltage and power)are employed along with an on-line search algorithm to compute the corresponding maximum power point which is dependent on insolation, temperature or degradation levels. Problems with this approach are undesirable measurement errors(especially for current)which strongly affect tracker accuracy.C)“Computational” methods [2],[16]–[19]—The nonlinear V-I haracteristics of a solar panel are modeled using mathematical equations or numerical approximations, and maximum power points are computed for different load conditions as a function of cell open-circuit voltages or cell short-circuit currents. In the literature, many battery charging techniques are investigated and proposed[20]–[24].These methods use avariety of battery characteristics(voltage and temperature) to achieve a safe and fast charging process. However, two well-known charging methods employing photovoltaic sources are the constant current charging, and the direct connection of solar panel to battery and load(e.g., battery tied solar systems).In this paper, a simple and fast variable-current charging tech-nique, based on “computational” methods, is proposed for photovoltaic applications —where photovoltaic charger and battery are matched with respect to voltage and current. Online measurements of panel open-circuit voltage are used to detect the maximum power point of a solar panel. Battery charge rate is continuously adjusted such that the system operating point is forced near the detected maximum power point of solar panels. The oretical and experimental analyses are used to demonstrate the reliability and validity of the proposed technique.II.MODELING OF PROPOSED FAST SOLARBATTERY CHARGERElectrical models for solar panel, maximum power point tracker, battery and battery charger will be used to simulate the proposed solar charging technique.A.Solar Panel ModelUsing the equivalent circuit of solar cells(Fig.1),the radiation and temperature dependent V-I haracteristics of m parallel strings with n series cells per string is00()sc sa sa s sa I i mI nn V In R i mI mλ-+=- （1） where is the cell short-circuit current(representing in solation level), is the reverse saturation current,is the series cell resistance and is a constant coefficient which depends on the cell material and the temperature T.For the silicon solar panel(,)used for theoretical and experimental analyses of this paper[Table I, manufactured by the Iranian Optical Fiber Fabrication Co.(OFFC)],(1)can be written as at T=250.000051.767()0.00005sc sa sa sa I i V In i -+=- （2） Equations(3a)and(3b)are evaluated for one OFFC panel at T=70 and T=-20, respectively. Computed and measured V-I as well as P-I characteristics for the OFFCpanel are shown in Fig.2 for two insolation levels. This figure illustrates the variations of cell maximum power points (e.g., maxima of P-I curves)with respect to insolation levels.3.0050.000241.69()0.00024sa sa sa i V In i -+=- (3a) 20830.000011.82()0.00001sa sa sa i V In i -+=- (3b) Eqs.(2)and(3)along with Fig.2 depict the strong nonlinear dependency of the Maximum Power Point(MPP)with respect to insolation and temperature levels and justify for any high efficient PV system an accurate MPP tracker.B.V oltage-Based Maximum Power Point Tracking to determine operating points corresponding to maximum power for different insolation and temperature levels,(2)and(3) are commonly used[2],[17]to compute the partial derivative ofpower with respect to cell voltage.Instead of finding the maximum via derivative,[18]and[19]employ numerical methods to show a linear dependency between “cell v oltages corresponding to maximum power ”and“ cell open circuit voltages”MP v OC V M V = (4)This equation characterizes the main idea of the V oltage-Based Maximum Power Point Tracking (VMPPT) technique. Is called the“voltage factor”and is equal to 0.74 for the OFFC silicon cells[18],[19].Equation(4)is plotted in Fig.3 together with the computed(almost linear)dependency of with respect to(shown by “+” signs ). C. Nonlinear Battery Model Most battery models ignore the presence of nonlinear electro chemical characteristics[27],[28].For the theoretical and experimental analyses of this paper, we propose a new nonlinear model for Ni-Cd batteries as shown in Fig.4. Measurements show linear variations of, and nonlinear characteristics of with respect to charge rate: （5）where is the charging current and R , Cs and Co are parameter values at biasing current level. For one cell of the 7 Ah Ni-Cd battery used for theoretical and experimental analyzes of this paper, the constants of(5)are obtained from measured characteristics(Table II)at charge rates of,and C. Computed and measured battery characteristics are compared in Fig.5. D.The Proposed Solar Charger For the optimal solar charger,an appropriate combination of the MPPT algorithm and battery charging technique must be selected. For the tracker, the simple and reliable voltage-based MPPT technique is used requiring very few components for sensing the solar-panel, open-circuit voltage. For the charging technique, variable-current charging is selected. This will allow the tracker to continuously adjust battery-charging rate and force the system operating point near the maximum power point of solar panels. Other tracking 1232123()()()()()()())lin s bat so rs bat o lin s bat so cs bat o lin P bat po cp bat o nonlin p bat p bat p bat p R f I R K I I C f I C K I I C f I C K I I R f I K I K I K ==+-==+-==+-==++techniques could also be used. However, they require more components(for sensing panel short-circuit current and/or simultaneous panel voltage and current measurements)resulting in lower overall efficiency.III.SIMULATION OF PROPOSED SOLARBATTERY CHARGERSimulink software and its facilities are used to model the proposed solar battery charger(Fig.6).We have created a block called“PV Source”to simulate the nonlinear V-I characteristics of one OFFC solar panel(2)employing cell short-circuit current as a measure of insolation level [Fig.6(b)].Saturation and delay functions are introduced to limit the fast response of the “controlled voltage source”and to improve convergence. The output of this block is the panel operating voltage.To simulate voltage-based maximum power point tracking, a block called “VMPPT”is introduced[Fig.6(c)]that usesand to generate desired duty cycles for the charge unit.The panel open-circuit voltage is calculated,thereafter the panel voltage corresponding to maximum power(4)is computed and compared with and the error is amplified through a proper transfer function to generate the desired duty cycle.The charger unit consists of a DC/DC buck converter(chopper and output filter)and a LC input filter. The chopper includes a fast switch and a schottky diode. A block called“B attery Parameter Calculation”computes battery parameters [Fig.4 and(5)]corresponding to the system operating point.IV.CONSTRUCTION OF PROPOSED SOLARBATTERY CHARGERFig.7 shows the constructed battery charger, which consists of the following parts:Silicon Solar Panel—one OFFC silicon solar panel with maximum output power of about 35 W(Table I)is used togenerate solar energy. Microprocessor—The 8085 Micro Controller Unit(MCU)is used to record and process measured voltage and current waveforms and to compute required signalsfor control and drive circuits. The 1524 IC employed to generate the required PWM command(e.g.,at 50 kHz)and voltage/current signals for the charger unit. Thevoltage-based MPPT for the solar panel is implemented by MCU under different environmental and output operating conditions. Note that the panel open-circuit voltage is continuously measured at a slower rate (e.g., every minute).Fig.8 shows the main functions of the MCU. If multiple solar panels with similar characteristics are used, a reference panel could be relied on to sense the open-circuit voltage. Any shadowing effects caused by dust, snow or clouds will result in power-current characteristics with several maxima. This will complicate MPPT.Charger Unit—A chopper circuit is used to properlyconnect anddisconnect—based on PWM signals—solarpanel from battery and load. Input and output filters are employed to suppress electrical noise at the output of the solar panel and at the input of the battery.Input and output current and voltage sensors are relied on for signal measurements.Battery and Load—Five units of 7 Ah Ni-Cd batteriesare connected in series to store electrical energy. Resistors serve as loads during discharging and charging modes, respectively. In discharge mode, the solar panel is partially or totally inactivated by shadow or eclipse effects.V.ANALYSIS OF EXPERIMENTAL ANDTHEORETICAL RESULTSThree charging methods are investigated: the proposed variable-current charging (method 1), direct connection of battery and load to solar panel(method 2),and constant-current charging(method 3). Battery (full) charging state is detected using the approach (e.g., using magnitude and slope of battery voltage as a function of time)of[24].Experiments are performed for the following three operating conditions.Case A:Operation at an Incidence Angle of about Measured and computed time functions for battery current and voltage as well as solar panel power and voltage are shown in Fig.9 for normal operating condition(e.g.,normal insolation and temperature).As expected,fine tracking of solar maximum output power is achieved throughout the charging process when the proposed charging technique is used[Fig.9(c)],method 1).Charging time for the proposed method is only 3 hours which is about 73%and 52%of the required charging times for methods 2 and 3,respectively. In method 1,panel voltage(corresponding to maximum power)which is determined by(4)is slightly higher at 11 A.M.due to lower environmental temperature.In method 2,panel voltage[e.g.,in Fig.9(d)]and its operating point is dominated by battery voltage.This causes panel output power to decrease from 29 W(for method 1)to about 20 W(for method 2).In method 3,panel voltage[about 17 V in Fig.9(d)]is determined by panel current which is proportional to the constant battery current (e.g.,0.2 C).This rate of charge is used to determine panel operating points for the simulation as outlined in Fig.6.The comparison of computed(X)and measured results forsome selected operating points is shown in Fig.9.Case B:Operation at an Incidence Angle of about Similar experiments are performed for a change in angle of incidence(Fig.10).At 12:30 P.M.the solar panel is rotated forward(in the direction of sun)such that the angle of incidence is changed from about to about. During the first 105 minutes, the charging processes of the three methods are normal and results are similar to Fig.9. At the start of changing the angle of incidence from about to about, maximum panel output power is decreased to about 25 W[Fig.10(c),method 1].Our detailed measurements show that under all operating conditions (e.g., before and after changing the angle of incidence),method 1 continues to adjust panel operating point near the maximum power point of the V-I characteristics. The angle of incidence of about increases charge time of method 1 toabout 3.2 h. Methods 2 and 3 are not able to completely charge the battery since their operating points are not optimally selected. Note the inherent small voltage regulation of method 1,caused by the increasing slope of battery voltage. This is not true for methods 2 and 3 where fast voltage drops [e.g., at 12:30 P.M. and 13:45 P.M.in Fig.10(b)]occur. The measured characteristics of method 3 are interesting: constant-current charging continues for some time after changing the angle of incidence from to,this is so because the battery requires about 20 W of power [Fig.9(c),method 3].At 13:45 P.M.,the solar panel is no longer able to produce the required power since its maximum power is decreased to about 20 W. The converter duty cycle is forced to unity, causing direct connection of panel, battery and load. Therefore, measured characteristics of methods 2 and 3 become similar.Case C: Operation with Eclipse This environmental operating condition is essential in satellite and spacecraft applications .Cease of insolation along with considerable temperature drop makes panel V-I characteristics very different before and after eclipse. We have generated this effect(Fig.11)by completely covering solar panel from 12:00 to 12:30 P.M. and decreasing its temperature from 24 C to 12 C As expected, charge time of proposed method is slightly increased to 2.8 h which is about 65%and 63%of the times required for methods 2 and 3,respectively. Note the increased panel maximum output power from 28 W(before eclipse)to 33 W(just after eclipse)due to temperature effects(Fig.11).The temperature drop does not change panel output power in method 2 because the panel operating point is dominated by the constant battery voltage. Similar analysis holds for method 3 where the panel operating point is mainly determined by constant panel current, caused by the constant battery current. Note that the stored energy in the battery[e.g.,] is not exactly equal for the three charging methods(Table III).This is due to different charging currents, which changes battery charging efficiency[29]VI.CONCLUSIONSV oltage-based maximum power point tracking and a nonlinear battery model are used to introduce a new class of microprocessor based optimal solar battery chargers.A photovoltaic system consisting of a silicon solar panel, charger unit,Ni-Cd batteries and a resistive load is constructed and simulated. Based on theoretical and experimental results which are performed for the proposed charging technique(method 1),the direct connection of solar panel to battery and load(method 2),and the constant current charging(method 3),the following conclusions are drawn:Computed results for selected operating points show good agreements with measurements.Under different operating conditions, the solar panel output powers are larger for the proposed charging technique(method 1)as compared to methods 2 and 3(e.g., 20%to 65%).Therefore, the proposed charging technique requires fewer solar panels(e.g., lower cost).The proposed charging technique is faster than methods 2 and 3(e.g.,40%to 75%shorter charging times)under different environmental conditions. Under low insolation condition(e.g., angle of incidence of about),charging time of proposedtechnique is increased by 20%while methods 2 and 3 fail to charge the battery since their operating points on panel V-I characteristics are not optimally selected.The battery stored energy for the proposed charger is less as compared to methods 2 and 3 due to the dependency of charging efficiency on the charge current[29]. The proposed charging technique does not introduce rapid voltage drops and establishes an inherent small voltage regulation, especially under unfavorable environmental conditions. Therefore, the proposed charging technique is suggested to replace unregulated photovoltaic systems.附录B一种基于单片机控制的新型光伏电池摘要本文提出了一种简单、快速可靠的太阳能电池阵列技术，使光伏电池在各种环境下（例如日照、温度等）都能接近最大功率点，理想的太阳能电池阵列工作点是通过基于最大功率点追踪技术（VMPPT）和控制工作点持续调节对改变的控制流改变来实现的。
89C51单片机英文说明论文英文翻译部份
89C51 Microcontroller IntroductionMicrocontrollers are used in a multitude of commercial applications such as modems, motor-control systems, air conditioner control systems automotive engine and among others. The high processing speed and enhaneed peripheral set of these microcontrollers make them suitable for such high-speed event-based applications. However, these critical application domains also require that these microcontrollers are highly reliable. The high reliability and low market risks can be ensured by a robust testing process and a proper tools en vironment for the validation of these microcontrollers both at the comp on ent and at the system level. Intel Plaform Engineering department developed an object-onented multi-threaded test environment for the validation of its AT89C51 automotive microcontrollers・ The goals of this environment was not only to provide a robust testing environment for the AT89C51 automotive microcontrollers but to develop an environment which can be easily extended and reused for the validation of several other future microcontrollers・ The environment was developed in conjunct!on with Microsoft Foundation Classes (AT89C51). The paper describes the design and mechanism of this test environme nt, its interactions with various h a rd wa re/softwa re en vironme ntal components and how to use AT89C51 ・Are 8-bit microcontroller early or 4 bits. One of the most successful is the INTEL 8031, for a simple, reliable and good performanee was a lot of praise. Then developed in 8031 out of MCS51 MCU Systems. SCM systems based on this system until now is still widely used. With the increased requirements of industrial control field, began a 16-bit microcontroller but not ideal because the cost has not been very widely used・After 90 years with the great development of consumer electronics, microcontroller tech no logy has been a huge increase. With INTEL i960 series especially the later series of widely used ARM, 32-bit microcontroller quickly replace high-end 16-bit MCU status and enter the mainstream market. The traditional8-bit microcontroller performance have been the rapid increase capacity in crease compared to 80 the number of times. Curre ntly, high-e nd 32-bit microcontroller clocked over 300MHz z the performa nee catchi ng the mid-90s dedicated processor, while the average model prices fall to one . dollar, the most high-end model is only 10 dollars ・ Modern SCM systems are no Ion ger only in the development and use of bare metal environment, a large number of proprietary embedded operating system is widely used in the full range of SCM・The handheld computers and cell phones as the core processing of high-end microcontroller can even use a dedicated Windows and Linux operating systems.SCM relies on the program, and can be modified・Through different procedures to achieve different functions, in particular special unique features, this is another device much effort needs to be done, some are great efforts are very difficult to achieve. A not very complex functions if the 50's with the United States developed 74 series, or the 60's CD4000 series of these pure hardware buttoned, then the circuit must be a large PCB board! But if the United States if the 70's with a series of successful SCM market, the result will be a drastic change! Just because you are prepared by microcomputer programs can achieve high intelligence, high efficiency and high reliability!IntroductionThe 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed calculations and fast input/output operations・ MCS 51 microcontrollers are typically used for high-speed event control systems. Commercial applications in elude modems, motor-control systems printers, photocopiers, air conditioner control systems, disk drives；and medical instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems, airbags, suspension system® and antilock braking systems (ABS). The AT89C51 is especially well suited to applications that benefit from its processing speed and enhanced on-chip peripheral functions set, such as automotive power-train control vehicle dynamic suspension, antilock braking z and stability control applications. Because of these critical applications the market requires a reliable cost-effective controller with a low interrupt latency response, ability to service the high number of time and event driven integrated peripherals needed in real time applications, and a CPU with above average processing power in a single package・ The financial and legal risk of having devices that operate unpredictably is very high. Once in the market, particularly in mission critical applications such as an autopilot or anti-lock braking system, mistakes are financiallyprohibitive. Redesign costs can 「un as high as a $500« much more if the fix means back annotating it across a product family that share the same core and/or peripheral design flaw.I n additi on, field replacements of comp on ents is extremely expe nsive. as the devices are typically sealed in modules with a total value several times that of the component To mitigate these problems, it is essential that comprehensive testing of the controllers be carried out at both the comp orient level and system level un der worst case environmentai and voltage complete and thorough validation necessitates not only a well-defined process but also a proper environment and tools to facilitate and execute the mission successfully・Intel Chandler Platform Engineering group provides postsilicon system validation (SV) of various micro-controllers and processors. The system validation process can be broken into three major type of the device and its application requirements determine which types of testing are performed on the device・The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines f two 16-bittimer/counters； a five vector two-level interrupt architecture^ full duple ser -ial port, on-chip oscillator and clock addition z the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable powersaving modes. The Idle Mode stops the CPU while allowing the RAM, timer/countersserial port and interrupt sys -tern to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscil -lator disabling all other chip functions until the next hardware reset.Pin DescriptionVCC Supply voltage・GND Ground.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When Is are written to port 0 pins, the pins can be used as highimpedance in puts ・Port 0 may also be con figured to be the multiplexed loworder address/data bus during accesses to external program and data memory・ In this mode PO has internal pullups ・Port 0 also receives the code bytes during Flash programming’and outputs the code bytes during program verification. External pullups are required during program verificatio n.Port 1Port 1 is an 8-bit bi-directional I/O port with internal Port 1 output buffers can sink/so -urce four TTL Is are written to Port 1 pins they are pulled high by the internal pullups and can be used as in puts ・ As in puts, Port 1 pins that are externally being pulled low will source current (HL) because of the internal pullups・Port 1 also receives the low-order address bytes during Flash programming and verificatio n.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL Is are written to Port 2 pins they are pulled high by the in ter nal pullups and can be used as inputs. As in puts, Port 2 pins that are exter nally being pulled low will source current (IIL) because of the internal pullups・Port 2 emits the high-order address byte during fetches from external program memory and during accesses to Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups・Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application/ it uses strong internal pull-ups when emitting Is. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals durin Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/sou -rce four TTL Is are written to Port 3 pins they are pulled high by the internal pullups and can be used as in puts ・ As inputs.Port 3 pins that are exte「n ally being pulled low will source current (HL) because of the pullups・RSTReset in put A high on this pin for two machi ne cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address duringaccesses to external memory・This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped duri -ng each access to external desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode・PSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory・EA/VPPExternal Access Enable・ EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed/ EA will be internally latched on should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require12-volt VPP.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complementof the written datum on ・ Once the write cycle has been completed, true data are valid on all outputs andthe next cycle may begin. Data Polling may begin any time after a write cycle has been initiated・Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal, is pulled low after ALE goes high during programming to indicate BUSY. is pulled high again when programming is done to indicate READY・Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly・ Verification of the lock bits is achieved by observing that their features are enabled.A microcomputer interface converts information between two forms. Outside the microcomputer the info rmation han died by an electronic system exists as a physical signal, but within the program/ it is represented nu merically ・ The fun ctio n of any in terface can be broken down into a number of operations which modify the data in some way, so that the process of conversion between the external and internal forms is carried out in a number of steps・An analog-to-digital converter(ADC) is used to convert a continuously variable signal toa corresponding digital form which can take any one of a fixed number of possible binary values・ If the output of the transducer does not vary continuously, no ADC is n ecessary .In this case the signal conditi oning section must convert the in coming signal to a form whichcan be connected directly to the next part of the interface, the input/output section of the microcomputer itself.Output in terfaces take a similar form, the obvious differe nee being that here the flow of information is in the opposite direction; it is passed from the program to the outside world. In this case the program may call an output subroutine which supervises the operation of theinterface and performs the scaling numbers which may be needed for a digital-to-analog converter(DAC). This subroutine passes information in turn to an output device which produces a corresponding electrical signal, which could be converted into analog form using a DAC. Finally the signal is conditioned(usually amplified) to a form suitable for operating an actuator.The signals used within microcomputer circuits are almost always too small to be connected directly to the "outside world" and some kind of interface must be used to translate them to a more appropriate form・ The design of section of interface circuits is one of the most important tasks facing the engineer wishing to apply microcomputers. We have seen that in microcomputers information is represented as discrete patterns of bits; this digital form is most useful when the microcomputer is to be connected to equipment which can only be switched on or off, where each bit might represent the state of a switch or actuator.To solve real-world problems, a microcontroller must have more than just a CPU/a program, and a data memory. In addition, it must contain hardware allowing the CPU to access info「mation from the outside world ・ Once the CPU gathers informatio n and processes the data, it must also be able to effect change on some portion of the outside world. These hardware devices, called peripherals, are the CPU' s window to the outside.The most basic form of peripheral available on microcontrollers is the general purpose 170 port. Each of the I/O pins can be used as either an in put or an output The function of each pin is determined by setting or clearing corresponding bits in a corresponding data direction register during the initialization stage of a program. Each output pin may be driven to either a logic one or a logic zero by using CPU instructions to pin may be viewed (or read.) by the CPU using program instructions.Some type of serial unit is included on microcontrollers to allow the CPU to communicatebit-serially with external devices ・ Using a bit serial format in stead of bit-parallel format requires fewer I/O pins to perform the communication function, which makes it less expensive, but slower. Serial transmissions are performed either synchronously or asynchronously・Its applicationsSCM is widely used in instruments and meters, household appliances, medical equipment, aerospace, specialized equipment, intelligent management and process control fields/ roughly divided into the following several areas:SCM has a small size, low power consumption, controlling function, expansion flexibility, the advantages of miniaturization and ease of use, widely used instrument, combining different types of sensors can be realized, such as voltage, power; frequency, humidity temperature, flow, speed z thicknes® angle, length, hardness, elementa- physical pressure measurement. SCM makes use of digital instruments, intelligence, miniaturization, and functionality than the use of more powerful electronic or digital circuits・ Such as precision measuring equipment (power meter, oscilloscope, variousanalytical instrument).89C51单片机简介单片机普遍应用于商业：诸如调制解调器,电动机操纵系统,空调操纵系统,汽车发动机和其他一些领域。
89c51单片机论文英文文献翻译
英文原文DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atm-el’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51™instruction set and pin out. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atm-el AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.Features:• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory• Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-Level Program Memory Lock• 128 x 8-Bit Internal RAM• 32 Programmable I/O Lines• Two 16-Bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low Power Idle and Power Down ModesThe AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Block DiagramPin Description:VCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 may also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode P0 has internal pull-ups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 alsoreceives some controlsignals for Flashprogramming andverification.RSTReset input. Ahigh on this pin fortwo machine cycles while the oscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the micro-controller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.mode Program memory ALE ^pens Port0 Port1Port2Port3idle internal 11 data data data DataIdle External 11 floatData data DataIn the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SF-Rs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.– Reserved bits.. Reset value depends on reset source.中文原文描述AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes的快速可擦写的只读程序存储器（PEROM）和128 bytes 的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flesh存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。
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毕业论文(设计)文献翻译本翻译源自于：维基百科wikiMicrocontroller毕业设计名称:基于STC89C52单片机的太阳能智能充电系统外文翻译名称：微控制器学生姓名：张钱勇院 (系)：电子信息学院专业班级：电气10803 指导教师：唐桃波辅导教师：唐桃波时间： 2012年4月15日至 2012年4月24日微控制器英特尔8742的核心, 片上集成12 MHz的CPU, 128字节的RAM, 2048字节EPROM, 以及IO设备。
微控制器，也称单片机（有时缩写为μC，UC或MCU）是一种在单个集成电路上包含一个控制器核心，内存和可编程输入输出外设的小型计算机。
类型为NOR Flash或OTP ROM的存储器也往往包括在芯片上，以及通常少量的RAM。
微控制器(MCU)是专为嵌入式应用，而相比之下，个人电脑或其他一般用途的应用中使用微控制器(CPU)。
微控制器用于自动控制产品和设备，如汽车发动机控制系统，植入式医疗设备，遥控器，办公设备，家用电器，电动工具，玩具。
比起使用一个单独的微控制器，内存和输入输出设备，微控制器通过降低尺寸和成本来更经济地数控更多的设备和流程。
混合信号微控制器是很常见的，整合了需要控制非数字电子系统的模拟组件。
有些微控制器可使用四位字长，操作频率的时钟速率低至4 kHz来实现低功耗（毫瓦或微瓦）。
他们通常在等待一个事件，如按一个按钮或其它中断时进入节能状态，处于节能状态（CPU时钟和大部分的外设关闭）时功耗可能只有纳瓦级别，使得他们很适合用电池供电长期工作。
其他微控制器，像数字信号控制器（DSP），可能需要注重性能，他们有更大的计算量，更高的时钟速度和更大的功耗。
历史在1971年第一款单片机4位英特尔4004被发布, 在随后的数年时间里英特尔8008和其它功能更为强大微控制器也开始出现。
然而,控制器需要外部芯片来实现某工作方式,这就提高了整个系统的成本,使它不能成为经济的电子器件。
史密森尼学会表示Gary Boone 和 Michael Cochran工程师在1971年成功地创造了第一款单片机。
他们的研究成果TMS 1000在1974年就已经商业化。
它在一块芯片中集合了只读存储器、读写内存、控制器和时钟芯片,是在嵌入式系统中使用。
部分原因是出于对单芯片TMS1000的考虑,英特尔公司开发了一种基于优化控制芯片应用的计算机系统, 在1977年英特尔8048的商业化有部分开始运营了部。
英特尔8048将只读存储器和随机存储器组合在一块芯片上。
该芯片将会在超过十亿个计算机键盘和其它许多应用上找到用武之地。
在那时，英特尔公司董事长Luke J·Valenter声称在公司历史上微控制器是最为成功的,且它使部门的预算超过了25%。
在这个时候大多数微控制器有两个变体。
有一个可擦除可编程只读存储器的程序存储器,这明显比只能编程一次的可编程只读存储器更加昂贵。
可擦除可编程只读存储器的擦除需要通过一个透明石英的盖子暴露于紫外线光。
一次性部分可以在低成本的不透明的塑料包装中制作。
在1993年,电可擦可编程只读存储器的引入使微控制器 (从芯片PIC16x84开始)能快速地实现电擦，而不必像可擦除可编程只读存储器一样需要昂贵的包装,且允许在系统编程中快速成型。
同年, Atmel公司首次推出使用闪速存储器的单片机，其它公司迅速跟进,推出具有同样存储类型的单片机。
随着时间的推移，微控制器成本急剧下降,在2009年，最便宜的8位微控制器只需花费不到0.25美金就可以大量获得,且类似的数量的一些32位微控制器也只需1美元左右就可以获得。
如今微控制器很便宜,这使得爱好者更容易获得,且针对某些控制器有许多的网上论坛。
在不久的将来,非挥发性的磁性随机存储器因其具有很长的耐久力和半导体晶片工艺成本较低的特点，很可能被用于微控制器中。
容量在世界上销售cpu中大约有55%属于8位微控制器和微控制器。
根据Semico所述, 2006年8位微控制器销量超过四十亿。
在发达国家有些家可能只有四个通用微控制器,但确拥有大约三打微控制器。
一辆典型的中档汽车有多达30或更多的微控制器。
它们也可以在诸如洗衣机、微波炉和电话等许多电气设备上找到。
嵌入式设计微控制器可以被认为是自包含的控制器、内存和外围设备，可作为嵌入式系统中使用。
今天的多数微控制器嵌入在其他设备里，如汽车，电话，家用电器，计算机外设。
这些被称为嵌入式系统。
一些嵌入式系统非常复杂，而很多对内存大小和程序长度有很低的要求，他们没有操作系统，软件的复杂性很低。
典型的输入和输出设备包括开关，继电器，螺线管，LED灯，小型或定制液晶显示器，射频器件，传感器（如温度，湿度，光照强度等）。
嵌入式系统通常没有键盘，屏幕，硬盘，打印机或其他电脑上用的I O设备，可能缺乏任何形式的人机交互设备。
中断微控制器必须对它所控制的嵌入式设备发生的事件提供实时（可预测的，虽然不一定快）的响应。
当某些事件发生时，中断系统可以命令控制器暂停处理当前指令序列，并开始中断服务例程（ISR，或“中断处理程序”）。
ISR将根据中断源执行响应的程序，然后再返回原来的指令序列。
可能的中断源是依赖设备的，通常包括一些事件如内部定时器溢出，完成模数转换，逻辑电平变化，一个按钮被按下等，数据会从通信链路接受。
在注重功耗的设备（如使用电池供电）中，中断也可能用来唤醒处于低功耗休眠状态的微控制器。
程序单片机程序必须符合现有的片上程序存储器，因为一个有外部可扩展存储器的系统是很贵的。
编译器和汇编器用来将高级语言和汇编语言代码转换成一个紧凑的机器代码来保存到微控制器的存储器中。
取决于不同的设备，存储器可能是永久性的只读存储器，只能在工厂里编程，或是Flash或可擦写ROM中。
其他微控制器的功能微控制器通常包含几个到几十个通用输入输出引脚（GPIO的）。
GPIO引脚可通过软件配置为输入或输出状态。
当GPIO引脚配置为输入状态，他们往往是用来读取传感器或外部信号。
配置为输出状态，GPIO引脚可以驱动LED或马达等外部设备。
许多嵌入式系统需要读取传感器产生的模拟信号。
这是使用模数转换器（ADC）的目的。
由于控制器在建造时，解释和处理数字数据，即1和0，他们是无法处理一个设备发送给它的任何模拟信号的。
因此，模数转换器用来将传入的数据转换成控制器可以识别的一种形式。
微控制器一个不常见的功能，是数模转换器（DAC），允许控制器输出模拟信号或电压等级。
除了转换器，许多嵌入式微控制器还包括多种定时器。
对定时器的最常见的类型是可编程间隔定时器（PIT）。
无论是从一个值倒数至零，或增加计数寄存器的值，溢出到零。
一旦它到达零，它发送一个表明它已经完成计数的中断到控制器。
这对于恒温器等设备是非常有用的：它定期测试周围的温度，判断这时是否需要开启空调的、加热器等设备。
实时处理单元（TPU）是一个复杂的计时器。
除了倒计时，TPU可检测输入事件，产生输出事件，并执行其他有用的操作。
一个专用的脉宽调制（PWM）模块使得CPU可以控制电源转换器，阻性负载，电机等，而不需要在计时循环上浪费大量的CPU资源。
通用异步接收器发送器（UART）的模块使我们能够在一个非常低的CPU负载的情况下通过串行线收发数据。
专用片上硬件还常常包括与其他设备数字通信的能力，如I2C和串行外设接口（SPI）。
更高的集成度相对于通用CPU，微控制器可能无法像CPU一样在同一个芯片上集成外部地址或数据总线，RAM和非易失性内存。
由于使用更少的引脚，该芯片可以被放置在一个更小，更便宜的封装里。
在单个芯片上集成了内存和其他外围设备并把它们作为一个单元来测试增加了该芯片的成本，但结果往往是降低整个嵌入式系统的净成本。
虽然一个已经集成外设的芯片通常成本略高于一个CPU和外围设备芯片，但是可以制作芯片更少，成本更小，更便宜的电路板，并减少所需的组装和测试的电路板的劳动。
一个微控制器是一个集成电路，通常具有以下特点：中央处理器单元，包括小型和简单的4位处理器到复杂的32或64位处理器易失性存储器（RAM）为数据存储ROM，EPROM中，EEPROM或闪存用于存储程序和操作参数离散输入和输出位，允许控制或检测每个封装引脚的逻辑状态串行输入输出，如串行端口器（UART）其他串行通讯接口，如I²C，串行外围接口和控制器区域网络互联定时器，计数器，PWM发生器和看门狗等外设时钟发生器，往往是一个石英振荡器计时晶体谐振器或RC电路许多包括模拟到数字转换器，一些包括数字至模拟转换器在线编程和调试支持这种集成大大降低了芯片的数量和电路板布线和空间，可以使用单独的芯片生产等效系统。
此外，在低引脚数的器件，每个引脚可用作几个内部外设接口，由软件选择的引脚功能。
这使得这样的一个部件比每个引脚专用功能的芯片应用更广泛。
微控制器已被证明自从1970年问世以来在嵌入式系统中高度流行。
有些微控制器采用哈佛结构：指令和数据分开存储总线，从而采取同时进行访问。
凡采用哈佛架构，控制器字长可能和内部存储器和寄存器位长度不同，例如：用8位数据寄存器使用了12位指令。
周边设备的整合往往难以决定。
微控制器供应商通常灵活地设计产品来适应不同时期的市场需求，使得系统整体成本较低。
制造商必须平衡的需要，尽量减少芯片尺寸而不是增加更多功能。
微控制器架构有很大的不同。
有些设计包括通用微控制器与一个或多个ROM，RAM，或集成I O功能内核到封装内。
其他设计构建目的是控制应用程序。
一个微控制器的指令集通常有很多逐位运算的指令旨在使控制程序更紧凑。
例如，通用控制器可能需要几个指令，以测试在一个寄存器位的值来判断分支，而微控制器可以用一个单一的指令来实现这个常用的功能。
微控制器通常没有一个数学协控制器，因此，浮点运算是由软件处理。
影响据2006共售出超过四十亿的8位微控制器Semico公司称，世界上销售的所有CPU中约55%是8位微控制器和微控制器。
一个典型的发达国家家庭很可能只有四个通用微控制器，却有约三十几个微控制器。
一个典型的中档汽车已多达30个或更多的微控制器。
他们还可以在很多电器设备中找到，如洗衣机，微波炉和电话。
制造商们通常生产微控制器的特殊版本，以帮助目标系统的硬件和软件开发。
起初这些措施包括EPROM的顶部有一个“窗口”，可以通过紫外线擦除它的程序存储器，以便重新编程（“烧写”）和测试周期。
自1998年以来，EPROM的版本变得罕见，并已被EEPROM和FLASH这些容易使用（可以电擦除）和更便宜的设备所取代。
其他版本可能出现在ROM作为外部设备，而不是内部记忆体的场合，但是因为廉价微控制器编程器的广泛使用，这种情况越来越少了。
单片机的现场可编程器件的使用可能允许现场更新固件或升级工厂已经组装的，但尚未交付的产品的版本。