芯片ISL6752的原理和应用

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开关电源小论文

1.开关电源研究的背景及意义现实生活中常用的电源，可以分为发出电能的电源和变换电能的电源两大类。

我们把输人和输出都是电能的电源称之为变换电能的电源。

开关电源就是属于变换电能的电源，此种电源就是电路中的电力电子器件工作在开关状态的电源。

开关电源的前身是线性稳压电源。

在我们生活中，大多数电子装置、电气控制设备的工作电源是直流电源。

在开关电源出现之前，这些装置的工作电源都采用线性稳压电源。

在20世纪50年代，美国宇航局以小型化、重量轻为目标,为搭载火箭而开发了开关电源。

在半个多世纪的电力电子技术发展历程中,开关电源因具有体积小、重量轻、效率高、发热量低、性能稳定等优点而逐渐取代传统技术制造的相控稳压电源,并广泛应用于电子整机设备中。

在现代社会,电子信息设备与人们的生活、工作的关系越来越密切,而所有的电子设备都离不开电源。

高速发展的计算机技术带领人类进入了信息社会,同时也促进了电源技术的迅速发展。

电源技术的精髓是电能变换,即利用电能变换技术,将市电或电池等一次电源变换成适用于各种用电对象的二次电源。

开关电源技术属于电力电子技术,它运用功率变换器进行电能变换。

经过变换的电能,可以满足各种用电需求。

由于其高效节能可带来巨大经济效益,因而引起社会各方面的重视而得到迅速推广。

2.国内外研究现状及发展趋势开关电源真正的发展是从70年代开始的,在此期间系统的电力电子理论的确立。

电力电子理论为开关电源的发展提供了一个良好而必需的基础。

但在产品应用的初期,存在开关频率低(20kHz以下)、功率密度比较低、可靠性较差的缺点。

因此开关电源主要的发展方向,是针对上述缺点不断加以改善。

大功率场效应管(MOSFET)及绝缘栅晶体管(IGBT)等器材的出现为高频和大功率变换器提供了极有利的条件。

新的器件和新的拓扑理论的出现使得开关电源技术日趋可靠、成熟、经济、适用。

开关电源目前的发展,主要朝着更高的功能密度和变换效率及更好的动态特性；更好的环保性能；智能化与高可靠性；更广泛的应用等方向发展。

中文ISL6752

ISL6752输出时序图输出时序图
状态一：、导通导通，、关断关断。状态一：UL、LR导通，LL、UR关断。
t1时刻，励磁电感Lm 在Vin 之下开始励磁。
im (t ) = Vin (t − t1 ) + im (t1 ) Lm
LL D4 C4 Ls LR D3 C3 Vin D1 C1 D2 C2
ห้องสมุดไป่ตู้
UL
UR
在t1时刻，励磁电感Lm中的励磁电流 im(t1)=-Im。输出电感Lo的端电压在t1时刻也随之跳变（见上图所示），其状态也由之前的能量释放状态转为存储能量状态。
Is(t)
Io(t)
D5
+
Lo
Co Ro
+
Lm
Np
-
Ns1
Im(t)
+
Ip(t)
+
Ns2 D6
状态二：关断关断，UR、LL仍关断，UL仍开通。状态二：LR关断
t2时刻，LR关断，C2开始放电和C3开始充电。因原边绕组电流Ip(t)近似于恒定，故C2、C3的是线性充放电，到了t21时刻，电容 C2 的电压UC2从VIN下降到 UOxNP/NS。。其中：其中：
I ⋅ (t − t 2 ) U C 2 (t ) = Vin − C 2 C2
Vin
Vin D1 C1 D2 C2 UL UR
LL
D4
C4
Ls
LR
D3
C3
Is(t)
Io(t)
D5
Lo
+
Co Ro
Ns1 Lm Np
Im(t)
Ns2 D6
Ip(t)

ISL6752(6754)EVAL1Z ZVS DC Power Supply with Synchronous Rectifiers User Guide

Application Note 1603Author: Richard GarciaISL6752/54EVAL1Z ZVS DC/DC Power Supply with Synchronous Rectifiers User GuideThe ISL6752/54EVAL1Z is a new design based on the ISL6752EVAL1Z but with several design modifications to improve the efficiency from 90% to 95%. The control circuit has been moved off the main board onto a daughter card. Two different daughter cards are provided: one using the ISL6752 and the other using the ISL6754. Both control cards utilize the Intersil zero voltage switching (ZVS) topology. The ISL6752 daughter card features pulse by pulse current limiting, and the ISL6754 daughter card features a patented method for average current limiting that results in a brick-wall current limit profile.The PCB layout of the ISL6752/54EVAL1Z has also been greatly improved over the ISL6752EVAL1Z. Even though the overall size of the board has been reduced, the copper losses have been reduced.In addition to the ZVS function, this board also incorporates N-Channel FETs as secondary side rectifiers, also known as synchronous rectifiers (SR). Power dissipation of the secondary side rectifiers is reduced because the conduction losses of SRs are significantly less than the conduction losses of PN or Schottky diodes.ScopeThis application note covers implementation of synchronous rectifiers (SRs) and their associated drive circuits as used on the ISL6752/54EVAL1Z board. Implementation of the primary side ZVS controller, based on the ISL6752 daughter card, is described extensively in Intersil Application Note AN1262, “Designing with the ISL6752, ISL6753 ZVS Full-Bridge Controllers.”Also reviewed is the performance of this evaluation board. Oscillographs illustrate the performance of the power supply with load transients on the output. The ZVS switching of the bridge FETs is shown, and efficiency and load regulation are measured.At the end of this application note, the schematics, bill of materials, and printed circuit board layouts are included for reference.TABLE 1.SPECIFICATIONSAbsolute Maximum Input Voltage450VDCOperating Input Voltage 350V to 450VDCMaximum Input Current 2.5ADC Rated Output Current50ADC Current Limit 60A ± 5%Output Voltage12V ± 5%Efficiency at 100% (50A) Load 95%Efficiency at 20% (10A) Load92%FIGURE 1.NEW ISL6752/54EVAL1ZBlock DiagramThe evaluation board is composed of several distinct circuit elements. The three main sections are the ZVS full bridge on the input, the current doubler rectifier on the output, and the controller daughter card. See “Schematics- Main Board,ISL6752/54EVAL1Z” on page23 and “Schematics - Daughter Card” on page25 for complete circuit details.Daughter CardsThe ISL6752 or ISL6754 control ICs are located on their respective daughter cards, as shown in Figures 3 and 4. Both daughter cards have the control ICs on the primary side and the voltage error amplifier on the secondary side. Creepage spacing between the primary and secondary is maintained on the cards. The ISL6752 and the ISL6754 control ICs are located on the primary side, eliminating the need for two AC line isolating gate drive transformers to drive the primary side bridge FETs. Instead, the low side FETs are driven directly by MOSFET drivers (on the main board), and the high side FETs are driven by a gate drive transformer that only requires operational insulation. Primary side control also simplifies design of the current sensing transformers because they also do not have to be AC line isolating.A line isolation rated opto-coupler (D5 on ISL6752DB or D2 on ISL6754DB) passes the analog error signal generated by the error amplifier, U1, from the secondary to the primary. Opto D3 passes a digital signal from primary to secondary to turn off the SRS for diode emulation. The only functional difference between the ISL6752 andISL6754 daughter cards is how current limit is implemented. The ISL6752 uses pulse-by-pulse current limit, and the ISL6754 uses average current limit.Special test points located on the daughter cards aid in probing nodes on the daughter cards for evaluation. Test points PGND and TP_PRI are located on the primary side, and SGND andTP_SEC are located on the secondary. With these test points, the user can employ the spring-like probe accessories included withFIGURE 2.ISL6752/54EVAL1Z BLOCK DIAGRAMFIGURE 3.ISL6752 DAUGHTER CARDmany scope probes. The scope signal pin is inserted in TP_PRI (or TP_SEC), and the short spring ground lead is inserted in PGND (or SGND).To probe any node on the daughter card, solder a 30ga insulated wire between the desired node and the via that is associated with the TP_PRI or TP_SEC test point. This method not only simplifies probing of any node, but also implements the preferredtechnique of measuring small signals in the presence of high amplitude switching magnetic fields.The ISL6752DBEVAL1Z and the ISL6754DBEVAL1Z daughter cards are also available as standalone evaluation kits.ZVS Full BridgeThe low side FETs, Q 3 and Q 4, are driven directly by the ISL89160 MOSFET driver, U1 (Figure 5). The two high-side FETs, Q 1 and Q 2, are indirectly driven by the ISL89160 driver, U2. A level translating gate drive transformer, T 3, with complementary output windings, directly drives the high-side bridge FETs with a symmetrical square wave. The design of T 3 is simplified because it only needs 400V operational insulation, and it is always driven with a square wave, thus eliminating the problems associated with non-symmetrical drive waveforms.Observe that the ISL89160 MOSFET drivers are located as close as possible to their respective bridge FETs to minimize thedetrimental effects of parasitic inductance on the outputs of the drivers. Although the input signal lead lengths between the drivers and the daughter card are relatively long (about 5cm), they are shielded on top and bottom by ground planes, to significantly reduce the noise injected on these lines. Thehysteresis of the ISL89160 inputs also lessens the possibility of noise corrupting the gate signals.High Voltage ProtectionBecause a failure of the bridge can cause catastrophic damage to the primary side control elements, a voltage crowbar, F1 and D 3, and a voltage blocking diode, D 4, are incorporated (Figure 6). D 3 clamps the bias voltage to a safe level. If 400V is applied to the V DD node, F1 opens shortly after D3 conducts current. D 4provides additional protection by blocking high voltage from being applied to the 13V lab supply. Note that a fully debugged power supply does not need these additional components. These parts are included on the evaluation board to minimize damage, should the user accidently introduce a fault while evaluating thecircuits. The designer may want to keep F1 in the final design, toprevent a loud bang if the bridge does fail.FIGURE 4.ISL6754 DAUGHTER CARDFIGURE 5.FULL BRIDGEFIGURE 6.PROTECTION CIRCUITSPrimary Side Current SensingThe primary side bridge has two current sensing transformers, T 2 and T 4, one on each leg on the drains of the low-side bridge FETs (Figure 7). Using two transformers allows each CT to reset during alternate half cycles. Alternate current sensing methods are reviewed in “Current Sensing” on page 8.Synchronous Rectifier Drive CircuitTwo banks of SRs are driven by the ISL89163 MOSFET driver, U4 (Figure 8). An RCD network on the inputs to this driver delay the turn-on of the SRs relative to the turn-off of the primary side bridge FETs.The ISL89367, U108, can optionally be used to drive the SRs instead of the ISL89163. Review “Schematics - Daughter Card” on page 25 to understand how to disconnect the ISL89163 and connect the ISL89367.The pulse transformer, T 6, crosses the isolation boundary to couple the control signals from the ISL6752, ISL6754 to the MOSFET drivers (Figure 9). Note that this transformer alsoprovides the secondary side bias voltage for the MOSFET drivers.Current Doubler OutputThe current doubler output is composed of two banks of SRs, Q 107... Q 109 and Q 111... Q 113; inductors L 102and L 103; and output filter capacitors, C 133... C 136 (Figure 10). The advantage of this topology is that the output current is shared by the two inductors, thus reducing conduction losses. Another advantage isthat the secondary winding of the power transformer does not require a center tap.FIGURE 7.PRIMARY SIDE CURRENT SENSINGFIGURE 8.SRs AND DRIVERSFIGURE 9.PULSE TRANSFORMER AND DRIVERBasic SR PrinciplesReplacing diodes with MOSFETs has two major advantages:•Dramatically reduces conduction losses•The applied duty cycle remains virtually constant from no load to full load. Disadvantages are:•Additional complexity and cost•Higher reverse recovery losses as compared to fast recovery diodes.•When paralleling units for redundancy, provisions must be made to prevent current circulation among the paralleled units.SR Drive Timing RequirementsTo emulate a diode, an SR must be driven ON when a diode would normally be conducting. But unlike a diode, if the SR is ON, the current through the SR can reverse if the voltage on the SR “cathode” becomes positive. The consequence is that if the SR is driven ON when the primary side is sourcing voltage to the secondary, the secondary side will be shorted by the SR. Figure 11 illustrates the timing required to drive the SRs. Notethat the rising edges of the two lower bridge FETs are delayed bythe ISL6752/54 relative to the PWM signal. Likewise, the risingedges of the SRs gate signals are delayed by the ISL89163relative to the falling edge of the PWM signal. These delays arenecessary to prevent the overlap of drive signals that wouldresult with high amplitude short circuit currents.When an SR is turned off while current is flowing from source todrain, the current diverts from the FET channel to the internalbody diode. Because the voltage drop across the body diode ishigher than the channel, it is desirable to minimize dissipation byminimizing the duration of the current flow through the bodydiode.FIGURE 10.CURRENT DOUBLER OUTPUTFIGURE 11.TIMING FOR SRs AND BRIDGE FETsSR Drive and BiasOUTLLN and OUTLRN in Figure 12 are control signals from the ISL6752/54 that are used to drive the SRs. Because theISL6752/54 is located on the primary side, a pulse transformer, T6, is used to cross the isolation boundary. The simplified schematic of Figure 12 illustrates the use of T6 to not only couple OUTLLN and OUTLRN to the secondary, but also to generate the bias for drivers on the secondary.When /OUTLLN or /OUTLRN (outputs of EL7212) transitions to a logic high, it is necessary to turn off the associated SR quickly. For example, when /OUTLRN (blue) transitions high, V1 is high, and C10 is quickly discharged by Q100. U4 then drives R-SR off. In a similar manner, when /OUTLLN is high, U4 drives L-SR off. When /OUTLLN or /OUTLRN transitions to a logic low, it is necessary to turn on the SRs after a time delay, to prevent the SRs from shorting the primary side bridge when it is sourcing current. For example, when /OUTLRN transitions to low, V1 is low and Q100 turns off, allowing C10 to be charged by R27. When the positive threshold of UR is exceeded, the output of U4 drives on R_SR. In a similar manner, the high to low transition of/OUTLLN results in the output of U4 driving on L_SR after a time delay.Note that the cathodes of D9 are connected together to peak charge C123. Because C123 is large in value, after the initial charging, the voltage does not change significantly from cycle to cycle. An important aspect of generating the bias for U4 in this manner is that the thresholds for the logic transitions on the inputs of U4 are proportional to VBIAS, and the voltage to charge C9 and C10 is also VBIAS. Consequently, the delays generated by the RC networks are independent of the absolute value of VBIAS. Current DoublerFigure 13 illustrates the current flow in the two inductors of the current doubler topology. Current flow in the circuit is correlated with the waveforms by color coding. The green waveform represents the sum of red and blue currents through R LOAD. For circuit clarity, paralleled SRs and output capacitors of theISL6752/54EVAL1Z board are not shown.When using diodes (instead of SRs), if the average load current is less than half of the ramp current in the output inductors, the current in the inductors becomes discontinuous, and the duty cycle of the PWM is shortened to maintain the desired output voltage. When using SRs, the inductor currents in L1 and L2 can become negative because current in SRs can flow bidirectionally; consequently, the duty cycle remains virtually unchanged. The benefit is that the load transient performance is the same for any load from zero up to current limit. Another advantage is that, for very light loads, the duty cycle is not reduced to very small duty cycles, pulse skipping does not occur, and the associated voltage jitter does not happen.An important design consideration for the current doubler topology is that the DC resistance of both halves must be equal. PCB layout must be as symmetrical as possible, and the DCRs of the inductors should be reasonably equal. If not, the current between the two sides does not split equally. Because perfect physical PCB symmetry is not always possible, current sharing between inductors must be confirmed.In Figure 14, inductor current waveforms are taken from the ISL6752/54EVAL1Z board. Current balance between the two inductors was achieved after one board revision. The inductor currents maintain the same waveform shape even at no load. Another design consideration when using SRs is how to connect the outputs of multiple power supplies in parallel for redundancy or increased power capacity. A consequence of negative current flow in an SR (when a diode would otherwise be reverse biased and off) is that power can be transferred from the secondary to the primary if one of the paralleled outputs has a higher voltage. The voltage loop of the units with lower set point voltages attempts to pull down the voltage by sinking current from the higher set point units. The primary side bridge capacitor is charged by the secondary side, eventually resulting in excessive voltage damage. This damage can be avoided by using OR-ing diodes (or FETs) on the paralleled outputs. Another solution is to turn off the SRs (diode emulation mode) when the current reverses in the SRs, but this eliminates some of the advantages of using SRs. Paralleling features are not implemented on the ISL6752/54EVAL1Z board.FIGURE 13.CURRENT FLOW IN TWO INDUCTORS OF CURRENT DOUBLER TOPOLOGYFIGURE 14.INDUCTOR CURRENT WAVEFORMS 50A LOAD30A LOAD NO LOADCurrent SensingCurrent flowing from the secondary to the primary can result in an unanticipated malfunction of the current sensing transformer circuit if reverse SR currents are not considered. Figure 15 shows a commonly used primary side current sensing circuit utilizing one current sensing transformer (CT).This circuit works well for peak current mode control if power is always flowing from primary to secondary, as is the case when diodes are used instead of SRs. Figure 16 illustrates the performance of the current sensing output when power always flows from primary to secondary.The voltage across R S is as expected. The vertical dashed lines show when the power cycle is terminated at the required peak of the current.Figure 17 illustrates what happens at no load to the sense voltage across R S.Notice that the negative components of the primary transformer current are rectified, resulting in two peaks of current across R S for each half cycle. Under steady state conditions, the rectified negative component may cause erratic performance because the cycle can terminate on the first peak (the inverted peak, as indicated by the vertical red line) instead of the required second peak. This condition can easily be corrected by having a small load across the output to ensure that the negative peak is always less than the positive.A minimum load, however, does not correct a more serious problem that occurs when there is a large load step from a heavy load to no load. When the load current is interrupted, the output capacitor charges higher than the regulated voltage. As the regulation loop is starting to respond by slewing to a minimum duty cycle, the excessive voltage on the output capacitor starts to discharge back to the primary. This results in a large negative current at the beginning of the duty cycle, which causes the duty cycle to be terminated very early. The imbalance of the applied volt-seconds to the power transformer may saturate the power transformer and damage the power bridge.Another scenario is that the current sensing transformer itself may saturate, which also damages the bridge. The control loop cannot maintain balanced alternate half cycles applied to the power transformer without valid current sense information. There are three solutions to this problem. Figure 18 illustrates the placements of two current sensing transformers, one on each drain leg of the bottom FETs.In this configuration, only positive current flowing into the drains of the bottom FETs are sensed across R S, solving the problem of rectified negative currents being impressed across R S. An advantage of using two CTs is that there is a full half cycle available to reset the cores of the CTs. This is the solution used in the ISL6752/54EVAL1Z board.FIGURE 15.PRIMARY SIDE CURRENT SENSING CIRCUIT UTILIZINGONE CTFIGURE 16.PERFORMANCE OF CURRENT SENSING OUTPUTFIGURE 17.NO LOAD SENSE VOLTAGE ACROSS R SFigure 19 shows a different current sensing implementation that also solves the problem shown in Figure 15. In this example, both drain currents of the bottom FETs are sensed by only one CT. There are some limitations that must be considered, however. The minimum time available to reset the core is the duration of the selected dead time between the two FETs on the same side of the bridge. To accommodate the resetting of the CT, this dead time can be made longer, but the consequences of reducing the maximum duty cycle available for output voltage regulation mustIf the dead time is kept short, then the peak voltage required for resetting the core is relatively large. For example, assume that the selected dead time is 2% of the duty cycle. The resultingworst-case reset voltage is shown approximately in Equation1:In Equation 1, V SMAX is 1V (the current limit voltage of theISL6752); this is the ideal reset voltage. In practice, however, the parasitic capacitance of the output windings suppresses the peak voltage, and consequently, the reset time increases. If a custom current sensing transformer is designed, the effects of the parasitic capacitance can be minimized by increasing the space between turns. If a standard, off-the-shelf transformer is used, however, the output capacitance may be too large to allow long duty cycles. In this case, the two-transformer solution may be necessary.Notice in Figure 19 that the 400V RTN is slightly more negative than signal ground. This configuration is recommended for applications that directly drive the bottom FETs with MOSFET drivers. If the 400V RTN and the MOSFET drivers are grounded, regenerative feedback will be present on the output of the MOSFET drivers because of the CT windings in the gate drive loop.A variation on the current sense circuit in Figure 19 is to place the current sensing transformer in the common drain lead of the two high-side FETs, as shown in Figure 20.The circuits shown in Figures 19 and 20 give exactly the same performance, but the problem associated with the gate drives (as explained in Figure 19) is avoided. The disadvantage of placing the CT at this location is that the CT must be designed with400VDC operational insulation.ConclusionThis application note reviews the use of MOSFETs as synchronous rectifiers to replace conventional diodes. The advantages of improved power efficiency and load transient are reviewed along with implementation problems that must be solved.The use of daughter cards for the ISL6752 and ISL6754 control ICs also allows comparison of cycle-by-cycle peak current limiting and average current limiting.TRANSFORMERSFIGURE 19.CURRENT SENSING TRANSFORMER IN THE COMMON SOURCE LEAD0.980.02⁄()V SMAX49V=•(EQ. 1)FIGURE 20.DRAIN LEADReferences[1]Fred Greenfeld, Intersil Application Note AN1246,“Techniques to Improve ZVS Full-bridge Performance”[2]Fred Greenfeld, Intersil Application Note AN1262, “Designingwith the ISL6752, ISL6753 ZVS Full-bridge Controllers”[3]Richard Garcia, Intersil Application Note AN1619, “Designingwith ISL6752DBEVAL1Z and ISL6754DBEVAL1Z ControlCards”Evaluation Board Set-upThe following sections cover the set-up of theISL6752/54EVAL1Z evaluation board. Also included are waveforms, performance parameters, PCB layout, and schematics.Setting UpLab Equipment Required•DC bias power supply, 12.6VDC @ 200mA minimum •Adjustable 0VDC-400VDC regulated lab power supply, 2.5ADC minimum with current limit•Fan to cool heatsinks•Oscilloscope, digital preferred, with 4 channels, 20MHz minimum bandwidth•Adjustable DC load (electronic or resistor), 70A @ 12V,100A @ 0V min, >850W•DC Multimeter•Infra-red temperature probe (optional but highly recommended)Turn-On Procedure1.Solder a wire between DISABLE and PGND-1 lugs located onthe lower left side of the main board. Optionally connect a switch between these two lugs.2.Install either of the daughter control cards onto the mainboard.3.Connect the DC load to the outputs of the evaluation board.Adjust the load to zero current.4.With both supplies turned off, connect the DC bias supply tothe +13V terminal and PGND.5.Connect the 400V supply to +400V and 400V RTN.6.Turn on the DC bias supply and adjust the current limit to200mA. Adjust the voltage to +12.6 VDC. The lab supplycurrent should be approximately 150mA.7.Turn on the 400V supply and adjust the current limit to 2.5A.Adjust the voltage to 400VDC. Do not exceed 450VDC. The current should be approximately 45mA.8.Turn on the fan and direct the air flow through the heatsinksmounted on the bottom of the board.ing the test points that are adjacent to the output powerlugs, measure the output voltage of 12V ±0.5VDC.The output load and input voltage can now be safely adjusted. Because there is no thermal shut-down circuit, it is important to maintain adequate airflow over the heatsinks, especially when applying large loads. It is recommended to measure the temperature of the power FETs (primary bridge and secondary SRs) to ensure that their temperatures do not exceed +85°C. It is usually necessary to have only a moderate airflow over the heatsinks, even under worst-case loads.Danger•This evaluation unit should be used and operated only by persons experienced and knowledgeable in the design and operation of high voltage power conversion equipment. •Use of this evaluation unit constitutes acceptance of all risk inherent in the operation of equipment having accessible hazardous voltage. Careless operation may result in serious injury or death.•Use safety glasses or other suitable eye protection.•A line isolated 400VDC supply is required. CautionA voltage clamp, D3, is used to protect the primary side control circuit from catastrophic damage should the high voltage bridge fail. In order to prevent this clamp from conducting, do not adjust the bias supply above 13.5VDC.WaveformsZVSIn Figure 21, the drain-source voltage of the low-side FETs relative to the gate voltage is displayed to highlight the ZVS performance of the bridge. The load is at the rated 50A. Notice that full ZVS is not achieved because the minimum resonance voltage is about 25VDC. Also, the gate drive is turning on late (about 25ns), allowing the resonant voltage to start rising. Eventhough the optimum zero voltage switching is not achieved, 98% of the switching losses are still recovered [(4002-502)/4002=98%]. This improvement over the ISL6752EVALZ was achieved by increasing the leakage inductance of thetransformer and by using bridge FETs with less body capacitance.In Figure 22, resonant switching with 50% load still saves 84% of the switching losses. Other techniques can be used to improve ZVS performance. For more information, see Application NoteAN1246, “Techniques to Improve ZVS Ful-bridge Performance”.ZVS WaveformsFIGURE 21.RESONANT SWITCHING WITH 100% (50A) LOADFIGURE 22.RESONANT SWITCHING WITH 50% (25A) LOADLoad Transients WaveformsFIGURE 23.STEP LOAD: 0A TO 12.5A (12.5A DELTA)FIGURE 24.STEP LOAD: 25A TO 37.5A (12.5A DELTA)FIGURE 25.STEP LOAD: 37.5A TO 50AFIGURE 26.STEP LOAD: 0A TO 25AFIGURE 27.STEP LOAD: 0A TO 50AFIGURE 28.SHORT CIRCUIT RELEASE WITH ISL6754V OUT recovers after a short circuit is removed when using the ISL6754DBEVAL controller.After the short is removed, V OUT increases linearly because the output capacitance is being charged with a constant current (~55A).NOTE:Output Ripple and Noise WaveformsFIGURE 29.OUTPUT RIPPLE, 50A LOAD, 40MHz BANDWIDTHFIGURE 30.OUTPUT RIPPLE, 50A LOAD, 145MHz BANDWIDTHTransformer Current, Primary Winding WaveformsFIGURE 31.PRIMARY TRANSFORMER CURRENT vs OUTPUT LOAD TRANSIENT (25A TO 50A)FIGURE 32.PRIMARY TRANSFORMER CURRENT vs OUTPUT LOAD TRANSIENT (50A TO 25A)Performance CurvesFIGURE 33.POWER EFFICIENCY vs LOAD (ISL6752 OR ISL6754)FIGURE 34.LOAD REGULATION FIGURE 35.PULSE BY PULSE vs AVERAGE CURRENT LIMIT21015202570758085909295100OUTPUT CURRENT (A)E F F I C I E N C Y (%)6560555030354045505592% EFFICIENCY WITH 20% LOAD12.0011.9511.9011.8511.80ISL6754ISL6752102030405060I OUT (A)V O U T (V )01020304050607080I OUT (A)V O U T (V )121086420ISL6754ISL6752Application Note 1603Bill of MaterialsPART NUMBERQTY UNITS REFERENCE DESIGNATORDESCRIPTION MANUFACTURER MANUFACTURER PART ISL6752/54EVAL1ZREVBPCB1eaPWB-PCB,ISL6752_54EVAL1Z, REV B, ROHSIMAGINEERING INCISL6752/54EVAL1ZREVBPC BC3216X7R1C475K-T 2eaC11, C17CAPACITOR, SMD, 1206, 4.7µF, 16V, 10%, X7R, ROHSTDK C3216X7R1C475KC4532X7R2J104K-T 2ea C5, C18CAP, SMD, 1812, 0.1µF, 630V, 10%, X7R, ROHSTDKC4532X7R2J104K GA355QR7GF332KW01L-T 2ea C20, C121CAP, SMD, 2220, 3300pF, 250V, 10%, X7R, ROHSMURATA GA355QR7GF332KW01L H1046-00102-100V10-T 2ea C14, C15CAP, SMD, 0805, 1000pF, 100V, 10%, X7R, ROHSVENKEL C0805X7R101-102KNE H1046-00102-50V5-T 2ea C9, C10CAP, SMD, 0805, 1000pF, 50V, 5%, NP0, ROHS PANASONIC ECU-V1H102JCX H1046-00105-25V10-T 5ea C6, C12, C13, C16, C22CAP, SMD, 0805, 1.0µF, 25V, 10%, X5R, ROHS AVX 08053C105KAT2A H1065-00106-25V10-T 1ea C123, C132CAP, SMD, 1206, 10µF, 25V, 10%, X5R, ROHS VENKEL C1206X5R250-106KNE H1082-00475-50V10-T 4ea C7, C8, C127, C129CAP, SMD, 1210, 4.7µF, 50V, 10%, X7R, ROHS MURATA GRM32ER71H475KA88L SER2814L-332KL2eaL102, L103COIL-PWR INDUCTOR, SMD, 3.3µH, 10%, 48A, 1.2m Ω, ROHS COILCRAFTSER2814L-332KLUUG1C222MNL1ZD 4ea C133-C136CAP, SMD, 16X16.5, 2200µF, 16V, 20%, AL.EL., ROHS NICHICON UUG1C222MNL1ZDUUG2W330MNL1MS 4ea C1-C4CAP, SMD, 18X21.5, 33µF, 450V, 20%, ALUM.ELEC, ROHS NICHICON UUG2W330MNL1MS131-4353-001ea VOUT CONN-SCOPE PROBE TEST PT, COMPACT, PCBMNT, ROHSTEKTRONIX 131-4353-001514-26eaa) 13VDC, 400VDC, PGND-1, PGND-2, DISABLE CONN-TURRET, TERMINAL POST, TH, ROHSKEYSTONE 1514-21514-20ea b) 400VDC_RTNCONN-TURRET, TERMINAL POST, TH, ROHSKEYSTONE 1514-250029ea a) CS+, VREF, OUTLL, OUTLR, OUTUL, OUTUR CONN-MINI TEST POINT, VERTICAL, WHITE, ROHS KEYSTONE500250020ea b) SR_EN, OUTLLN, OUTLRNCONN-MINI TEST POINT, VERTICAL, WHITE, ROHSKEYSTONE 50025016-T13eaa) GLL, GLR, LLN, LRN, SR_A, SR_B, PGND-3, 2, +12VOUT, 12V RTN CONN-COMPACT TEST POINT, SMD, ROHS KEYSTONE50165016-T 0ea b) SGND-1, SGND-CONN-COMPACT TEST POINT, SMD, ROHSKEYSTONE 50165016-Teac) L_PHASE, R_PHASE CONN-COMPACT TESTPOINT, SMD, ROHSKEYSTONE5016。

ISL6752_06中文资料

Pinout
ISL6752 (QSOP) TOP VIEW
VADJ 1 VREF 2 VERR 3 CTBUF 4 RTD 5 RESDEL 6 CT 7 CS 8 16 VDD 15 OUTLL 14 OUTLR 13 OUTUL 12 OUTUR 11 OUTLLN 10 OUTLRN 9 GND
FN9181.2 April 4, 2006
OVERTEMPERATURE PROTECTION
OUTLL OUTLR OUTLLN OUTLRN
VADJ
ISL6752
OSCILLATOR + 1.00V 70ns LEADING EDGE BLANKING 80mV + PWM COMPARATOR 0.33 VREF 1mA CS
3
400 VDC VIN-
R12 + Vout Q12 Q10A R1 Q10B C10 Q9A Q9B Q13 C12 L1 C15 C7
+
R13 RETURN
Q6A Q4 Q6B
Q7A Q7B
Q3
C13
ISL6752
R18
R17 R19 T2 CR1 R8 R2 R20 VADJ VREF VERR CTBUF RTD RESDEL R3 CT CS R4 Q11 R23 R24 Q14 U3 U2 R22 R21 R5 R6 C16 C6 R14 R7 U1 R24 VDD OUTLL OUTLR OUTUL OUTUR OUTLLN OUTLRN GND C11 R15 CR4 U5 U4 EL7212 C5 T4 R23 EL7212 C14
R19
FN9181.2 April 4, 2006

数字电源优势分析

开关电源技术是电力电子技术的一个重要领域，有着广阔应用前景，近年来，随着DSP 等电子器件的小型化、高速化，开关电源的控制部分正在向数字化方向发展。

用于开关电源的数字控制器已经在电力电子领域中引起了越来越多的关注，各种在模拟电路中难以实现的现代控制方法也开始应用于开关电源的控制中，大大丰富了开关电源的控制方案。

数字控制系统的概述信号处理实际就是构造信号与信号之间的传递函数，实现方法有两种：模拟方式和数字方式。

模拟方式使用电容、电阻、运算放大器等模拟器件来直接实现滤波、补偿、比较等控制功能，而数字方式则是先将模拟量数字化，再进行数字处理，然后还原成模拟信号。

（a）模拟控制开关变换器（b）数字控制开关变换器图a、b为模拟控制开关变换器与数字控制开关变换器的结构图。

两者相同的部分为功率单元和滤波单元，不同部分在于控制单元：模拟控制开关变换器采用模拟控制器，包括模拟补偿网络、脉冲宽度调制器(PWM)和斜坡信号；而数字控制开关变换器采用数字控制器，包括模数转换器(A／D Converter)、数字补偿器(Compensator)和数字脉冲宽度调制器(DPWM)。

模拟控制系统是传统的电路控制形式，经过多年研究，技术已经非常成熟。

随着电力电子技术及其控制技术的不断发展，模拟控制的局限性也越来越明显。

首先，模拟元器件的元器件老化问题和不可补偿的温漂问题，以及受环境干扰(如工作环境温度，电磁噪声等)等因素都会影响控制系统的长期稳定性。

同时，模拟控制系统需要大量的分立元件和电路板，器件数量多，制造成本高，对于每一个采用模拟控制的电路装置，其控制系统都需要专门的设计。

每一次产品的更新换代，都需要重新设计、制作它们的控制系统。

另外，目前大多数的模拟控制回路，仍采用传统的PID调节，而很少采用现代控制理论提供的控制方案。

在高性能低价格的微控制器和DSP处理器不断涌现的今天，数字控制系统的应用越来越广。

因为与传统的模拟控制器相比，基于DSP的数字控制器具有如下优点：●系统构成简单和可靠性高与模拟控制相比，完成同一任务，数字信号处理器的外围电路简单，数字控制器使用非常少的模拟元器件，解决了模拟控制中元器件老化和温漂带来的问题。

PWM控制技术的最新科技成果-介绍ISL6752

PWM控制技术的最新科技成果-----全桥零电压开关次级零电压同步整流的控制IC-ISL6752ISL6752是英赛尔公司05年最新的科技成果。

它不用移相技术就获得了初级侧的软开关拓扑，同时克服了全桥移相电路不能确保次级ZVS同步整流的毛病。

第一次做到了初，次级同时实现ZVS开关，从而实现了功率MOSFET在开关电源中的最佳工作状态。

ISL6752是一个高性能，可供选择的少引脚数ZVS全桥PWM控制器。

与英赛尔公司的ISL6551相比，它获得的ZVS工作是通过驱动上边桥MOSFET在一个固定的50%的占空比，下边桥MOSFET在跟随沿被谐振开关延迟调制的方法。

和我们熟悉的移相控制方法相比，这个方法提供了同等的效率，但是用简单的少引脚封装的IC，它还改进了过流保护和轻载时的性能。

ISL6752的特点是为了实现同步整流控制，PWM互补输出用一个外部控制电压，这个互补输出与相关的PWM输出可以在相位上动态的超前或者滞后。

这个最先进BICMOS设计特点使振荡频率可以调节到2MHz，有可调节的软启动，精确的死区时间调节和谐振延迟控制。

除此以外，多脉冲抑制确保了交替输出脉冲在低占空比可能发生的脉冲跳跃问题。

它的方框电路如图1。

图1 ISL6752控制IC 内部等效方框电路引脚说明:VDD IC的供电端子，为了免除噪声干扰加一个陶瓷旁路电容。

RTD这是振荡器定时电容放电电流控制端，接一个电阻到GND。

流过该电阻的电流决定了放电电流的大小，放电电流通常为20X该电流。

PWM的死区时间取决于定时电容的放电脉宽。

在RTD端的电压通常是2V。

CT振荡器定时电容端子，并连接到GND。

它通过内部200μΑ电流源充电,并通过可以调节的TRD控制端放电。

V ADJ用一个0-5V的电压加到此输入端来实现相位的延迟和超前。

(OUTLL与OUTLLN之间,OUTLR与OUTLRN之间)。

而OUTUL与OUTUR之间OUTUR与OUTLR之间的相位关系仍然保持,而不管OUTLL与OUTLR, OUTLLN与OUTLRN之间的相位关系。

基于Mathcad的高效率全桥DC-DC控制部分的设计

基于Mathcad的⾼效率全桥DC-DC控制部分的设计
基于Mathcad的⾼效率全桥DC-DC控制部分的设计
李臻;康龙云
【期刊名称】《新型⼯业化》
【年(卷),期】2016(006)012
【摘要】本⽂针对采⽤了先进的全桥软开关电流模式PWM控制芯⽚ISL6752控制的全桥DC-DC拓扑,使⽤Mathcad设计计算软件,简化了全桥拓扑关键控制参数的设计过程.本⽂先介绍了系统整体结构,设置了主电路的基本参数.然后,把从控制到输出的控制环路分为了三级,并分别推导了它们的等效数学模型.最后,为了验证设计的有效性,本⽂使⽤Mathcad搭建了控制系统三级组成的数学模型,并绘制了整个系统的伯德图.通过反复调试控制补偿电路参数,得到了满意的系统频率响应特性,验证了对采⽤
ISL6752芯⽚的全桥拓扑控制部分建模以及设计的准确性.
【总页数】6页(9-14)
【关键词】全桥DC-DC;ISL6752;Mathcad
【作者】李臻;康龙云
【作者单位】华南理⼯⼤学电⼒学院,⼴东⼴州510640;华南理⼯⼤学电⼒学院,⼴东⼴州 510640
【正⽂语种】中⽂
【中图分类】
【相关⽂献】
1.基于Intersil全桥ZVS控制器的⾼效率DC-DC变换器设计 [J],
2.⾼效率倍流与同步整流之⾮对称半桥DC-DC转换器设计与实现[C], 吴黎明;。

ZVS全桥控制IC-ISL6754

全桥ZVS控制PWM改进型ISL6754ISL6754比ISL6752增加了四个引脚，加入了许多更优秀的功能。

用于大功率控制电路作PWM-IC。

同样，它驱动高边MOS在各50%占空比这下工作，而两个低边MOS采用后沿调制并可调节谐振开关的延迟。

ISL6754比ISL6752增加了软启动功能端（SS），平均电流信号可以用于平均电流限制，电流均衡控制，及平均电流型控制的PWM。

此外ISL6754也可以支持电压型控制，它控制二次侧的同步整流时可以更好地做到ZVS模式。

ISL6754有更准确的死区时间和谐振延迟控制，振荡器最高到2MHZ，此外，多脉冲抑制可以确保两交替输出的脉冲正常进入跳周期模式工作，此为降低空载功耗。

主要特点列出如下：* 调节谐振延迟，确保ZVS开关。

* 同步整流驱动可调延迟。

* 可以电压型，也可以电流型控制。

* 3%的限流阀值。

* 可调平均电流限制。

* 可调死区时间控制。

* 175uA的起动电流。

* VCC供电的UVLO保护。

* 可高达2MHZ的工作频率。

* 芯片过热保护。

* 振荡器锯齿波输出缓冲器。

* 最快速电流检测。

* 逐个周期式限流保护。

* 70ns的前沿消隐。

（电流型）* 多脉冲抑制。

ISL6754内部电路框图如图1，典型应用电路如图2。

图1 ISL6754内部等效方框电路图2 ISL6754基本应用电路各引脚功能如下：*VDD---IC供电端，加旁路电容到GND。

用瓷介电容紧靠VDD和GND。

*GND---IC公共端，信号地，功率地采用一个端子。

由于在高峰值电流及高频工作台，必须要一个低阻抗布局接地线尽量短。

*VREF---5V基准电压端。

有3%的偏差。

要用0.1---2.2uF的瓷电容旁路。

*CT---振荡器定时电容端。

外接于此端到GND，由内部200uA电流源充电，放电速率由RTD电阻决定。

*RTD---振荡器定时电容放电电阻，接于此端到地。

决定CT电流放电幅度，最小为20*电阻电流。

中文ISL6752

i L S (t ) = I S ⋅ cos ω m (t − t 4 )
LS 其中： Z m = ， ωm = C1 + C4
1 LS (C1 + C4 )
边界条件： t4时刻，uC 4 (t 4 ) = Vin ， iLS (t 4 ) = I S = I m + I o
Np Ns
状态五：状态五： UR仍开通，UL、LL、LR仍关断。
特殊引脚及功能（）特殊引脚及功能（2）
VADJ：这个引脚上这个引脚上0~5V的电压是用来设置的电压是用来设置OUTLLN相对于相对于OUTLL、的电压是用来设置相对于、 OUTLRN相对于相对于OUTLR的相位超前与滞后时间。的相位超前与滞后时间。相对于的相位超前与滞后时间 2.425V以下的电压，OUTLLN/OUTLRN的相位超前于以下的电压，以下的电压的相位超前于 OUTLL/OUTLR。。 2.575V以上的电压，OUTLLN/OUTLRN的相位滞后于以上的电压，以上的电压的相位滞后于 OUTLL/OUTLR。。 2.5+/-0.75V之间的电压，OUTLLN/OUTLRN的相位与之间的电压，之间的电压的相位与 OUTLL/OUTLR的相位相同。的相位相同。的相位相同相位超前与滞后的范围是0ns或者或者40~300ns之间，随着与之间，相位超前与滞后的范围是或者之间随着与2.5V 电压差的增加，超前与滞后的相位差也会增大。电压差的增加，超前与滞后的相位差也会增大。控制电压与相位差的关系是非线性的，当控制电压接近2.5V时，电压增益位差的关系是非线性的，当控制电压接近时（△t/△v）是很小的，并且会随着电压接近控制极限而很快地 △ ）是很小的，增大。增大。

UCC3895

更新观念用新技术设计最优秀的电源从2003年以来，电源控制IC展示出了全新的面貌。

新的隔离控制IC达100余款，非隔离DC/DC达几百款。

但是我们国内的技术还是老面孔。

工程师选用的还是十几，二十年前的老式IC，电路模式仍旧是老样子。

我在这里给出几个最新的例子，看看现在的技术进步。

1，两相交错式PFC控制, UCC28060和UCC28070。

先看看UCC28060组成的300W的CRM的PFC电路，有效地减小了输出电压的纹波，减小了输入端的峰值电流，减小了EMI的强度，提高了效率。

再看看UC28070组成的1200W的CCM的大功率PFC电路，输入可以采用600W的EMI滤波电路，升压电感的感量比单相的小两倍，输出电容的容量可以小一半，输出纹波小一半，效率提高大约0.4 -0.5% 。

采用无整流桥的PFC电路在低端AC电压115V输入时提高效率约1%。

而且解决了EMI的问题。

下面是NCP1653控制的EMI过关的无桥PFC电路。

再看看NCP1606控制的小功率CRM方式的最新的PFC电路，多么简单！再看看ICE1PCS01控制的CCM的PFC电路，外围元件简化了多少！2, 反激变换器采用准谐振有高压起动源的NCP1337 比采用UC3842的电路简单，易于控制，转换效率高，EMI强度低。

高压起动源直接接在高压输入端，光耦直接接到IC的端子，不再处理放大器的补偿，前沿消隐做在IC内部，IC外部只有电流取样。

有关UC3842的应用电路太多了，看看起动电路，放大器补偿电路，占空比超过50%时另外加入的斜率补偿电路，就知道NCP1337应用起来简单多少了。

如果是DC/DC的应用，可以选择LTC3803，下面是LTC3803的应用电路。

其外部只有6个引脚，几乎无须调试，设计好变压器就可以了。

输入输出之间加入光耦隔离也很简单。

3，有源箝位正激电路。

采用新一代具有软关断技术的NCP1562，UCC2891取代旧有的UCC3580。

各种电路拓朴的同步整流技术

3
3
3
C43 0805 102/100V
3
3
3
C44 0805 102/100V
R29
R30
R31
0603
0603
0603
4.7R
4.7R
4.7R
R32
R33
R34
0603
0603
0603
4.7R
4.7R
4.7R
C35
C36
C37
C38
C39
C40
C41
C42
106/50V 106/50V 106/50V 106/50V 106/50V 106/50V 106/50V 106/50V
检测栅驱动技术等）。
控制IC方式的同步整流
IR1167
主要特色有： * 适应反激变换器的DCM，CRM及CCM三种模式工
作。适应LLC式半桥。 * 最高500KHz工作频率。 * 2A源出5A漏入的输出驱动的能力。 * 栅驱动输出电压在10.7V到14.5V。 * Vcc电压从11.3V到20V。 * 50ns关断比例延迟。 * 直接检测MOSFET的源漏电压。
0603
33R 33R 33R
105/16V
VSS 7
C32 0805 2
471/100V
Trans4
LI 6
LR 8 LO HI 5 UCC27200
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2 1
3 2 1
3 2 1
3 2 1
3 2 1
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1N4148
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0603 PBSS4350 VCC
2K
L4 18uH Inductor Iron Dot

开关电源的容差分析报告

GERM4815T 容差分析报告项目负责人：梁立敏1.输出过压保护输出过压保护原理图如图1。

通过输出电压OUT+反馈取样电压到单片机U16的24脚，判断输出过压，22脚PWM-OFF 始终输出低电平使电源过压锁死。

图1 输出过压保护、过温、副边限流保护原理图U16设定过压保护值为59.5V ，无容差时24脚理论电平为：59.5÷（33000+33000+4700）×4700=3.955V贴片电阻R50、R51、R54的容差为1%。

当R50偏小1%，R51、R54偏大1%时，为过压保护点的上限值，该值为：V 6.60%)]11(330002%)11(47000[%)11(47000955.3=+⨯+-⨯-当R50偏大1%，R51、R54偏小1%时，为过压保护点的下限值，该值为：V 4.58%)]11(330002%)11(47000[%)11(47000955.3=-⨯++⨯+由于电阻容差，输出过压保护点的理论范围为：58.4V ～60.6V 。

技术要求范围：58.5V ～60.5V 。

所有电阻同时偏小或偏大到最大值1%的可能性接近零，所以实际测量值一定在范围内。

2.输出过温保护电源输出过温保护电路如图1，温度电阻RT1随温度的变化而变化。

通过RT1和R49分压取样基准VDD 到U16的25脚，由RT1的阻值与温度的关系（如图2）设定过温保护点。

RT1固定在输出整流管D35上，D35高温50℃满载工作温度为82℃。

软件为10位二进制模拟采样，即将VDD 5V 分为1023份，即10231210=-。

程序设定过温保护值为766，所以过温保护点无容差时25脚的电压为：5÷1023×766=3.743V25脚为3.743V时，RT1的阻值为：5×10000÷3.743-10000=3358Ω对应图2中100℃，即当RT1的温度达到100℃时，U16检测到25脚电压为3.743V 时判定过温保护，PWM-OFF发出低电平，关断电源输出。

intersil ISL6752 说明书

®CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 兼有可调性的同步整流控制及ZVS 全桥式电流模式PWM 控制器ISL6752是高性能, 少引脚的零电压 (ZVS)全桥式脉冲宽度(PWM)控制器。

与Intersil 的ISL6551相似, 通过上层开关启动于固定的50%占空比, 下层开关调整脉冲宽度于后沿, 它能实现ZVS 运行。

与熟悉的相位位移控制方法(Phase-Shifted)比较, 这个方法用较少数目引脚的包装, 相应简单地提供同等的效率性能以及改善的过流保护和轻载性能。

ISL6752为同步整流控制具备互补PWM 输出端。

利用外部控制电压, 这些互补的输出端可以动态地被前置或者延迟。

这个先进的BiCMOS 设计不但兼容了精确的死区时间控制以及共振延迟控制, 而且具有一个可调振荡器其频率高达2MHz。

另外, 当跳脉冲可能发生的情况下, 多相脉冲抑制能在低工作周期时保证相应的输出脉冲。

定购资料零件号码温度范围(°C)包装包装图号 #ISL6752AAZA(Note)-40 to 10516 Ld QSOP (Pb-free)M16.15AAdd -T suffix to part number for tape and reel packaging.NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.主要特点• ZVS 运行可调共振延迟 • 延迟/前置可调的同步整流控制输出 • 电流摸式控制 • 3%限流临界 • 可调死区时间控制 • 175µA 启动电流• 输入电源欠压切断保护 • 可调振荡频率高达2MHz • 内部过温保护 • 缓冲振荡锯齿输出 • 快电流传感延迟 •可调周期性峰值限流电流 • 70ns 上升沿消隐 •多脉冲抑制• 不含铅 (RoHS Compliant)•ELV, WEEE, and RoHS Compliant应用• ZVS 全桥转换器 •电信和信息电源 • 无线基站电源 • 档案服务器电源 • 工业动力系统插脚引线ISL6752 (QSOP)顶视图14151691312111012345768VAD JVREF VERR CTBUF RTD RESD ELCSCT VDD OUTLR OUTUL OUTUR OUTLLN OUTLRN GNDOUTLL/Intersil额定值Supply Voltage, VDD ----------------GND - 0.3V to +20.0V OUTxxx ------------------------------------GND - 0.3V to VDD Signal Pins-------------------------GND - 0.3V to V REF +0.3V Peak GATE Current -----------------------------------------0.1A ESD ClassificationHuman Body Model (Per MIL-STD-883 Method 3015.7)------3000VCharged Device Model (Per EOS/ESD DS5.3, 4/14/93)-------1000V运行条件Supply Voltage Range (Typical)------------------9V-16VDC Temperature RangeISL6752AAxx-------------------------------40o C to 105oC热性能的资料Thermal Resistance Junction to Ambient (Typical) θJA (oC/W) 16 Lead QSOP (Note 1)-------------------------------------105Maximum Junction Temperature -------------------55o C to 150oCMaximum Storage Temperature Range-----------65o C to 150oCMaximum Lead Temperature (Soldering 10s)--------------300oC (QSOP – Lead Tips Only)CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Notes:1) θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.2)All voltages are with respect to GND.Electrical SpecificationsRecommended Operating Conditions, Unless Otherwise Noted. Refer to Block Diagram and Typical Application Schematic.9V < V DD < 20V, RTD = 10.0k Ω, CT = 470pF, T A = -40o C to 105o C (Note 3), Typical values are at T A = 25o C.PARAMETER TEST CONDITIONS MIN TYP MAX UNITSSUPPLY VOLTAGE Supply Voltage- - 20 V Start-Up Current, I DDV DD = 5.0V-175400µA Operating Current, I DDR LOAD , C OUT =0 -11.015.5mA UVLO START Threshold 8.00 8.75 9.00 V UVLO STOP Threshold6.507.007.50VHysteresis- 1.75 -VREFERENCE VOLTAGE Overall Accuracy I VREF = 0-10mA4.8505.000 5.150 V Long Term StabilityT A = 125oC, 1000 hours (Note 4) - 3 - mV Operational Current (source) -10 - - mA Operational Current (sink)5 - - mA Current Limit VREF = 4.85V-15--100mACURRENT SENSE Current Limit Threshold VERR = VREF 0.97 1.00 1.03 V CS to OUT DelayExcl. LEB (Note 4) - 35 50 ns Leading Edge Blanking (LEB) Duration (Note 4)5070100nsCS to OUT Delay + LEBT A = 25oC - - 130 ns CS Sink Current Device Impedance V CS = 1.1V - - 20 Ω Input Bias CurrentV CS = 0.3V-6.00 - -2.00 µA电气规范/Intersil9V < V DD < 20V, RTD = 10.0kΩ, CT = 470pF, T A = -40o C to 105o C (Note 3), Typical values are at T A= 25o C. (continued)PARAMETER TESTCONDITIONSMINTYPMAXUNITSCS to PWM Comparator Input Offset T A = 25o C 658095mV PULSE WIDTH MODULATORVERR Pull-Up Current Source VERR = 2.50V 0.80 1.00 1.30 mAVERR VOH I LOAD = 0mA 4.20 - - VMinimum Duty Cycle VERR < 0.6V - - 0 %VERR = 4.20V, V CS = 0V (Note 5) - 94 - %RTD = 2.00kΩ, CT = 220pF - 97 - %Maximum Duty Cycle (per half-cycle)RTD = 2.00kΩ, CT = 470pF - 99 - %Zero Duty Cycle VERR Voltage 0.85 - 1.20 VVERR to PWM Comparator Input Offset T A = 25o C 0.70.80.9V VERR to PWM Comparator Input Gain 0.31 0.33 0.35 V/VCommon Mode (CM) Input Range (Note 4) 0 - 4.45 VOSCILLATOR165 183 201 KHzFrequency Accuracy, Overall (Note 4)-10 - 10 %Frequency Variation with VDD T A = 25o C, (F20V - F10V)/F10V -0.31.7%VDD = 10V, |F-40o C – F0o C|/F0o C -4.5-%Temperature Stability|F0o C – F105o C|/F25o C (Note 4) - 1.5 - %Charge Current T A = 25o C -193 -200 -207 µADischarge Current Gain 19 20 23 µA/ µACT Valley Voltage Static Threshold 0.75 0.80 0.88 VCT Peak Voltage Static Threshold 2.75 2.80 2.88 VCT Pk-Pk Voltage Static Value 1.92 2.00 2.05 VRTD Voltage 1.97 2.00 2.03 VRESDEL Voltage Range 0 - 2.00 VCTBUF Gain (V CTBUFp-p/V CTp-p) V CT = 0.8V, 2.6V 1.95 2.0 2.05 V/VCTBUF Offset from GND V CT = 0.8V 0.34 0.40 0.44 VCTBUF VOH ∆V(I LOAD = 0mA, I LOAD = -2mA), V CT =2.6V- -0.10VCTBUF VOL ∆V(I LOAD = 2mA, I LOAD = 0mA), V CT =0.8V- -0.10VOUTPUTHigh Level Output Voltage (VOH) I OUT = -10mA, VDD - VOH - 0.5 1.0 V Low Level Output Voltage (VOL) I OUT = 10mA, VOL - GND - 0.5 1.0 V Rise Time C OUT = 220pF, VDD = 15V (Note 4) - 110 200 ns Fall Time C OUT = 220pF, VDD = 15V (Note 4) - 90 150 ns UVLO Output Voltage Clamp VDD = 7V, I LOAD = 1mA (Note 6) - - 1.25 VOutput Delay/Advance Range VADJ = 2.50V (Note 4) - - 3 ns/Intersil9V < V DD < 20V, RTD = 10.0kΩ, CT = 470pF, T A = -40o C to 105o C (Note 3), Typical values are at T A= 25o C.V ADJ < 2.425V -40 - -300 nsOUTLLN/OUTLRN relative toOUTLL/OUTLRV ADJ > 2.575V 40 - 300 nsOUTLxN Delayed 2.575 - 5.000 VDelay/Advance Control Voltage RangeOUTLLN/OUTLRN relative toOUTLL/OUTLR OUTLxN Advanced 0 - 2.425 VT A = 25o C (OUTLx Delayed)V ADJ = 0V280 300 320 nsV ADJ = 0.5V 92 105 118 nsV ADJ = 1.0V 61 70 80 nsV ADJ = 1.5V 48 55 65 nsV ADJ = 2.0V 41 50 58 nsT A = 25o C (OUTLx NDelayed)V ADJ = VREF280 300 320 nsV ADJ = VREF - 0.5V 86 100 114 nsV ADJ = VREF - 1.0V 59 68 77 nsV ADJ = VREF - 1.5V 47 55 62 nsV ADJ Delay TimeV ADJ = VREF - 2.0V 41 48 55 ns THERMAL PROTECTIONThermal Shutdown (Note 4) 130 140 150 o C Thermal Shutdown, Clear (Note 4) 115 125 135 o C Hysteresis, Internal Protection (Note 4) - 15 - o C NOTES:3. Specifications at -40o C are guaranteed by 25o C test with margin limits.4. Guaranteed by design, not 100% tested in production.5. This is the maximum duty cycle achieveable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may beobtained using other values for these components. See Equation 1-3.6. Adjust VDD below the UVLO stop threshold prior to setting at 7V./Intersil各管脚简介VDDVDD是控制器的电源输入端。

ZVS 全桥调试指南AN1262 Intersil

针对ISL6752、ISL6753 ZVS全桥控制器的设计应用笔记 2006年8月15前言ZVS（零电压开关）全桥拓扑已经出现多年，并且已成为业界主流。

这种结构的主要缺点就是需要一个附加的特定波形发生器来生成正确的栅极驱动信号。

使用英特矽尔半导体（Intersil）公司的ISL6752和ISL6753等器件，就可以克服上述缺点。

使用这些器件，不仅可以使设计人员简化ZVS全桥控制器的设计，还可以带来额外的好处。

适用范围本文提供了在使用ISL6752和ISL6753等器件设计ZVS全桥结构时的一些有用信息和技巧，这些技巧包括设置谐振时间和同步整流器时序。

更多有用信息，请参阅应用笔记AN1002和AN1246。

谐振时间和能量对ZVS全桥结构进行的关键操作之一就是基于谐振时间要求来设置打开下管的延时。

这个操作可以通过调节该IC上的RESDEL管脚上的电压来实现。

在初始时刻，在变换器上电之前，将RESDEL管脚上的电压设置为1.8V，这样就在上管关断与下管打开之间设置了较大的延时。

推荐在这个过程中，暂时禁用同步整流器。

禁用的方法，参见第三页的“同步整流器”一节。

上述调整步骤完成后，缓慢增加ZVS全桥的供电电压，保持负载处于最小的电流状态。

同时监测上管的栅－源压降和对角位置的下MOSFET的栅－源、漏－源压降。

图1 给出了ZVS全桥上的电压波形。

Upper MOSFET：上管Lower MOSFET：下管Lower MOSFET D－S voltage：下管D－S压降Resonant Delay：谐振延时Resonant Cycle：谐振周波On：开Off：关Time ：时间图 1 谐振延时和转换下管漏－源之间的压降波形应该能够清楚的看出谐振周波，下管打开的时间故意滞后于谐振过渡的时段。

如果没有看到谐振周波，略微增大负载电流。

谐振是由于变压器的漏感和漏源寄生电容导致的。

该电容取决于MOSFET的电容大小。

针对ISL6752、ISL6753 ZVS 全桥控制器的设计

` 针对ISL6752、ISL6753 ZVS全桥控制器的设计应用笔记 2006年8月15前言ZVS（零电压开关）全桥拓扑已经出现多年，并且已成为业界主流。

这种结构的主要缺点就是需要一个附加的特定波形发生器来生成正确的栅极驱动信号。

使用Intersil公司的ISL6752和ISL6753等器件，就可以克服上述缺点。

使用这些器件，不仅可以使设计人员简化ZVS全桥控制器的设计，还可以带来额外的好处。

适用范围本文提供了在使用ISL6752和ISL6753等器件设计ZVS全桥结构时的一些有用信息和技巧，这些技巧包括设置谐振时间和同步整流器时序。

更多有用信息，请参阅应用笔记AN1002和AN1246。

谐振时间和能量对ZVS全桥结构进行的关键操作之一就是基于谐振时间要求来设置打开下MOSFET管的延时。

这个操作可以通过调节该IC上的RESDEL管脚上的电压来实现。

在初始时刻，在变换器上电之前，将RESDEL管脚上的电压设置为1.8V，这样就在上MOSFET管关断与下MOSFET管打开之间设置了较大的延时。

推荐在这个过程中，禁用同步整流器。

禁用的方法，参见第三页的“同步整流器”一节。

上述调整步骤完成后，缓慢增加ZVS全桥的供电电压，保持负载处于最小的电流状态。

同时监测上MOSFET管的栅－源压降和对角位置的下MOSFET的栅－源、漏－源压降。

图1 给出了ZVS全桥上的电压波形。

Upper MOSFET：上MOSFETLower MOSFET：下MOSFET（这里的上下是对角的――译注）Lower MOSFET D－S voltage：下MOSFET的D－S压降Resonant Delay：谐振延时Resonant Cycle：谐振周波On：开Off：关Time ：时间图 1 谐振延时和转换下MOSFET管上的漏－源之间的压降波形应该能够清楚的看出谐振周波，下MOSFET管打开的时间故意滞后于谐振过渡的时段。

恒流恒压稳压电源的设计与制作

恒流恒压稳压电源的设计与制作摘要：。

本人设计的此直流恒流恒压电源是将交流电压转化为输出电压电流稳定的直流电源，电路的特点是：当负载电阻小于25欧姆时，输出为恒流，也即恒流源，有0.3A和0.6A两个档位。

当负载电阻大于25欧姆时，输出为恒压，也即电源为恒压源，有9V.12V和15V三个档位。

关键词：直流电源恒压源恒流源工作原理0 引言随着电子技术的发展，特别是电子计算机技术应用到各工业、科研领域后，各种电子设备都要求稳定的直流恒流恒压电源供电，电网直接供电已不能满足需要，直流恒流恒压电源的出现解决了这一问题。

目前直流恒流恒压电源的发展更快，它的种类繁多，功能不同应用非常广泛。

我们日常生活中的许多电器设备中都含有直流电源。

直流恒流恒压电源易于设计、配置、稳定、调节，随着电器的不断发展，它的应用会更多。

种类及功能都会进一步发展，以满足人们的需要。

通过直流稳压电源设计,把所学的知识用于实践，了解一些电子产品的设计原理,可以达到触类旁通的功效。

1 其它电源的发展近些年来，随着电子技术的迅猛发展，开关稳压电源已作为一种较理想的电源为人们所使用。

然而当前的开关稳压电源，虽然体积小，效率高，但输出电压的纹波较大Ⅲ，难以保证输出电压的高稳定性。

非隔离DC／DC技术发展也非常迅速。

现在的非隔离的DC/DC基本上分成两大类。

一是在内部含有功率开关元件，称DC/DC转换器；二是不含功率开关．需要外接功率MOSFET，称DC/DC控制器按照电路功能划分有降压的BUCK、升压BOOST，还有升降压的BUCK—BOOST等．以及正压转负压的INVERTOR等。

其中品种最多芨展最快的是BUCK型。

控制方式以PWM为主。

1．1 初级PWM控制IC不断优化有源筘位技术自从2002年VICOR公司此项专利技术到期解禁之后新型有源箝位控制IC纷纷涌现。

在大功率领域，全桥移相ZVS软开关技术在解决开关电源的效率上功不可没。

INTERSIL公司推出的PWM 对称全桥的ZVS控制IC—ISL6752,既能控制初级侧的四个MOS开关为ZVS工作状态，又能准确地给出控制二次侧的同步整流为ZVS工作状态的驱动信号。

ISL6752AAZA-T中文资料

Add -T suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
VIN+
Q1
T3 1:1:1
Q2
Q5
Q6
R13
CR2
CR3
R12
T1 Np:Ns:Ns=9:2:2
Ns Np C10 Q9A Q9B Ns Q16
R15 + Vout L1
4
Q10A Q10B + 400 VDC C1 T4 1:1:1 Q4 Q7A Q7B C8 C9 R10 R11 Q3 Q8A Q8B C11 R14 CR4 CR5 Q11A Q11B C7 Q12A Q12B VINVREF R7 T2 CR1 R8 VADJ VREF VERR CTBUF R9 RTD RESDEL CT R1 R6 U1 CS VDD OUTLL OUTLR OUTUL OUTUR OUTLLN OUTLRN GND

BL6552三相电能监测及分析专用芯片数据手册说明书

BL6552三相电能监测及分析专用芯片数据手册V1.12目录1、产品简述 (6)2、基本特征 (7)2.1主要特点 (7)2.2系统框图 (8)2.3管脚排列 (9)2.4性能指标 (10)2.4.1 电参数性能指标 (10)2.4.2 极限范围 (11)3、工作原理 (12)3.1电流电压波形产生原理 (12)3.1.1 有功相位补偿 (13)3.1.2 通道偏置校正 (14)3.1.3 通道增益校正 (14)3.1.4 电流电压波形输出 (15)3.2有功功率计算原理 (16)3.2.1 有功功率输出 (17)3.2.2 有功功率校准 (17)3.2.3 有功功率的防潜动 (18)3.2.4 有功功率小信号补偿 (19)3.2.5 有功功率选择 (19)3.3有功能量计量原理 (20)3.3.1 有功能量输出 (20)3.3.2 有功能量脉冲输出选择 (21)3.3.3 有功电能脉冲输出比例 (22)3.4电流电压有效值计算原理 (23)3.4.1 有效值输出 (23)3.4.2 有效值输入信号的设置 (24)3.4.3 有效值刷新率的设置 (24)3.4.4 电流电压有效值校准 (24)3.4.5 有效值的防潜动 (25)3.5快速有效值检测原理 (26)3.5.1快速有效值输出 (26)3.5.2 快速有效值输入选择 (26)3.5.3 快速有效值累计时间 (27)3.5.4 电网频率选择 (27)3.6无功计算 (27)3.6.2 无功功率输出 (29)3.6.3 无功功率校准 (29)3.6.4 无功功率的防潜动 (30)3.6.5 无功功率小信号补偿 (31)3.6.6 无功能量输出 (31)3.7视在和功率因子计算 (32)3.7.1 视在功率和能量输出 (32)3.7.2 视在功率校准 (33)3.7.3 功率因子 (33)3.8三相电流和的计算 (34)3.8.1 电流和的输出 (34)3.8.2 电流和的调整 (34)3.8.3 电流和的比较 (34)3.9小信号补偿 (35)3.10电参数测量 (36)3.11.1 线周期计量 (36)3.11.2 线频率计量 (36)3.11.3 相角计算 (36)3.11.4 功率符号位 (37)3.11故障检测 (38)3.12.1 过零检测 (38)3.12.2 峰值超限 (38)3.12.3 线电压跌落 (39)3.12.4 过零超时 (41)3.12.5 过零指示 (42)3.12.6 电源供电指示 (42)4、内部寄存器 (44)4.1电参量寄存器（外部读） (44)4.2校表寄存器1 (46)4.3校表寄存器2 (48)4.4校表寄存器详细说明 (50)4.4.1 通道PGA增益调整寄存器 (50)4.4.2 相位校正相关寄存器 (50)4.4.3 有效值增益调整寄存器 (52)4.4.3 有效值偏置校正寄存器 (52)4.4.4 功率小信号补偿寄存器 (53)4.4.6 快速有效值相关设置寄存器 (55)4.4.7 故障检测相关寄存器 (55)4.4.8 ADC使能控制 (55)4.4.9 模式寄存器1 (55)4.4.10 模式寄存器2 (56)4.4.11 模式寄存器3 (56)4.4.12 中断状态寄存器 (57)4.4.13 中断屏蔽寄存器 (58)4.4.14 能量读后清零设置寄存器 (59)4.4.15 用户写保护设置寄存器 (59)4.4.16 软复位指令 (59)4.4.17 通道增益调整寄存器 (59)4.4.18 通道偏置调整寄存器 (60)4.4.19 功率增益调整寄存器 (61)4.4.20 功率偏置调整寄存器 (61)4.4.21 CF缩放比例寄存器 (62)4.4.22 AT1~3逻辑输出管脚配置寄存器 (63)4.5电参数寄存器详细说明 (64)4.5.1 波形寄存器 (64)4.5.2 有效值寄存器 (65)4.5.3 快速有效值寄存器 (65)4.5.4 有功功率寄存器 (66)4.5.5 无功功率寄存器 (67)4.5.6 视在功率寄存器 (67)4.5.7 电能脉冲计数寄存器 (68)4.5.8 波形夹角寄存器 (70)4.5.9 功率因数寄存器 (70)4.5.10 线电压频率寄存器 (71)5、通讯接口 (72)5.1SPI (72)5.1.1 概述 (72)5.1.2 工作模式 (72)5.1.3 帧结构 (72)5.1.4 读出操作时序 (74)5.1.5 写入操作时序 (74)5.1.6 SPI接口的容错机制 (75)5.2 UART (76)5.2.1 概述 (76)5.2.2 每个字节格式 (76)5.2.3 读取时序 (76)5.2.4 写入时序 (77)5.2.5 UART接口的保护机制 (77)6、封装信息 (78)6.1订单信息 (78)6.2封装 (78)6.3封装外观 (78)1、产品简述BL6552是一颗7通道三相电能监测及分析芯片，适用于三相智能断路器、三相导轨表、电测仪表、大功率设备电源监控等应用，具有较高的性价比。

一种全桥副边整流控制电路[发明专利]

专利名称：一种全桥副边整流控制电路专利类型：发明专利
发明人：陈学文,蒋中为
申请号：CN201310344683.8
申请日：20130809
公开号：CN104348336A
公开日：
20150211
专利内容由知识产权出版社提供
摘要：本发明提供一种全桥副边整流控制电路，利用ISL6752　PWM控制器，由ISL6752　PWM的驱动上管的输出脚OUTUL和OUTUR分别作为同步整流的驱动，包括上左输出控制电路和上右输出控制电路；这两个电路是一样的，由空载判断信号SDROFF控制是否将ISL6752　PWM的驱动上管的输出脚OUTUL和OUTUR输出放大。

本发明的电路简单，由空载判断信号SDROFF控制
ISL6752　PWM的驱动上管的输出脚OUTUL和OUTUR信号是否输出，并具有死区控制电路。

申请人：深圳市金威源科技股份有限公司
地址：518000 广东省深圳市宝安区新安街道宝城68区留仙二路丰业源工业厂区B2栋厂房一、二、五楼
国籍：CN
代理机构：深圳市百瑞专利商标事务所(普通合伙)
代理人：金辉
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