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FPGA可编程逻辑器件芯片5CGXFC4F6M11C7N中文规格书

Board LayoutSince spread spectrum affects the m counter values, all spread-spectrumPLL outputs are effected. Therefore, if only one spread-spectrum signal isneeded, the clock signal should use a separate PLL without other outputsfrom that PLL.No special considerations are needed when using spread spectrum withthe clock switchover feature. This is because the clock switchover featuredoes not affect the m and n counter values, which are the counter valuesswitching when using spread spectrum.Board Layout The enhanced and fast PLL circuits in Stratix II and Stratix II GX devicescontain analog components embedded in a digital device. These analogcomponents have separate power and ground pins to minimize noisegenerated by the digital components. Stratix II and Stratix II GXenhanced and fast PLLs use separate V CC and ground pins to isolatecircuitry and improve noise resistance.V CCA and GNDAEach enhanced and fast PLL uses separate V CC and ground pin pairs fortheir analog circuitry. The analog circuit power and ground pin for eachPLL is called VCCA_PLL<PLL number> and GNDA_PLL<PLL number>.Connect the V CCA power pin to a 1.2-V power supply, even if you do notuse the PLL. Isolate the power connected to V CCA from the power to therest of the Stratix II or Stratix II GX device or any other digital device onthe board. You can use one of three different methods of isolating theV CCA pin: separate V CCA power planes, a partitioned V CCA island withinthe V CCINT plane, and thick V CCA traces.Separate V CCA Power PlaneA mixed signal system is already partitioned into analog and digitalsections, each with its own power planes on the board. To isolate the V CCApin using a separate V CCA power plane, connect the V CCA pin to theanalog 1.2-V power plane.Partitioned V CCA Island Within V CCINT PlaneFully digital systems do not have a separate analog power plane on theboard. Since it is expensive to add new planes to the board, you can createislands for VCCA_PLL. Figure1–35 shows an example board layout withan analog power island. The dielectric boundary that creates the islandshould be 25 mils thick. Figure1–36 shows a partitioned plane withinV CCINT for V CCA.Advanced Featuresthe primary to the secondary clock for PLL reference. The design sendsout the clk0_bad, clk1_bad, and the clk_loss signals from the PLLto implement a custom switchover circuit.Figure1–17.Automatic Clock Switchover Circuit Block DiagramThere are two possible ways to use the clock switchover feature.■Use the switchover circuitry for switching from a primary tosecondary input of the same frequency. For example, in applicationsthat require a redundant clock with the same frequency as theprimary clock, the switchover state machine generates a signal thatcontrols the multiplexer select input shown on the bottom ofFigure1–17. In this case, the secondary clock becomes the referenceclock for the PLL. This automatic switchover feature only works forswitching from the primary to secondary clock.■Use the CLKSWITCH input for user- or system-controlled switchconditions. This is possible for same-frequency switchover or toswitch between inputs of different frequencies. For example, ifinclk0 is 66 MHz and inclk1 is 100 MHz, you must control theswitchover because the automatic clock-sense circuitry cannotmonitor primary and secondary clock frequencies with a frequencydifference of more than 20%. This feature is useful when clocksources can originate from multiple cards on the backplane,requiring a system-controlled switchover between frequencies ofoperation. You should choose the secondary clock frequency so thePLLs in Stratix II and Stratix II GX DevicesTable1–11 shows the physical pins and their purpose for the fast PLLs.For inclk port connections to pins, see “Clocking” on page1–62.Table1–11.Fast PLL Pins(Part 1 of2)Note(1)Pin DescriptionCLK0p/n Single-ended or differential pins that can drive the inclk port for PLLs 1, 2, 7 or 8.CLK1p/n Single-ended or differential pins that can drive the inclk port for PLLs 1, 2, 7 or 8.CLK2p/n Single-ended or differential pins that can drive the inclk port for PLLs 1, 2, 7 or 8.CLK3p/n Single-ended or differential pins that can drive the inclk port for PLLs 1, 2, 7 or 8. CLK8p/n Single-ended or differential pins that can drive the inclk port for PLLs 3, 4, 9 or 10. CLK9p/n Single-ended or differential pins that can drive the inclk port for PLLs 3, 4, 9 or 10. CLK10p/n Single-ended or differential pins that can drive the inclk port for PLLs 3, 4, 9 or 10. CLK11p/n Single-ended or differential pins that can drive the inclk port for PLLs 3, 4, 9 or 10. FPLL7CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 7.FPLL8CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 8.FPLL9CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 9.FPLL10CLKp/n Single-ended or differential pins that can drive the inclk port for PLL 10.PLL_ENA Dedicated input pin that drives the pllena port of all or a set of PLLs. If you do not use this pin, connect it to GND.VCCD_PLL Digital power for PLLs. Y ou must connect this pin to 1.2 V, even if the PLL is not used. VCCA_PLL1Analog power for PLL 1. Y ou must connect this pin to 1.2 V, even if the PLL is not used. GNDA_PLL1Analog ground for PLL 1. Y our can connect this pin to the GND plane on the board. VCCA_PLL2Analog power for PLL 2. Y ou must connect this pin to 1.2 V, even if the PLL is not used. GNDA_PLL2Analog ground for PLL 2. Y ou can connect this pin to the GND plane on the board.VCCA_PLL3Analog power for PLL 3. Y ou must connect this pin to 1.2 V, even if the PLL is not used. GNDA_PLL3Analog ground for PLL 3. Y ou can connect this pin to the GND plane on the board. VCCA_PLL4Analog power for PLL 4. Y ou must connect this pin to 1.2 V, even if the PLL is not used. GNDA_PLL4Analog ground for PLL 4. Y ou can connect this pin to the GND plane on the board. GNDA_PLL7Analog ground for PLL 7. Y ou can connect this pin to the GND plane on the board.VCCA_PLL8Analog power for PLL 8. Y ou must connect this pin to 1.2 V, even if the PLL is not used. GNDA_PLL8Analog ground for PLL 8. Y ou can connect this pin to the GND plane on the board.VCCA_PLL9Analog power for PLL 9. Y ou must connect this pin to 1.2 V, even if the PLL is not used. GNDA_PLL9Analog ground for PLL 9. Y ou can connect this pin to the GND plane on the board. VCCA_PLL10Analog power for PLL 10. Y ou must connect this pin to 1.2 V, even if the PLL is not used.。

瑞通电子线性单元Li-Ion电池充电IC说明书

DS9524-01 April 2011Ordering InformationNote :Richtek products are :` RoHS compliant and compatible with the current require-ments of IPC/JEDEC J-STD-020.` Suitable for use in SnPb or Pb-free soldering processes.Pin ConfigurationsWDFN-10L 3x2(TOP VIEW)Linear Single Cell Li-Ion Battery Charger IC for Portable ApplicationsGeneral DescriptionThe RT9524 is a fully integrated single cell Li-ion battery charger IC ideal for portable applications. The RT9524optimizes the charging task by using a control algorithm including pre-charge mode, fast charge mode and constant voltage mode. the input voltage range of the VIN pin can be as high as 28V. When the input voltage exceeds the OVP threshold, it will turn off the charging MOSFET to avoid overheating of the chip.In RT9524, the maximum charging current can be programmed with an external resistor. For USB application,the user can set the current to 100mA/500mA through the EN/SET pin. For the factory mode, the RT9524 can allow 4.2V/2.3A power pass through to support system operation. It also provides a 50mA LDO to support the power of peripheral circuit. The internal thermal feedback circuit regulates the die temperature to optimize the charge rate for all ambient temperatures. The RT9524provides protection functions such as under voltage protection, over voltage protection for VIN supply and thermal protection for battery temperature.The RT9524 is available in a WDFN-10L 3x2 package to achieve optimized solution for PCB space and thermal considerations.Featuresz 28V Maximum Rating for DC Adapter z Internal Integrated Power MOSFETs z Support 4.2V/2.3A Factory Modez 50mA Low Dropout Voltage Regulator z Status Pin Indicatorz Programmed Charging Current z Under Voltage Lockout z Over Voltage Protectionz Thermal Feedback Optimized Charge Rate zRoHS Compliant and Halogen FreeApplicationsz Cellular Phones z Digital Camerasz PDAs and Smart Phones zProtable InstrumentsMarking InformationA0 : Product CodeW : Date CodeISET IEOCGND PGB CHGSB GND EN/SETLDOVIN BATT G : Green (Halogen Free and Pb Free)Typical Application CircuitFunction Block DiagramDS9524-01 April 2011Electrical CharacteristicsTo be continuedRecommended Operating Conditions (Note 3)z Supply Input Voltage, V IN ----------------------------------------------------------------------------------------------4.3V to 5.5V z Junction T emperature Range ------------------------------------------------------------------------------------------−40°C to 125°C zAmbient T emperature Range ------------------------------------------------------------------------------------------ −20°C to 85°CAbsolute Maximum Ratings (Note 1)z Supply Input Voltage, V IN ----------------------------------------------------------------------------------------------−0.3V to 28V z Other Pins -----------------------------------------------------------------------------------------------------------------−0.3V to 6V zPower Dissipation, P D @ T A = 25°CWDFN-10L 3x2----------------------------------------------------------------------------------------------------------- 1.111W zPackage Thermal Resistance (Note 2)WDFN-10L 3x2, θJA ------------------------------------------------------------------------------------------------------90°C/W WDFN-10L 3x2, θJC -----------------------------------------------------------------------------------------------------15°C/W z Lead Temperature (Soldering, 10 sec.)-----------------------------------------------------------------------------260°C z Junction T emperature ---------------------------------------------------------------------------------------------------150°CzStorage Temperature Range -------------------------------------------------------------------------------------------−65°C to 150°C(V IN= 5V, V BATT = 4V, T A = 25°C, unless otherwise specified)Note 1. Stresses listed as the above“Absolute Maximum Ratings”may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability.Note 2. θJA is measured in the natural convection at T A = 25°C on a high effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the package.Note 3. The device is not guaranteed to function outside its operating conditions.DS9524-01 April 2011VOUT Regulation Voltage vs. Input Voltage4.1954.2004.2054.2104.2154.2204.2254.54.945.385.826.266.7Input Voltage (V)V O U T R e g u l a t i o n V o l t a g e (V)VOUT Sleep Leakage Current vs. Battery Voltage0481216201.31.72.12.52.93.33.74.14.5Battery Voltage (V)V O U T S l e e p L e a k a g e C u r r e n t (µA )Input OVP Threshold vs. Temperature6.706.726.746.766.786.806.826.84-50-25255075100125Temperature (°C)I n p u t O V P T h r e s h o l d (V )Typical Operating CharacteristicsLDO Voltage vs. Temperature4.854.874.894.914.934.95-50-25255075100125Temperature (°C)L D O V o l t a g e (V)LDO Output Voltage vs. Output Current4.854.874.894.914.934.9520406080100Output Current (mA)L D O O u t p u t V o l t a g e (V)VOUT Regulation Voltage vs. Temperature4.1854.1904.1954.2004.2054.2104.215-50-25255075100125Temperature (°C)V O U T R e g u l a t i o n V o l t a g e (V )EN/SET Shut-DownTime (1ms/Div)V IN = 5VEN/SEB (1V/Div)VLDO (2V/Div)I CHARGER (500mA/Div)CHGS (2V/Div)Power On Time (10ms/Div)PGB (2V/Div)V IN (5V/Div)V BATT = 3.8V, R ISET = 680Ω, EN/SEB = LowCHGSB (2V/Div)I CHARGER (500mA/Div)USB 100 Mode Charge Current vs. Input Voltage8590951004.54.95.35.76.16.5Input Voltage (V)Ch a r g e C u r r e n t (m A )ISET Voltage vs. Input Voltage1.471.481.491.501.511.521.534.24.725.245.766.286.8Input Voltage (V)I S E T V o l t a g e (V )USB 500 Mode Charge Current vs. Input Voltage3653753853954054154.54.95.35.76.16.5Input Voltage (V)Ch a r g e C u r r e n t (m A )ISET Mode Charge Current vs. Input Voltage3003754505256006757508259004.54.95.35.76.16.5Input Voltage(V)C h a r ge C u r r e n t (m A )DS9524-01 April 2011Factory ModeTime (50μs/Div)V IN = 5V , C OUT = 44μF, I OUT = 10Ω to 2.3ΩVIN (5V/Div)VBA TT (200mV/Div)EN/SET (1V/Div)I OUT (1A/Div)LDO Load Transient ResponseTime (250μs/Div)V IN = 5V, V BATT = 3.8V, I LDO = 5mA to 50mAVLDO _ac(100mV/Div)I LDO(500mA/Div)Time (1ms/Div)V IN = 5V, V BATT = 3.8V, R ISET = 680ΩVIN (5V/Div)VBA TT (5V/Div)EN/SET (2V/Div)I CHARGER (500mA/Div)VIN (5V/Div)VBA TT(5V/Div)EN/SET (2V/Div)I CHARGER (500mA/Div)V IN = 5V, V BATT = 3.8V, R ISET = 80ΩTime (1ms/Div)Application InformationDescriptionThe RT9524 is a fully integrated low cost single-cell Li-Ion battery charger IC with a constant current mode (CC mode) or a constant voltage mode (CV mode). The charge current is programmable to USB100, USB500 or ISET mode and the CV mode voltage is fixed at 4.2V. The pre-charge threshold is fixed at 2.5V. If the battery voltage is below the pre-charge threshold, the RT9524 charges the battery with a trickle current until the battery voltage rises above the pre-charge threshold. The RT9524 is capable of being powered up from AC adapter and USB (Universal Serial Bus) port inputs. Moreover, the RT9524 include a linear regulator (LDO 4.9V, 50mA) for supplying low power external circuitry.ACIN Over Voltage ProtectionThe input voltage is monitored by the internal comparator and the input over voltage protection threshold is set to 6.9V. However, input voltage over 28V will still cause damage to the RT9524. When the input voltage exceeds the threshold, the comparator outputs a logic signal to turn off the power P-MOSFET to prevent the high input voltage from damaging the electronics in the handheld system. When the input over voltage condition is removed, the comparator re-enables the output by running through the soft-start.Charger Enable and mode SettingEN/SET is used to enable or disable the charger as well as to select the charge current limit. Drive the EN pin to low or leave it floating to enable the charger. The EN/SET pin has a 200kΩ internal pull down resistor. So, when left floating, the input is equivalent to logic low. Drive this pin to high to disable the charger. After the EN/SET pin pulls low for 50μs, the RT9524 enters the USB500 mode and wait for the setting current signal. EN/SET can be used to program the charge current during this cycle. The RT9524 will change its charge current by sending different pulse to EN/SET pin. If no signal is sent to EN/SET, the RT9524 will remain in USB500 mode. A correct period of time for high pulse is between 100μs and 700μs and the period of pulse to pulse must be between 100μs and 700μs to be properly read. Once EN/SET is held low for 1.5ms,the number of pulses is locked and sent to the control logic and then the mode changes. The RT9524 needs to be restarted to reset the charge current. Once the EN/ SET input is held high for more than 1.5ms, the RT9524 is disabled.Table 1. Pulse Counting Map for EN/SET InterfaceFigure .1 (b)Battery Charge ProfileThe RT9524 charges a Li-Ion battery with a constant current (CC) or a constant voltage (CV).The constant current is decided by the operation mode of USB100, USB500 or ISET mode. The constant current is set with the external resistor R ISET and the constant voltage is fixed at 4.2V. If the battery voltage is below the Pre-Charge Threshold, the RT9524 charges the battery with a trickle current until the battery voltage rises above the trickle charge threshold. When the battery voltage reaches 4.2V, the charger enters CV mode and regulates the battery voltage at 4.2V to fully charge the battery without the risk of over chargingFigure .1 (a)IIDS9524-01 April 2011Battery Pre-Charge CurrentDuring a charge cycle, if the battery voltage is below the pre-charge threshold, the RT9524 enters the pre-charge mode. This feature revives deeply discharged cells and protects battery. Under USB100 Mode, the pre-charge current is internally set to 95mA. When the RT9524 is under USB500 and ISET Mode, the pre-charge current is 20% of fast-charge current set by external resistor R ISET .Battery Fast-Charge Current ISET ModeThe RT9524 offers ISET pin to program the charge current.The resistor R ISET is connected to ISET and GND. The parameter K ISET is specified in the specification table.ISEF Charge ISEF ISETKI = ; K = 530R USB500 and USB100 ModeThe fast-charge current is 95mA in USB100 mode and 395mA in USB500 mode. Note that if the fast-charge current set by external resistor is smaller than that in USB500 mode (395mA), the RT9524 charges the battery in ISET mode.Battery Voltage Regulation (CV Mode)The battery voltage regulation feedback is through the BATT pin. The RT9524 monitors the battery voltage between BATT and GND pins. When the battery voltage closes in on the battery regulation voltage threshold, the voltage regulation phase begins and the charging current begins to taper down. When the charging current falls below the programmed end-of-charge current threshold,the CHGSB pin goes high to indicate the termination of charge cycle.The end-of-charge current threshold is set by the IEOC pin. The resistor R EOC is connected to IEOC and GND.The parameters K EOC and IEOC are specified in the specification table.EOC EOC EOC EOC RI (%) = ; K = 200K The current threshold of IEOC (%) is defined as the percentage of fast-charge current set by R ISET . After the CHGSB pin is pulled high, the RT9524 still monitors the battery voltage. Charge current is resumed when the battery voltage goes to lower than the battery regulation voltage threshold.Factory ModeThe RT9524 provides factory mode for supplies up to 2.3A for powering external loads with no battery installed and BATT is regulated to 4.2V. The factory mode allows the user to supply system power with no battery connected.In factory mode, thermal regulation is disabled but thermal protection (155°C) is still active. When using currents greater than 1.5A in factory mode, the user must limit the duty cycle at the maximum current to 20% with a maximum period of 10ms.LDOThe RT9524 integrates one low dropout linear regulator(LDO) that supplies up to 50mA. The LDO is active whenever the input voltage is between POR threshold andFigure 2Figure 32004006008001000120014000.40.60.81 1.2 1.4 1.61.82 2.22.4 2.62.83R SET ∠)B a t t e r yC h a r g e C u r r e n t (m A )(k ΩOVP threshold. It is not affected by the EN/SET input.Note that the LDO current is independence and not monitored by the charge current limit.Charge Status Outputs (CHGSB and PGB)The open-drain CHGSB and PGB outputs indicate various charger operations as shown in the following table. These status pins can be used to drive LEDs or communicate to the host processor. Note that ON indicates the open-drain transistor is turned on and LED is bright.Table 2Sleep ModeThe RT9524 enters sleep mode if the power is removed from the input. This feature prevents draining the battery during the absence of input supply.Temperature Regulation and Thermal Protection In order to maximize charge rate, the RT9524 features a junction temperature regulation loop. If the power dissipation of the IC results in a junction temperature greater than the thermal regulation threshold (125°C), the RT9524 limits the charge current in order to maintain a junction temperature around the thermal regulation threshold (125°C). The RT9524 monitors the junctiontemperature, T J , of the die and disconnects the battery from the input if T J exceeds 125°C. This operation continues until junction temperature falls below thermal regulation threshold (125°C) by the hysteresis level. This feature prevents maximum power dissipation from exceeding typical design conditions.Selecting the Input and Output CapacitorsIn most applications, all that is needed is a high-frequency decoupling capacitor on the input. A 1μF ceramic capacitor,placed in close proximity to input to GND, works well. Insome applications depending on the power supplycharacteristics and cable length, it may be necessary toadd an additional 10μF ceramic capacitor to the input.The RT9524 requires a small output capacitor for loop stability. A typical 1μF ceramic capacitor placed between the BATT pin and GND is sufficient.Thermal ConsiderationsFor continuous operation, do not exceed absolutemaximum operation junction temperature. The maximum power dissipation depends on thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. Themaximum power dissipation can be calculated by thefollowing formula :P D(MAX) = (T J(MAX) − T A ) / θJAwhere T J(MAX) is the maximum operation junctiontemperature, T A is the ambient temperature, and θJA is thejunction to ambient thermal resistance.For recommended operating conditions specification of RT9524, the maximum junction temperature is 125°C and T A is the maximum ambient temperature. The junction to ambient thermal resistance, θJA , is layout dependent. For WDFN-10L 3x2 packages, the thermal resistance, θJA , is 90°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at T A = 25°C can be calculated by the following formula :P D(MAX) = (125°C − 25°C) / (90°C/W) = 1.111W for WDFN-10L 3x2 packageThe maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA . For RT9524 package, the derating curveRT952411DS9524-01 April 2011in Figure 4 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.Figure 4. Derating Curve for RT9524 Package Layout ConsiderationThe RT9524 is a fully integrated low cost single-cell Li-Ion battery charger IC ideal for portable applications. Careful PCB layout is necessary. For best performance, place all peripheral components as close to the IC as possible. A short connection is highly recommended. The following guidelines should be strictly followed when designing a PCB layout for the RT9524.`Input capacitor should be placed close to the IC and connected to ground plane. The trace of input in the PCB should be placed far away from the sensitive devices or shielded by the ground.`The GND should be connected to a strong ground plane for heat sinking and noise protection.`The connection of R ISET and R IEOC should be isolated from other noisy traces. The short wire is recommended to prevent EMI and noise coupling.`Output capacitor should be placed close to the IC and connected to ground plane to reduce noise coupling.Figure 5. PCB Layout GuideThe capacitor should be placed close to IC pin and The connection of resistor should be isolated from other noisy traces. Short to prevent EMI and noise coupling.ground plane for heat sinking and noise protection.0.00.20.40.60.81.01.2255075100125Ambient Temperature (°C)M a x i m u m P o w e r D i s s i p a t i o n (W )12DS9524-01 April 2011Richtek Technology CorporationHeadquarter5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C.Tel: (8863)5526789 Fax: (8863)5526611Richtek Technology CorporationTaipei Office (Marketing)5F, No. 95, Minchiuan Road, Hsintien City Taipei County, Taiwan, R.O.C.Tel: (8862)86672399 Fax: (8862)86672377Email:*********************Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.W-Type 10L DFN 3x2 Package。

微芯片Adaptec产品指南：信任存储解决方案说明书

Adaptec ® Product GuideTrusted Storage SolutionsData Center SolutionsThe Microchip name and logo, the Microchip logo, Adaptec and maxCrypto is a trademark are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks mentioned herein are property of their respective companies.© 2020, Microchip Technology Incorporated. All Rights Reserved. 1/20 DS00003375ASupportMicrochip is committed to supporting its customers in developing products faster and more efficiently. We maintain a worldwide network of field applica -tions engineers and technical support ready to provide product and system assistance. For more information, please visit :• Technical Support: /support • Evaluation samples of any Microchip device:/sample • Knowledge base and peer help:/forums• Sales and Global Distribution: /salesTrainingIf additional training interests you, Microchip offers several resources including in-depth technical training and reference material, self-paced tutorials and significant online resources.• Overview of Technical Training Resources: /training • MASTERs Conferences:/masters • Developer Help Website:/developerhelp • Technical Training Centers:/seminarsMicrochip Technology Inc. | 2355 W. Chandler Blvd. | Chandler AZ, 85224-6199Adaptec ® Product GuideEach New Product Family Has Unique, Differentiating FeaturesSmartRAID 3100The SmartRAID 3100 is optimized for Enterprise storage applications that require the highest level of data availability and data center applications that benefit from caching.• Adapters with up to 24 ports using 28 nm SAS/SATA-optimized silicon, offering the industry’s lowest power • Z ero Maintenance Cache Protection (ZMCP) with a cache size up to 4 GB with integrated cache backupcircuitry for optimal cost, thermal performance and operating efficiency • Board options without cache backup• Mixed mode enables drives to be independently configured as raw drives or as part of a logical volume • maxCache 4.0 included on 315x and 316x adapters• maxCrypto controller-based encryption on the 3162-8i/e adapterSmartHBA 2100The SmartHBA 2100 is optimized for Software-Defined Storage (SDS) applications that require hardware RAID for OS boot drives as well as entry-level RAID for SMBs.• The only basic hardware RAID solution offering a fully featured, high-performance Host Bus Adapter(HBA) for drives configured as raw drives, required for multi-path IO and SDS applications • RAID levels 0, 1, 10, 5• Industry’s only basic hardware RAID solution with more than 8 ports• Mixed mode enables drives to be independently configured as raw drives or as part of a logical volumeHBA 1100The HBA 1100 is optimized for SDS, cold storage, and raw high-performance connectivity.• Adapters with up to 24 ports using 28 nm SAS/SATA-optimized silicon, offering the industry’s lowestpower• Support for host-managed and host-aware Shingled Magnetic Recording (SMR) drives • Broad OS driver support, including inbox driver support • Performance of up to 1.7M IOPS Smart Storage Solutions OverviewCablesSmartRAIDSmartRAIDSmartHBASmartRAID 3100 RAID AdaptersAdaptec 12 Gbps SmartRAID 3100 adapters have an 8-lane PCIe ®Gen 3 host bus interface, a SmartROC 3100 processor, an MD2 low-profile form factor, and can be scaled to a maximum of 256 SAS/SATA devices*. The newest addition, the SmartRAID 3162-8i/e, provides the industry’s only data-at-rest controller-based encryption solution, maxCrypto. Supporting operating systems include include Microsoft Windows ®, Red Hat, SUSE, Fedora, Debian, Ubuntu, Sun Solaris, FreeBSD, VMware ESXi, open-source Linux ®drivers and inbox drivers.Series 8 RAID AdaptersAdaptec 12 Gbps RAID Adapters have an 8-lane PCIe Gen3 host bus interface,a 12 Gbps RoC processor, a MD2 low-profile form factor, and can be scaled to a maximum of 256 SAS/SATA devices*. Supporting operating systems include Microsoft Windows, Red Hat Linux, SUSE Linux, Fedora, Debian Linux, Ubuntu Linux,Sun Solaris, FreeBSD and VMware ESXi.SmartHBA and Host Bus Adapters (HBA)Adaptec 12 Gbps HBAs have an 8-lane PCIe Gen 3 host bus interface, a SmartIOC 2100 processor, an MD2 low-profile form factor, and can be scaled to a max -imum of 256 SAS/SATA devices*. In addition, the SmartHBA 2100 series uniquely combines the capabilities of a full-featured HBA, with those of a basic hardware RAID adapter. Supporting operating systems include Microsoft Windows, Red Hat, SuSE, CentOS, Ubuntu, VMware ESXi, FreeBSD, Solaris and Citrix Xen Server.SmartHBA 2100 Host Bus Adaptor Specifications4SAS-SBExternal CablesACK-E-HDmSAS-HDmSASACK-E-HDmSAS-mSASMake the Right Connection With Adaptec 12 Gbps and 6 Gbps SAS HD CablesAdaptec SmartRAID 3100, SmartHBA 2100, HBA 1100 and Series 8/8Q/8E RAID adapters are configured with mini-SAS HD connectors to allow for maximum performance and connectivity in a MD2 low-profile form factor. Pick the right cable for your internal or external storage solution.。

FPGA可编程逻辑器件芯片EP4CE55F23C7N中文规格书

Chapter 3:Memory Blocks in Arria II DevicesMemory Modes Figure3–18 shows the memory block in shift-register mode.Figure3–18.Shift-Register Memory ConfigurationROM ModeAll Arria II memory blocks support ROM mode. A .mif initializes the ROM contentsof these blocks. The address lines of the ROM are registered on M9K and M144Kblocks; however, they can be unregistered on MLABs. The outputs can be registeredor unregistered. Output registers can be asynchronously cleared. The ROM readoperation is identical to the read operation in the single-port RAM configuration.FIFO ModeAll memory blocks support FIFO mode. MLABs are ideal for designs with manysmall, shallow FIFO buffers. To implement FIFO buffers in your design, you can usethe FIFO MegaWizard Plug-In Manager in the Quartus II software. Both single- anddual-clock (asynchronous) FIFOs are supported.f For more information about implementing FIFO buffers, refer to the SCFIFO andDCFIFO Megafunctions User Guide.1MLABs do not support mixed-width FIFO mode.Arria II Device Handbook Volume 1: Device Interfaces and IntegrationChapter 9:Configuration, Design Security, and Remote System Upgrades in Arria II DevicesJTAG ConfigurationYou must connect the nCE pin to GND or drive it low during JTAG configuration. Inmulti-device FPP, AS, and PS configuration chains, the nCE pin of the first device isconnected to GND, while its nCEO pin is connected to nCE of the next device in thechain. The nCE input of the last device comes from the previous device, while its nCEOpin is left floating. In addition, the CONF_DONE and nSTATUS signals are all shared inmulti-device FPP, AS, or PS configuration chains so the devices can enter user mode atthe same time after configuration is complete. When the CONF_DONE and nSTATUSsignals are shared among all the devices, you must configure every device when JTAGconfiguration is performed.1If you only use JTAG configuration, Altera recommends connecting the circuitry as shown in Figure9–17, where each of the CONF_DONE and nSTATUS signals are isolated toenable each device to enter user mode individually.After the first device completes configuration in a multi-device configuration chain,its nCEO pin drives low to activate the nCE pin of the second device, which prompts thesecond device to begin configuration. Therefore, if these devices are also in a JTAGchain, ensure the nCE pins are connected to GND during JTAG configuration or thatthe devices are JTAG configured in the same order as the configuration chain. As longas the devices are JTAG configured in the same order as the multi-deviceconfiguration chain, the nCEO of the previous device drives the nCE of the next devicelow when it has successfully been JTAG configured.You can place other Altera devices that have JTAG support in the same JTAG chain fordevice programming and configuration.1JTAG configuration support is enhanced and allows more than 17 Arria II devices to be cascaded in a JTAG chain.f For more information about configuring multiple Altera devices in the sameconfiguration chain, refer to the Configuring Mixed Altera Device Chains chapter involume2 of the Configuration Handbook.You can configure Arria II devices using multiple configuration schemes on the sameboard. Combining JTAG configuration with a PS or AS configuration on your board isuseful in the prototyping environment because it allows multiple methods toconfigure your FPGA.f For more information about combining JTAG configuration with other configurationschemes, refer to the Combining Different Configuration Schemes chapter in volume2 ofthe Configuration Handbook.Arria II Device Handbook Volume 1: Device Interfaces and IntegrationChapter 3:Memory Blocks in Arria II DevicesDesign ConsiderationsPower-Up Conditions and Memory InitializationM9K and M144K block outputs power up to zero (cleared), regardless of whether theoutput registers are used or bypassed. MLABs power up to zero if the output registersare used and power up reading the memory contents if the output registers are notused. You must take this into consideration when designing logic that might evaluatethe initial power-up values of the MLAB memory block. For Arria II devices, theQuartus II software initializes the RAM cells to zero unless there is a .mif filespecified.All memory blocks support initialization using a .mif. You can create .mif files in theQuartus II software and specify their use with the RAM MegaWizard Plug-InManager when instantiating a memory in your design. Even if a memory ispre-initialized (for example, using a .mif), it still powers up with its outputs cleared.f For more information about .mif files, refer to the Internal Memory (RAM and ROM)Megafunction User Guide and the Quartus II Handbook.Power ManagementArria II memory block clock enables allow you to control clocking of each memoryblock to reduce AC-power consumption. Use the read-enable signal to ensure thatread operations only occur when you need them to. If your design does not requireread-during-write, you can reduce your power consumption by deasserting theread-enable signal during write operations or any period when no memoryoperations occur.The Quartus II software automatically places any unused memory block in low powermode to reduce static power.Arria II Device Handbook Volume 1: Device Interfaces and Integration。

启英泰伦 CI1312 数据手册说明书

CI1312数据手册高性能神经网络智能语音芯片SOP16长9.9mm宽6.0mm高1.7mm•脑神经网络处理器（BNPU）–BNPU V3，支持DNN\TDNN\RNN\CNN等神经网络及并行矢量运算，可实现语音识别、声纹识别、命令词自学习、语音检测及深度学习降噪等功能•CPU和存储器–CPU主频可达220MHz–内置2MBytes Flash存储器–内置640KBytes SRAM–内置512bit eFuse，可用于应用加密•Audio Codec–高性能低功耗audio ADC，SNR≥95dB–低功耗audio DAC，SNR≥95dB •PWM–支持3路PWM接口•GPIO–5个高速GPIO，响应速率可达20MHz–全部GPIO支持5V输入•复位和电源管理–内置电源管理单元PMU–PMU输入电压范围: 3.6V到5.5V–内置上电复位（POR）–内置电压检测(PVD)•时钟–内置RC振荡器•通讯接口–1路IIC接口–2路UART接口，支持5V通讯，支持最高3Mbps速率•定时器和看门狗–内置4组32位定时器和2组看门狗目录1概述 (3)1.1功能描述 (3)1.2芯片规格 (4)2引脚图和功能描述 (6)2.1引脚图 (6)2.2管脚描述 (7)2.3复用功能 (9)3电气特性 (10)4封装信息 (12)5订购信息 (13)6应用方案 (14)6.1应用参考电路图 (14)6.2应用其它注意事项 (15)1概述1.1功能描述CI1312是启英泰伦研发的新一代高性能神经网络智能语音芯片，集成了启英泰伦自研的脑神经网络处理器BNPU V3和CPU内核，系统主频可达220MHz，内置高达640KByte的SRAM，集成PMU电源管理单元和RC振荡器，集成单通道高性能低功耗Audio Codec和多路UART、IIC、PWM、GPIO等外围控制接口。

芯片仅需少量电阻电容等外围器件就可以实现各类智能语音产品硬件方案，性价比极高。

启珑微电子产品手册说明书

产品手册PRODUCT MANUAL(北京︶有限公司并一直致力于为工业智能控制、医疗设备、轨道交通、智能交通以及智能家居等领域提供更优质的产品与服务。

公司具有深厚的文化底蕴，由多位有欧美留学、工作经历的归国人员创办，坚实的理论功底和丰富的芯片设计经验奠定了启珑微电子的高起点和高水准，并迅速成长为业内具有自主知识产权的中国IC设计品牌之一。

产品手册01序号产品型号封装形式产品概述兼容型号1CLM811HST-AXC TQFP-48SL811HST-AXC 2CLCP82C55AZ DIP-40CP82C55AZ 3CLIP82C55AZ DIP-40IP82C55AZ 4CLCS82C55AZ PLCC-44CS82C55AZ 5CLIS82C55AZ PLCC-44IS82C55AZ 6CLCQ82C55AZ MQFP-44CQ82C55AZ 7CLIQ82C55AZ MQFP-44IQ82C55AZ 8CLID82C55AZ DIP-40ID82C55A 9CLMD82C55A/B DIP-40MD82C55A/B 10CLMD82C55QA DIP-40MD82C55QA 11CLM65HVD230D SOIC-8SN65HVD230D 12CLM65HVD230QD SOIC-8SN65HVD230QD 13CLM65HVD231D SOIC-8SN65HVD231D 14CLM65HVD231QD SOIC-8SN65HVD231QD 15CLM65HVD232D SOIC-8SN65HVD232D 16CLM65HVD232QD SOIC-8SN65HVD232QD 17CLM65HVD233D SOIC-8具有待机模式和环回功能的 3.3V SN65HVD233D 18CLM65HVD233HD SOIC-8具有待机模式和环回功能的 3.3V SN65HVD233HD 19CLM65HVD233QDRQ1SOIC-8具有待机模式和环回功能的 3.3V SN65HVD233QDRQ120CLM65HVD233MDREP SOIC-8具有待机模式和环回功能的 3.3V SN65HVD233MDREP产品手册02序号产品型号封装形式产品概述兼容型号21CLM65HVD234D SOIC-8SN65HVD234D 22CLM65HVD234QDRQ1SOIC-8SN65HVD234QDRQ123CLM65HVD235D SOIC-8SN65HVD235D 24CLM65HVD235QDRQ1SOIC-8SN65HVD235QDRQ125CLM75176BPS SOIC-8SN75176BPSR 26CLM75176BDR SOIC-8SN75176BDR 27CLM75176ADR SOIC-8SN75176ADR 28CLM75176AP DIP-8SN75176AP 29CLM76176BP DIP-8SN75176BP 30CLM75179BPS SOIC-8SN75179BPS 31CLM75179BDR SOIC-8SN75179BDR 32CLM75179AP DIP-8SN75179AP 33CLM75179BP DIP-8SN75179BP 34CLM65HVD08D SOIC-8SN65HVD08D 35CLM65HVD08P DIP-8SN65HVD08P 36CLM65HVD75D SOIC-8具有IEC ESD保护功能和20Mbps的SN65HVD75D 37CLM65HVD75DGK VSSOIC-8具有IEC ESD保护功能和20Mbps的SN65HVD75DGK 38CLM65HVD75DRBT VDFN-8具有IEC ESD保护功能和20Mbps的SN65HVD75DRBT 39CLM3085CPA+DIP-8(10Mbps)、限摆率RS-485/MAX3085CPA+40CLM3085EPA+DIP-8(10Mbps)、限摆率RS-485/MAX3085EPA+产品手册03序号产品型号封装形式产品概述兼容型号41CLM3085EEPA DIP-8(10Mbps)、限摆率RS-485/MAX3085EEPA 42CLM3085CSA+T SOIC-8(10Mbps)、限摆率RS-485/MAX3085CSA+43CLM3085ECSA+T MSOIC-8(10Mbps)、限摆率RS-485/MAX3085ECSA+T 44CLM3085ESA+T SOIC-8(10Mbps)、限摆率RS-485/MAX3085ESA+45CLM3085EESA+T SOIC-8(10Mbps)、限摆率RS-485/MAX3085EESA+46CLM3088CSA+T SOIC-8MAX3088CSA+T 47CLM3088ECSA+T SOIC-8MAX3088ECSA+T 48CLM3088ESA+T SOIC-8MAX3088ESA+T 49CLM3088EESA+T SOIC-8MAX3088EESA+T 50CLM3088CPA+DIP-8MAX3088CPA+51CLM3088ECPA+DIP-8MAX3088ECPA+52CLM3088EPA+DIP-8MAX3088EPA+53CLM3088EEPA+DIP-8MAX3088EEPA+54CLM485CPA+DIP-8低功耗、限摆率、RS-485/RS-422MAX485CPA+55CLM485ECPA+DIP-8低功耗、限摆率、RS-485/RS-422MAX485ECPA+56CLM485EPA+DIP-8低功耗、限摆率、RS-485/RS-422MAX485EPA+57CLM485EEPA+DIP-8低功耗、限摆率、RS-485/RS-422MAX485EEPA+58CLM485CSA+SOIC-8低功耗、限摆率、RS-485/RS-422MAX485CSA+59CLM485ESA+SOIC-8低功耗、限摆率、RS-485/RS-422MAX485ESA+60CLM485EESA+SOIC-8低功耗、限摆率、RS-485/RS-422MAX485EESA+产品手册04序号产品型号封装形式产品概述兼容型号61CLM3490CSA+SOIC-8 3.3V供电、10Mbps、限摆率、真MAX3490CSA+62CLM3490ECSA+SOIC-8 3.3V供电、10Mbps、限摆率、真MAX3490ESA+63CLM3490ESA+SOIC-8 3.3V供电、10Mbps、限摆率、真MAX3490ESA+64CLM3490EESA+SOIC-8 3.3V供电、10Mbps、限摆率、真MAX3490EESA+65CLM3491CSD SOP-14 3.3V供电、10Mbps、限摆率、真MAX3491CSD+66CLM3491ECSD+SOP-14 3.3V供电、10Mbps、限摆率、真MAX3491ECSD+67CLM3491ESD+SOP-14 3.3V供电、10Mbps、限摆率、真MAX3491ESD+68CLM3491EESD+SOP-14 3.3V供电、10Mbps、限摆率、真MAX3491EESD+69CLM490CSA+SOIC-8低功耗、限摆率、RS-485/RS-422MAX490CSA+70CLM490ECSA+SOIC-8低功耗、限摆率、RS-485/RS-422MAX490ECSA+71CLM490ESA+SOIC-8低功耗、限摆率、RS-485/RS-422MAX490ESA+72CLM490EESA+SOIC-8低功耗、限摆率、RS-485/RS-422MAX490EESA+73CLM490CPA+DIP-8低功耗、限摆率、RS-485/RS-422MAX490CPA+74CLM490ECPA+DIP-8低功耗、限摆率、RS-485/RS-422MAX490ECPA+75CLM490EPA+DIP-8低功耗、限摆率、RS-485/RS-422MAX490EPA+76CLM490EEPA+DIP-8低功耗、限摆率、RS-485/RS-422MAX490EEPA+77CLM488CSA+SOIC-8低功耗、限摆率、RS-485/RS-422MAX488CSA+78CLM488ECSA+SOIC-8低功耗、限摆率、RS-485/RS-422MAX488ECSA+79CLM488ESA+SOIC-8低功耗、限摆率、RS-485/RS-422MAX488ESA+80CLM488EESA+SOIC-8低功耗、限摆率、RS-485/RS-422MAX488EESA+产品手册序号产品型号封装形式产品概述兼容型号81CLM488CPA+DIP-8MAX488CPA+82CLM488ECPA+DIP-8MAX488ECPA+83CLM488EPA+DIP-8MAX488EPA+84CLM488EEPA+DIP-8MAX488EEPA+85CLM232CSE SOIC-16MAX232CSE+T86CLM232ECSE SOIC-16MAX232ECSE+87CLM232ESE SOIC-16MAX232ESE+T88CLM232EESE SOIC-16MAX232EESE+T89CLM232CPE DIP-16MAX232CPE+90CLM232ECPE DIP-16MAX232ECPE+91CLM232EPE DIP-16MAX232EPE+92CLM232EEPE DIP-16MAX232EEPE+93CLM232CWE SOIC-16MAX232CWE+T94CLM232ECWE SOIC-16MAX232ECWE+T95CLM232EWE SOIC-16MAX232EWE+T96CLM232EEWE SOIC-16MAX232EEWE+T97CLM232ACWE SOIC-16MAX232ACWE+T98CLM232AEWE SOIC-16MAX232AEWE+99CLM3232CSE SOIC-16MAX3232CSE+T 100CLM3232ECSE SOIC-16MAX3232ECSE+T05产品手册06序号产品型号封装形式产品概述兼容型号101CLM3232ESE SOIC-16MAX3232ESE+T 102CLM3232EESE SOIC-16MAX3232EESE+T 103CLM1302S SOIC-8DS1302S+T&R 104CLM1302SN+SOIC-8DS1302SN+T&R 105CLM1302Z+T SOIC-8DS1302Z+T&R 106CLM1302ZN+SOIC-8DS1302ZN+T&R 107CLM1302+DIP-8DS1302+108CLM1302N+DIP-8DS1302N+109CLM307Z+SOIC-8DS1307Z+T&R 110CLM1307ZN+SOIC-8DS1307ZN+T&R 111CLM1307+DIP-8DS1307+112CLM1307N+DIP-8DS1307N+113CLM4717EUB+MSOP-10拟开关MAX4717EUB+114CLM231N/NOPB DIP-8LM231N/NOPB 115CLM231AN/NOPB DIP-8LM231AN/NOPB 116CLM331N/NOPB DIP-8LM331N/NOPB 117CLM331AN/NOPB DIP-8LM331AN/NOPB 118CLM298N Multiwatt-15L298N 119CLM298P POWERSO-20L298P 120CLM2543CDW SOIC-20TLC2543CDW产品手册07序号产品型号封装形式产品概述兼容型号121CLM2543IDW SOIC-20TLC2543IDW 122CLM2543CDB SSOP-20TLC2543CDB 123CLM2543IDB SSOP-20TLC2543IDB 124CLM2543CN DIP-20TLC2543CN 125CLM2543IN DIP-20TLC2543IN 126CLM1543CDW SOIC-20TLC1543CDW 127CLM1543IDW SOIC-20TLC1543IDW 128CLM1543CN DIP-20TLC1543CN 129CLM1543IN DIP-20TLC1543IN 130CLM5615CDGK VSSOIC-8趋稳时间为12.5us并具备上电复位功能的10位、单通道、低功耗DAC TLC5615CDGK 131CLM5615IDGK VSSOIC-8趋稳时间为12.5us并具备上电复位功能的10位、单通道、低功耗DAC TLC5615IGGK 132CLM5615CD SOIC-8趋稳时间为12.5us并具备上电复位功能的10位、单通道、低功耗DAC TLC5615CD 133CLM5615ID SOIC-8趋稳时间为12.5us并具备上电复位功能的10位、单通道、低功耗DAC TLC5615ID 134CLM5615CP DIP-8趋稳时间为12.5us并具备上电复位功能的10位、单通道、低功耗DAC TLC5615CP 135CLM5615IP DIP-8趋稳时间为12.5us并具备上电复位功能的10位、单通道、低功耗DAC TLC5615IP 136CLM3616-00SOP-14IW3616-00137CLM3616-01SOP-14IW3616-01138CLM3617-00SOP-14IW3617-00139CLM3617-01SOP-14IW3617-01140CLM3630-00SOP-14IW3630-00产品手册序号产品型号封装形式产品概述兼容型号141CLM1100-0001BGA-128ASIC从站控制ET1100-0001142CLM1100-0002BGA-128ASIC从站控制ET1100-0002143CLM1100-0003BGA-128ASIC从站控制ET1100-0003144CLM1200-0001QFN-48ASIC从站控制ET1200-0001145CLM1200-0002QFN-48ASIC从站控制ET1200-0002146CLM1200-0003QFN-48ASIC从站控制ET1200-0003147CLM8656ARZ SOIC-8AD8656ARZ148CLM8656ARMZ MSOIC-8AD8656ARMZ149CLM1040T/CM,118SOIC-8TJA1040T/CM,118 150CLM1042T/CM,118SOIC-8TJA1042T/CM,118 151CLM1050T/CM,118SOIC-8TJA1050T/CM,118 152CLM1051T/CM,118SOIC-8TJA1051T/CM,118 153CLM82C250T/YM SOIC-8PCA82C250T/YM 154CLM82C251T/YM SOIC-8PCA82C251T/YM 155CLMEE80C196KC20PLCC-68EE80C196KC20 156CLMEN80C196KC20PLCC-68EN80C196KC20 157CLMN80C196KC20PLCC-68N80C196KC20 158CLMTN80C196KC20PLCC-68TN80C196KC20 159CLMEE87C196KC20PLCC-68EE87C196KC20 160CLMEN87C196KC20PLCC-68EN87C196KC2008产品手册09序号产品型号封装形式产品概述兼容型号161CLMN87C196KC20PLCC-68N87C196KC20162CLMTN87C196KC20PLCC-68TN87C196KC20163CLM8051F020-GQ TQFP-100C8051F020-GQ 164CLM8051F021-GQ TQFP-64C8051F021-GQ 165CLM8051F330-GM VFQFN-20C8051F330-GM 166CLM8051F500-IQ TQFP-48C8051F500-IQ 167CLM8051F500-IM VFQFN-48C8051F500-IM 168CLM8051F502-IQ LQFP-32C8051F502-IQ 169CLM8051F502-IM QFN-32C8051F502-IM170CLM08D1500CIYB/NOPB HLQFP-128ADC08D1500CIYB/NOPB 171CLM083000CIYB/NOPB HLQFP-128ADCADC083000CIYB/NOPB 172CLM10AQ190AVTPY EBGA-38010位5GSPS ADC EV10AQ190AVTPY 173CLM9680BCPZ-1250LFCSP-64双通道14位1GSPS ADC AD9680BCPZ-1250174CLM9739BBCZ BGA-16014位、2.5 GSPS、RF数模AD9739BBCZ 175CLM9779ABSVZ TQFP-100双通道16位1GSPS DAC AD9779ABSVZ 176CLM12DS130AVZPY FPBGA-19612位3GSPS DAC EV12DS130AVZPY 177CLM12DS460AVZP FPBGA-19612位6.4GSPS DAC EV12DS460AVZP 178CLM9434BCPZ-370LFCSP-5612位370MSPS ADC AD9434BCPZ-370179CLM9434BCPZ-500LFCSP-5612位500MSPS ADC AD9434BCPZ-500180CLM4149IRGZTVQFN-4814位250MSPS ADCADS4149IRGZT产品手册10序号产品型号封装形式产品概述兼容型号181CLM9467BCPZ-200LFCSP-7216位200MSPS ADC AD9467BCPZ-200182CLM9467BCPZ-250LFCSP-7216位250MSPS ADC AD9467BCPZ-250183CLM9656BCPZ-125LFCSP-56四通道16位125MSPS ADC AD9656BCPZ-125184CLM9245BCPZ-40LFCSP-3214位40MSPS ADC AD9245BCPZ-40185CLM9245BCPZ-65LFCSP-3214位65MSPS ADC AD9245BCPZ-80186CLM9245BCPZ-80LFCSP-3214位80MSPS ADC AD9245BCPZ-80187CLM9783BCPZ LFCSP-72双通道16位500MSPS DAC AD9783BCPZ 188CLM7656BSTZ-REEL LQFP-64六通道16位250KSPS ADC AD7656BSTZ-REEL 189CLM7960BCPZLFCSP-3218位2MSPS ADC AD7960BCPZ190CLM128S102CIMTX/NOPB TSSOP-1612位1MSPS ADC ADC128S102CIMTX/NOPB 191CLM5638IDR SOIC-8DACTLV5638IDR 192CLM7606BSTZ LQFP-64AD7606BSTZ 193CLM9625BBPZ-2.5BGA-19612位2.6GSPS ADC AD9625BBPZ-2.5194CLM9164BBCZ BGA-16516位12GSPS DAC AD9164BBCZ 195CLM9154BCPZ LFCSP-88四通道16位2.4GSPS DAC AD9154BCPZ 196CLM2160IUK#PBF QFN-4816位25MSPS ADC LTC2160IUK#PBF 197CLM9652BBCZ-310BGA-144双通道16位310MSPS ADC AD9652BBCZ-310198CLM7779ACPZ-RL LFCSP-6424位16KSPS ADC AD7779ACPZ-RL 199CLM9208BBPZ-3000BGA-196双通道14位3GSPS ADCAD9208BBPZ-3000200CLM320VC33PGE120LQFP-144TMS320VC33PGE120产品手册序号产品型号封装形式产品概述兼容型号201CLM320VC33PGEA120LQFP-144TMS320VC33PGEA120 202CLM320VC33PGE150LQFP-144TMS320VC33PGE150203CLM320VC5402PGE100LQFP-144TMS320VC5402PGE100 204CLM320F28335PGFA LQFP-176TMS320F28335PGFA205CLM320LF2406APZA LQFP-100TMS320LF2406APZA206CLM320LF2406APZS LQFP-100TMS320LF2406APZS207CLM320LF2407APGES LQFP-144TMS320LF2407APGES208CLM320LF2407APGEA LQFP-144TMS320LF2407APGEA 209CLM320C6713BPYP200HLQFP-208TMS320C6713BPYP200 210CLM320C6713BZDP225BGA-272TMS320C6713BZDP225 211CLM320C6713BGDP225BGA-272TMS320C6713BGDP225 212CLM320C6713BZDP300BGA-272TMS320C6713BZDP300 213CLM320C6713BGDG300BGA-272TMS320C6713BGDP30011邮箱：*******************。

BL0972 交直流电能计量芯片数据手册 V1.0说明书

BL0972交/直流电能计量芯片数据手册V1.0目录1、产品简述 (5)2、基本特征 (6)2.1主要特点 (6)2.2系统框图 (7)2.3管脚排列（TSSOP20） (7)2.4性能指标 (8)2.4.1电参数性能指标 (8)2.4.2极限范围 (9)3、工作原理 (10)3.1电流电压波形产生原理 (10)3.1.1PGA增益调整 (10)3.1.2相位补偿 (11)3.1.3通道偏置校正 (11)3.1.4通道增益校正 (12)3.1.5电流电压波形输出 (12)3.2有功功率计算原理 (13)3.2.1有功波形的选择 (14)3.2.2有功功率输出 (14)3.2.3有功功率校准 (14)3.2.4有功功率的防潜动 (15)3.2.5有功功率小信号补偿 (15)3.3有功能量计量原理 (16)3.3.1有功能量输出 (16)3.3.2有功能量输出选择 (16)3.3.3有功能量输出比例 (17)3.4电流电压有效值计算原理 (17)3.4.1有效值输出 (18)3.4.2有效值输入信号的设置 (18)3.4.3有效值刷新率的设置 (18)3.4.4电流电压有效值校准 (19)3.4.5有效值的防潜动 (19)3.5快速有效值检测原理 (20)3.5.1快速有效值输出 (20)3.5.2快速有效值输入选择 (21)3.5.3快速有效值累计时间和阈值 (21)3.5.4电网频率选择 (21)3.5.5快速有效值超限数据保存 (22)3.5.6过流指示 (22)3.5.7继电器控制 (22)3.6温度计量 (23)3.7.1线周期计量 (23)3.7.2线频率计量 (23)3.7.3相角计算 (24)3.7.4功率符号位 (24)3.8故障检测 (25)3.8.1过零检测 (25)3.8.2峰值超限 (25)3.8.3线电压跌落 (26)3.8.4过零超时 (27)3.8.5电源供电指示 (28)4、内部寄存器 (30)4.1电参量寄存器（只读） (30)4.2校表寄存器（外部写） (30)4.3OTP寄存器 (32)4.4模式寄存器 (33)4.4.1 MODE1寄存器 (33)4.4.2 MODE2寄存器 (33)4.4.3 MODE3寄存器 (34)4.5中断状态寄存器 (34)4.5.1 STATUS1寄存器 (34)4.5.2 STATUS3寄存器 (34)4.6校表寄存器详细说明 (34)4.6.1 通道PGA增益调整寄存器 (34)4.6.2 相位校正寄存器 (35)4.6.3 有效值增益调整寄存器 (35)4.6.4 有效值偏置校正寄存器 (36)4.6.5 有功小信号补偿寄存器 (36)4.6.7 防潜动阈值寄存器 (36)4.6.8 快速有效值相关设置寄存器 (37)4.6.9 过流报警及控制 (38)4.6.11 能量读后清零设置寄存器 (39)4.6.12 用户写保护设置寄存器 (39)4.6.13 软复位寄存器 (39)4.6.14 通道增益调整寄存器 (40)4.6.15 通道偏置调整寄存器 (40)4.6.16 有功功率增益调整寄存器 (40)4.6.17 有功功率偏置调整寄存器 (41)4.6.20 CF缩放比例寄存器 (41)4.7电参数寄存器详细说明 (42)4.7.1 波形寄存器 (42)4.7.2 有效值寄存器 (42)4.7.3 快速有效值寄存器 (42)4.7.7 电能脉冲计数寄存器 (43)4.7.8 波形夹角寄存器 (44)4.7.9 快速有效值保持寄存器 (44)4.7.11 线电压频率寄存器 (44)5、SPI通讯接口 (45)5.1概述 (45)5.2工作模式 (45)5.3帧结构 (45)5.4读出操作时序 (46)5.5写入操作时序 (47)5.6SPI接口的容错机制 (48)6、典型应用图 (49)7、封装信息 (50)1、产品简述BL0972是一颗内置时钟的单相交/直流电能计量芯片。

NQC_datasheet_D3en

Rev D3,Page1/30Copyright©2009,2013iC-Haus Rev D3,Page2/30Rev D3,Page3/30PACKAGING INFORMATION4 PIN CONFIGURA TIONTSSOP204.4mm,lead pitch0.65mm.4ABSOLUTE MAXIMUM RATINGS5 THERMAL DATA5ELECTRICAL CHARACTERISTICS6 CHARACTERISTICS:Diagrams (8)OPERATING REQUIREMENTS:I/O Interface9 PARAMETER and REGISTER10 SIGNAL CONDITIONING11 CONVERTER FUNCTIONS12 MAXIMUM POSSIBLE CONVERTERFREQUENCY13 Serial Data Output (13)Incremental Output to A,B and Z (14)INCREMENTAL SIGNALS15 SIGNAL MONITORING and ERRORMESSAGES17TEST FUNCTIONS18I/O INTERFACE:BiSS C PROTOCOL19 Interface Parameters With BiSS C Protocol.19 Example of BiSS Data Output (20)Register Communication (20)Internal Reset Function (20)Short BiSS Timeout (20)I/O INTERFACE:SSI Protocol22 Examples of SSI Data Output (23)EEPROM INTERFACE24 Example of CRC Calculation Routine (24)STARTUP BEHAVIOR25 Startup With A Conﬁgured EEPROM (25)Startup Without An EEPROM (25)Initialization After Conﬁguration Failure (25)APPLICATION NOTES27 Principle Input Circuits (27)Input Circuit for Sine Encoders(1Vpp) (28)Basic Circuit for MR Sensors (28)EVALUATION BOARD29 DESIGN REVIEW:Function Notes29Rev D3,Page4/30PIN CONFIGURATIONTSSOP204.4mm,lead pitch0.65mm PIN FUNCTIONS Function1PCOS Input Cosine+ 2NCOS Input Cosine-3VDDA+5V Supply Voltage(analog)1)4GNDA Ground(analog)1)5VREF Reference Voltage Output6A Incremental Output AAnalog signal COS+(TMA mode)PWM signal for Offset Sine(calib.)7B Incremental Output BAnalog signal COS-(TMA mode)PWM signal for Offset Cosine(calib.)8Z Incremental Output ZPWM signal for Phase/Ratio(calib.)9GND Ground10VDD+5V Supply Voltage(digital)11SLI I/O Interface,data input2)12MA I/O Interface,clock line13SLO I/O Interface,data output14SDA EEPROM interface,data lineAnalog signal SIN+(TMA mode)15SCL EEPROM interface,clock line3)Analog signal SIN-(TMA mode)16NERR Error Input/Output,active low17PZERO Input Zero Signal+18NZERO Input Zero Signal-19PSIN Input Sine+20NSIN Input Sine-1)External connections linking VDDA to VDD and GND to GNDA are required.2)If only a single iC-NQC is used and no chain circuitry of multiple BiSS slaves,pin SLI can remain unwired or can be linked to ground(GND).3)It is not permissible to pull down pin SCL during power-up.Rev D3,Page 5/30These ratings do not imply permissible operating conditions;functional operation is not guaranteed.Exceeding these ratings may damage thedevice.Item SymbolParameter ConditionsUnitNo.Min.Max.G001VDDA Voltage at VDDA -0.36V G002VDD Voltage at VDD-0.36V G003Vpin()Voltage atPSIN,NSIN,PCOS,NCOS,PZERO,NZERO,VREF ,NERR,SCL,SDA,MA,SLI,SLO,A,B,ZV()<VDDA +0.3V -0.36V V()<VDD +0.3V G004Imx(VDDA)Current in VDDA -5050mA G005Imx(GNDA)Current in GNDA -5050mA G006Imx(VDD)Current in VDD-5050mA G007Imx(GND)Current in GND-5050mA G008Imx()Current inPSIN,NSIN,PCOS,NCOS,PZERO,NZERO,VREF ,NERR,SCL,SDA,MA,SLI,SLO,A,B,Z -1010mAG009Ilu()Pulse Current in all pins (Latch-up Strength)according to Jedec Standard No.78;-100100mAT a =25°C,pulse duration to 10ms,VDDA =VDDA max ,VDD =VDD max ,Vlu()=(-0.5...+1.5)x Vpin()maxG010Vd()ESD Susceptibility at all pins HBM 100pF discharged through 1.5k Ω2kV G011Tj Junction T emperature -40150°C G012TsStorage T emperature Range-40150°COperating Conditions:VDDA =VDD =5V ±10%Item Symbol ParameterConditionsUnitNo.Min.Typ.Max.T01T aOperating Ambient T emperature Range (extended temperature range of -40to 125°C available on request)-2585°C All voltages are referenced to ground unless otherwise stated.All currents ﬂowing into the device pins are positive;all currents ﬂowing out of the device pins are negative.Rev D3,Page6/30Operating Conditions:VDDA=VDD=5V±10%,Tj=-40...125°C,unless otherwise stated.Item Symbol Parameter Conditions Unit No.Min.Typ.Max.Total DeviceFunctionality and parameters beyond the operating conditions(with reference to independent voltage supplies,for instance)are to be veriﬁed within the individual application using FMEA methods.001VDDA,VDDPermissible Supply Voltage 4.5 5.5V 002I(VDDA)Supply Current in VDDAﬁn()=200kHz;A,B,Z open15mA 003I(VDD)Supply Current in VDDﬁn()=200kHz;A,B,Z open20mA 004Von T urn-on Threshold VDDA,VDD 3.2 4.4V 005Vhys T urn-on Threshold Hysteresis200mV006Vc()hi Clamp Voltage hi atPSIN,NSIN,PCOS,NCOS,PZERO,NZERO,VREF Vc()hi=V()-VDDA;0.3 1.6V I()=1mA,other pins open007Vc()lo Clamp Voltage lo atPSIN,NSIN,PCOS,NCOS,PZERO,NZERO,VREF,NERR,SCL,SDA,MA,SLI,SLO,A,B,ZI()=-1mA,other pins open-1.6-0.3V008Vc()hi Clamp Voltage hi atNERR,SCL,SDA,MA,SLI,SLO,A,B,Z Vc()hi=V()-VDD;0.3 1.6V I()=1mA,other pins openInput Ampliﬁers and Signal Inputs PSIN,NSIN,PCOS,NCOS101Vos()Input Offset Voltage Vin()and G()in accordance with table GAIN;G≥20-1010mVG<20-1515mV 102TCos Input Offset VoltageT emperature Driftsee101±10µV/K 103Iin()Input Current V()=0V...VDDA-5050nA 104GA Gain Accuracy G()in accordance with table GAIN95102% 105GArel Gain SIN/COS Ratio Accuracy G()in accordance with table GAIN97103% 106fhc Cut-off Frequency G=80150kHzG=2.667630kHz 107SR Slew Rate G=80 2.3V/µsG=2.6678.0V/µs Sine-To-Digital Conversion201AAabs Absolute Angle Accuracy withoutcalibration referred to360°input signal,G=2.667,Vin=1.5Vpp,HYS=0-1.0 1.0DEG202AAabs Absolute Angle Accuracy aftercalibration referred to360°input signal,HYS=0,internalsignal amplitude of2...4Vpp-0.5±0.35+0.5DEG203AArel Relative Angle Accuracy referred to signal periods at A,resp.B(see Fig.1);-1010%G=2.667,Vin=1.5Vpp,SELRES=1024,FCTR=0x0004...0x00FF,ﬁn<ﬁn max(see table15)Reference Voltage Output VREF801VREF Reference Voltage I(VREF)=-1mA...+1mA4852%VDDA OscillatorA02fosc()Oscillator Frequency presented at pin SCL with subdivisionof2048;VDDA=VDD=5V±10%5692MHzVDDA=VDD=5V607486MHz A03TCosc Oscillator Frequency T empera-ture DriftVDDA=VDD=5V-0.1%/KA04VCosc Oscillator Frequency Power Sup-ply Dependance+9%/VRev D3,Page7/30Operating Conditions:VDDA=VDD=5V±10%,Tj=-40...125°C,unless otherwise stated.Item Symbol Parameter Conditions Unit No.Min.Typ.Max.Zero Signal Enable Inputs PZERO,NZEROB01Vos()Input Offset Voltage V()=Vcm()-2020mVB02Iin()Input Current V()=0V...VDDA-5050nAB03Vcm()Common-Mode Input VoltageRange 1.4VDDA-1.5VB04Vdm()Differential Input Voltage Range0VDDA V Incremental Outputs A,B,Z and I/O Interface Output SLOD01Vs()hi Saturation Voltage hi Vs()hi=VDD-V();I()=-4mA0.4V D02Vs()lo Saturation Voltage lo I()=4mA0.4V D03tr()Rise Time CL()=50pF60ns D04tf()Fall Time CL()=50pF60ns D05RL()Permissible Load at A,B TMA=1(calibration mode)1MΩI/O Interface Inputs MA,SLIE01Vt()hi Threshold Voltage hi2V E02Vt()lo Threshold Voltage lo0.8V E03Vt()hys Hysteresis Vt()hys=Vt()hi-Vt()lo300mV E04Ipu(MA)Pull-up Current in MA V()=0...VDD-1V-240-120-25µA E05Ipd(SLI)Pull-down Current in SLI V()=1...VDD20120300µA E06fclk(MA)Permissible MA Clock Frequency SSI protocol4MHzBiSS protocol10MHzE07tp(MA-SLO)Propagation Delay:MA edge vs.SLO outputRL(SLO)≥1kΩ1050nsE08tbusy_s Processing Time Single-CycleData(delay of start bit)0µsE09tbusy_r Processing Time Register Ac-cess(delay of start bit)with read access to EEPROM2ms E10tidle Interface Blocking Time powering up with no EEPROM1 1.5ms E11t_tos Timeout TIMO=0,TOA=020µs EEPROM Interface Inputs SDA and Error Input NERRF01Vt()hi Threshold Voltage hi2V F02Vt()lo Threshold Voltage lo0.8V F03Vt()hys Hysteresis Vt()hys=Vt()hi-Vt()lo300mV F04tbusy()cfg Duration of Startup Conﬁguration error free EEPROM access57ms EEPROM Interface Outputs SDA,SCL and Error Output NERRG01f()Write/Read Clock at SCL20100kHz G02Vs()lo Saturation Voltage lo I()=4mA0.45V G03Ipu()Pull-up Current V()=0...VDD-1V-600-300-75µA G04ft()Fall Time CL()=50pF60nsG05tmin()lo Min.Duration Of Error Indicationat NERR(lo signal)MA=hi,no BiSS access,amplitude or frequenyerror10msG06Tpwm()Cycle Duration Of Error Indica-tion at NERRfosc()subdivided22260.7msG07t()lo Duty Cycle Of Error Indication atNERR signal duration low to high;AERR=0(amplitude error)75% FERR=0(frequency error)50%G08RL()Permissible Load at SDA,SCL TMA=1(calibration mode)1MΩRev D3,Page 8/30Operating Conditions:VDDA =VDD =5V ±10%,Tj =-40...125°C,unless otherwisestated.Item SymbolParameterConditionsUnitNo.Min.Typ.Max.Signal Monitoring H01Vth Voltage Threshold for Monitoring of Minimal AmplitudeVDDA =5V ,SELAMPL =0,AMPL =0x00,PHI:0°,90°,180°,270° 2.8 3.0 3.2V AMPL =0x01,PHI:0° 3.0 3.2 3.4V AMPL =0x02,PHI:0° 3.2 3.4 3.6V AMPL =0x03,PHI:0°3.4 3.6 3.8V H02Vthmax Upper Voltage Threshold for Monitoring of Sin 2+Cos2VDDA =5V ,SELAMPL =1,AMPL =0x04...0x07,PHI:0°,45°...315° 3.35 4.5 4.95V H03Vthmin Lower Voltage Threshold for Monitoring of Sin 2+Cos2VDDA =5V ,SELAMPL =1,AMPL =0x04,PHI:0°,45°...315°0.2 1.0 1.5V AMPL =0x05,PHI:45°0.6 1.5 2.0V AMPL =0x06,PHI:45° 1.1 2.0 2.5V AMPL =0x07,PHI:45°1.62.53.0VCHARACTERISTICS:DiagramsFigure 1:Deﬁnition of relative angle error and minimum transition distance0°90° 180° 270° 360°-0.15° -0.1°-0.05° 0 0.05° 0.1° 0.15°Figure 2:T ypical residual absolute angle error after calibration.Rev D3,Page9/30Operating Conditions:VDD=5V±10%,T a=-25...85°C;input levels lo=0...0.45V,hi=2.4V...VDDItem Symbol Parameter Conditions Fig.Unit No.Min.Max.SSI ProtocolI001T MAS Permissible Clock Period t tos according to T able4442502x t tos nsI002t MASh Clock Signal Hi Level Duration425t tos nsI003t MASl Clock Signal Lo Level Duration425t tos ns BiSS C ProtocolI004T MAS Permissible Clock Period t tos according to T able3451002x t tos nsI005t MASh Clock Signal Hi Level Duration525t tos nsI006t MASl Clock Signal Lo Level Duration525t tos nsFigure3:Timing diagram in SSI protocol.Figure4:Timing diagram in BiSS C protocol.Rev D3,Page10/30Register Description,Overview...........Page10 Signal Conditioning.......................Page11 GAIN:Gain SelectSINOFFS:Offset Calibration SineCOSOFFS:Offset Calibration Cosine REFOFFS:Offset Calibration ReferenceRATIO:Amplitude CalibrationPHASE:Phase CalibrationConverter Function........................Page12 SELRES:ResolutionHYS:HysteresisFCTR:Max.Permissible Converter Frequency Incremental Signals.......................Page15 CFGABZ:Output A,B,ZROT:Direction of RotationCBZ:24-bit Period Counter Conﬁguration ENRESDEL:Output Delay A,B,ZZPOS:Zero Signal PositionCFGZ:Zero Signal LengthCFGAB:Zero Signal Logic Signal Monitoringand Error Messages.......................Page17 SELAMPL:Amplitude Monitoring,function AMPL:Amplitude Monitoring,thresholds AERR:Amplitude ErrorFERR:Frequency ErrorTest Functions.............................Page18 TMODE:T est ModeTMA:Analog T est ModeBiSS Interface.............................Page19 SELSSI:Protocol VersionTIMO,TOA:TimeoutTOS:Timeout Short**M2S:Data Output and OptionsCRC6:CRC Polynomial and Status Messages NZB:Zero BitENCDS:Protocol OptionsRPL:Register Protection SettingsGRAY:SSI Data FormatWhen no register protection is active,all registers permit read and write access(see RPL). *)Reserved registers must be programmed to zero.**)For TOS see table42on page21.T able5:Register layoutRevD3,Page11/30Input stages SIN and COS are conﬁgured as instru-mentation ampliﬁers.The ampliﬁer gain must be se-lected in accordance with the input signal amplitude and programmed to register GAIN according to the fol-lowing table.Half of the supply voltage is available at VREF as a center voltage to enable the DC level to be adapted.T able6:Input gainTable7:Sine/cosine offset calibrationTable8:Offset referenceT able9:Amplitude calibrationT able10:Phase calibrationRevD3,Page12/30Table11:Binary resolutionsT able12:Decimal resolutionsRev D3,Page13/30The converter frequency automatically adjusts to the value required by the input frequency and resolution. This value ranges from zero to a maximum depen-dent on the oscillator frequency that is set via register FCTR.Serial Data OutputFor BiSS or SSI output the maximum possible con-verter frequency can be adjusted to suit the maxi-mum input frequency;an automatic converter resolu-tion step-down feature can be enabled via the FCTR register.Should the input frequency exceed the fre-quency limit of the selected converter resolution,the LSB is kept stable and not resolved any further;the interpolation resolution halves.If the next frequency limit is overshot,the LSB and LSB +1are kept stable and so on.If the input frequency again sinks below this frequency threshold,ﬁne reso-lution automatically returns.With the programming of CRC6=1a resolution step-down will be signalled via the BiSS warning bit.Table14:Maximum converter frequency for serial data output.Rev D3,Page14/30Incremental Output to A,B and ZSettings for the maximum possible converter fre-quency using register FCTR are governed by two cri-teria:1.The maximum input frequency2.System restrictions caused by slow counters or data transmission via cableIn this case it is sensible to preselect a minimum tran-sition distance for the output signals.These settings also make a suitable zero-delay digital glitchﬁlter that acts on ESD impact on the sensor and keeps the out-put signals spike free through temporal separation,for example.Serial data output is possible at any time in BiSS or SSI protocol.However,for the transfer of angle data to the output register the incremental output is halted for one period of the clock signal at pin MA.Table15:Maximum possible converter frequency for incremental A/B/Z output, deﬁned by the maximum input frequencyTable16:Maximum possible converter frequency for incremental A/B/Z output, deﬁned by the minimum transition distanceRevD3,Page15/30T able17:Outputs A,B,ZTable18:Code directionTable19:Reset enable for period counterTable20:Output delay A,B,ZABZFigure11:Period counter reset by zero signal(en-abled by CBZ=1).Example gives a resolution of64(SELRES=0x0A),a zero signal at45°(ZPOS=0x04,CFGAB=0x00)and noinversion of the direction of rotation(ROT=0x00,COS leads SIN).Rev D3,Page 16/30Table 21:Zero signal positionT able 22:Zero signal lengthT able 23:Zero signal logic-180°-90°0°45°90°180°WinkelSINCOSA BZ (CFGZ= 1)Z (CFGZ= 2)Z (CFGZ= 0)Figure 12:Incremental output signals for various zero signal lengths.Example gives a resolution of 64(SELRES =0x0A),a zero signal position of 45°(ZPOS =0x04,CFGAB =0x00)and no inversion of the direction of rotation (ROT =0x00,COS leads SIN).Rev D3,Page17/30Table 24:Signal amplitude monitoringTable 25:Amplitude errorTable 26:Frequency errorTable 27:Conﬁguration errorTable 28:Error indication at NERRFigure 13:Signal monitoring of minimumamplitude.Figure 14:Sin 2+Cos 2signal monitoring.T able 29:Error messagesT o enable the diagnosis of faults,the various types of error are signaled at NERR using a PWM code as given in the key on the left.T wo error bits are provided to enable communication via the I/O interface;these bits can decode four differ-ent types of error.If NERR is held at low by an external source,such as an error message from the system,for example,this can also be veriﬁed via the I/O interface.Error are stored until the sensor data is output via the I/O interface and then deleted.Errors at NERR are displayed for a minimum of ca.10ms unless they are deleted beforehand by a data output.Rev D3,Page 18/30If an error in amplitude occurs,conversion is termi-nated and the incremental output signals halted.Anerror in amplitude rules out the possibility of an errorin frequency.Table 30:T est modeT able 31:Analog test modeSDA: Sin+A: COS+5 VX/Y 0 V1 V/Div vert. 1 V/Div hor.Y/T 1 V/Div vert.Figure 15:Calibrated signals in TMA mode.The signal is set to ca.4Vpp using GAIN and must not be altered after calibration.Both display modes are suitable for OFFS (positive values)and RA TIO adjust-ments;X/Y mode is preferable for PHASE.T est signals COS-(pin B)and SIN-(pin SCL)must be selected to set negative values for OFFS.Rev D3,Page19/30The serial I/O interface operates in BiSS C protocol mode and enables sensor data to be output in uninter-ruptible cycles(data channel SCD).At the same time parameters can be exchanged via bidirectional register communication(data channel CD).The sensor data produced by iC-NQC contains the an-gle value(S)with3to13bits,the period count(P)with 0,8,12or24bits,two error bits(E1and E0)and5or 6CRC bits(CRC).Figure16:Example line signals(BiSS C)Table32:BiSS data channels Interface Parameters With BiSS C ProtocolT able33:Protocol versiontos fclk(MA)min*50kHz660kHzspeciﬁcation50kHzto32fosc(see El.Char.,clock frequency is speciﬁedT able34:Timeout conﬁguration(protectable)T able35:Period counter output T able36:CRC Polynomial and status messagesRev D3,Page20/30T able37:Zero bitTable38:Protocol optionsM2S can be used to set the number of period counter bits sent as sensor data.The counter bits are trans-mitted before the angle value,with the MSB leading.The5-bit CRC output is based on polynomial0x25 (100101b),with the6-bit CRC output based on poly-nomial0x43(1000011b)automatically coming active with longer SCD data,or when preselected by CRC6. As a rule,CRC bits are sent inverted.An additional zero bit can be output following the CRC bits.However,disabling the zero bit by NZB=1is rec-ommended when the output data length does not need to comply with existing applications.To obtain a position data output being compatible to the BiSS B protocol parameter ENCDS=0does switch off the CDS bit,without a replacement by a zero bit.Thus, the output data length is shorten by one bit and register communication is limited to the direction of the master to the slave.The bidirectional BiSS C register commu-nication must be enabled by setting ENCDS=1. Example of BiSS Data OutputTable39:Example format1for BiSS proﬁle BP1T able40:Example format2T able41:Example format3Register CommunicationAfter the BiSS C protocol slave registers are directly addressed in a reserved address area(0x40to0x7F). Other storage areas are addressed dynamically and in blocks.BiSS addresses0x00to0x3F aim for a reg-ister bank consisting of64bytes,the physical storage address of which is determined by Bank Select n.iC-NQC supports up to16storage banks,making it possible to use an8-bit EEPROM to its full capacity. There is therefore also enough storage space for an ID plate(EDS)and OEM data.Information regarding memory map and addressing via BiSS is given on page25).Internal Reset FunctionA write access at RAM address0x00(BiSS address 0x00with Bank Select n=0)triggers an internal reset. Based on the current conﬁguration in the RAM,iC-NQC restarts without reading the EEPROM.The con-ﬁgured interface timeout and write protect settings be-come active,the period counter is set to zero and any stored conﬁguration errors are deleted.The data out-put via SLO and the incremental signals at A,B and Z are released.Providing no amplitude error is present, the converter again counts up from an angle value of zero to the current angle position.Short BiSS TimeoutFor programming via the I/O interface iC-NQC has a short BiSS timeout function according to the descrip-tion of the BiSS C protocol(see page19,T able2,El. Char.no.6).Rev D3,Page21/30Regardless of register protection settings a short time-out of typically1.8µs can be temporarily activated by writing value0x07to address0x7C(address124d).A controller can then transmit the device conﬁguration over a shorter period.Table42:Short timeout(via BiSS device ID)The value written to address0x7C is also transferred to the EEPROM,provided an EEPROM has been con-nected up and is available.On reading address0x7C the byte stored in the EEP-ROM is output as part of the BiSS device ID.Here, high-order bits7:3are part of the manufacturer’s ID; low-order bits2:0act as an indicator of the timeout op-tions(regular or short timeout,see T able42).Rev D3,Page22/30iC-NQC can transmit position data in SSI protocol mode;the parameters described in the following give the necessary settings andoptions.Figure 17:Example line signal (SSI)Table 43:Protocol versionTable 44:Timeout conﬁguration for SSIT able 45:Period counter for SSI data outputT able 46:Options for SSI data outputT able 47:SSI data formatRev D3,Page23/30 Examples of SSI Data OutputT able48:SSI transmission formatsRev D3,Page24/30The serial EEPROM interface consists of the two pins SCL and SDA and enables read and write access to a serial EEPROM with I2C interface(with at least128 bytes,5V type with a3.3V function; e.g.24C01, 24C02,24C08and maximal24C16).The conﬁguration data in the EEPROM,of addresses 0x00to0x0F,is secured by a CRC check value to ad-dress0x0F.When the device is powered up,the ad-dress range from0x00to0x0F is mapped onto iC-NQC’s conﬁguration RAM.The higher memory area contains BiSS C slave registers and optional memory banks available to the sensor system.The register access to the conﬁguration data and the memory banks1to7(intended for EDS)can be re-stricted by parameter RPL.N.B.When writing conﬁguration data to the EEPROM (BiSS addresses0x10to0x1F)a wait time of at least 4ms must be allowed after each register.Example of CRC Calculation Routineunsigned char ucDataStream=0;i n t iCRCPoly=0x127;unsigned char ucCRC=0;i n t i=0;ucCRC=0;//s t a r t value!!!for(iReg=0;iReg<15;iReg++){ucDataStream=ucGetValue(iReg);for(i=0;i<=7;i++){i f((ucCRC&0x80)!=(ucDataStream&0x80))ucCRC=(ucCRC<<1)^iCRCPoly;elseucCRC=(ucCRC<<1);ucDataStream=ucDataStream<<1;}}T able49:Check value for EEPROM dataT able50:Register overviewT able51:Register protection settingsRev D3,Page 25/302 k b i t / 24C 028 k b i t / 24C 0816k b i t / 24C 16R e g i s t e r s (B a n k n )D i r e c t A c c e s s R egi s t ersRegisterProtectionFigure 18:Registers and addressingStartup With A Conﬁgured EEPROMAfter the supply has been turned on (power-on reset),iC-NQC reads the conﬁguration data from the EEP-ROM.During this phase it actively keeps error pin NERR at a low signal (open drain output),and data output SLO and the incremental signals at A,B and Z at a high signal.After a successful CRC the data output to SLO and to the incremental A,B,and Z outputs is released and the error indication at pin NERR reset;an external pull-up resistor at pin NERR can supply a high signal.iC-NQC then switches to normal operation and determines the current angle position,providing that a sensor is con-nected up to it and there is no amplitude error (or this is deactivated).Should the CRC prove unsuccessful due to a data er-ror (disrupted transmission,no EEPROM or the EEP-ROM is not programmed),the conﬁguration phase is automatically repeated.After a third failed attempt,the procedure is aborted and error pin NERR displays a permanent low;data output SLO and the incremental signals at A,B and Z remain at a high signal.Startup Without An EEPROMThe conﬁguration RAM contains random values after startup;iC-NQC does not have a default conﬁguration.Error pin NERR shows a low signal (open drain out-put);data output SLO and the incremental signals at A,B and Z indicate a high signal.T o reduce the device conﬁguration time,a short time-out of 3µs maximum (cf.TIMO =1and TOA =0)can be temporarily activated by writing value 0x07to ad-dress 0x7C (address 124d).When operated without an EEPROM,iC-NQC does not respond to higher addresses -with the exception of the BiSS addresses reserved for manufacturer and device IDs (0x78to 0x7F).This address area supplies the chip version from the ROM.Initialization After Conﬁguration FailureSo that it is always possible to talk to iC-NQC via the I/O interface,iC-NQC ﬁrst ignores the register values of TIMO,TOA,RPL and TMA.Instead,iC-NQC ap-plies the longest timeout (cf.TIMO =0and TOA =0),ignores safety settings (cf.RPL =0x0)and evaluates the BiSS register communication (CDM bit from the CD data channel).Rev D3,Page 26/30During this phase regular bidirectional BiSS register communication is not yet possible,as data output SLO is permanently kept at high.Writing the conﬁguration to RAM addresses 0x01to 0x0C and to address 0x00must be executed without evaluating a reply.Data in-put SLI is ignored;iC-NQC always uses slave ID 0.lowing ﬁgures each show a single cycle with CDM =0and CDM =1.A wide range of 100ns to 12.5µs is per-missible for clock period T(MA);the timeout must last at least 30µs.A complete write cycle requires 14cycles at CDM =0Rev D3,Page 27/30or current source signals with ground ref-current source outputs,such as for op-toencoder iC-WG.signals.RS3/4and CS1serve as protec-tion against ESD and transients.Rev D3,Page28/30 Input Circuit for Sine Encoders(1Vpp)Figure28:Input circuit for sine encoders(0.8Vpp to1.2Vpp)with120Ωtermination and low-passﬁltering.R2/R3serve as protection against ESD and transients,R4/R5reduce the input signal to suit aninput gain of8.Basic Circuit for MRSensorsRev D3,Page29/30iC-NQC comes with a demo board for test purposes.Instructions are available separately.Table52:Notes on chip functions regarding iC-NQC chip release2.Table53:Notes on chip functions regarding iC-NQC chip release3.Table54:Notes on chip functions regarding iC-NQC chip release5.iC-Haus expressly reserves the right to change its products and/or speciﬁcations.An info letter gives details as to any amendments and additions made to the relevant current speciﬁcations on our internet website www.ichaus.de/infoletter;this letter is generated automatically and shall be sent to registered users by email.Copying–even as an excerpt–is only permitted with iC-Haus’approval in writing and precise reference to source.iC-Haus does not warrant the accuracy,completeness or timeliness of the speciﬁcation and does not assume liability for any errors or omissions in these materials.The data speciﬁed is intended solely for the purpose of product description.No representations or warranties,either express or implied,of merchantability,ﬁtness for a particular purpose or of any other nature are made hereunder with respect to information/speciﬁcation or the products to which information refers and no guarantee with respect to compliance to the intended use is given.In particular,this also applies to the stated possible applications or areas of applications of the product.iC-Haus conveys no patent,copyright,mask work right or other trade mark right to this product.iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.。

FPGA可编程逻辑器件芯片5CGXFC5C6M13I7N中文规格书

number is the minimum timing parameter for commercial devices.
Stratix II Device Handbook, Volume 1
Hot Socketing & Power-On Reset
IIOPIN is the current at any user I/O pin on the device. This specification takes into account the pin capacitance, but not board trace and external loading capacitance. Additional capacitance for trace, connector, and loading needs must be considered separately. For the AC specification, the peak current duration is 10 ns or less because of power-up transients. For more information, refer to the Hot-Socketing & Power-Sequencing Feature & Testing for Altera Devices white paper.
PLL1 PLL2
Support PLL-Based Implementation
Support PLL-Based Implementation
PLL4 PLL3
VREF 0B1 VREF 1B1 VREF 2B1 VR EF3B1 VR EF4B1

数字IC电源静噪和去耦应用手册

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配电网（PDN） IC2 返回信号电流信号电流去耦电路电源电流供电电源IC 平滑电路噪声排放噪声进入 IC3 IC1 目标 IC 此图仅仅以集成电路的去耦电路操作为重点。噪声产生噪声接收 IC 接收 IC 去耦电路工作： (1) 抑制噪声 (2) 供应临时电流 (3) 形成信号返回通道
注
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Silicon Storage Technology DS75054A_CN 数据手册说明书

数据手册特性•高增益：–在-40°C至+85°C的温度范围内，从2.4 GHz到2.5 GHz 的增益典型值为33 dB•高线性输出功率–>30 dBm P1dB-请参见第5页上的“绝对最大极限参数”–功率高达28.5 dBm时仍满足802.11g OFDM频谱模板的要求–对于功率最高为25 dBm的54 Mbps 802.11g信号，EVM 约为3%–对于功率最高为23.5 dBm时的802.11n HT40信号，EVM为2.5%–对于功率最高为21.5 dBm时的802.11ac MCS8信号，EVM为1.75%–功率高达28.5 dBm的时候仍满足802.11b ACPR的要求•高速上电/掉电–开启/关断时间（10%-90%）<100 ns•10:1 VSWR稳定性（功率高达28.5 dBm时仍无条件稳定）•片上功率检测–20 dB动态范围–对VSWR和温度不敏感•简单的输入/输出匹配•可用封装–16触点VQFN（3 mm x 3 mm）•所有无铅器件均符合RoHS标准应用•WLAN（IEEE 802.11b/g/n）•AP路由器•WiMax（IEEE 802.16e）•家用RF•无绳电话•2.4 GHz ISM无线设备•1.8 GHz Pico CellSST12CP11是基于高度可靠的InGaP/GaAs HBT技术的高功率及高增益功率放大器（Power Amplifier，PA）。

该功率放大器可方便地针对高功率应用进行配置，当工作在2.4-2.5 GHz的频带时具有良好的功率附加效率。

对于Pico Cell应用，它还可以配置为工作在1.8 GHz。

SST12CP11可提供典型值为33 dB的增益且具有良好的线性度，对于54 Mbps 802.11g操作，当输出功率为25 dBm时EVM通常约为 3%，同时满足28.5 dBm时的802.11g频谱模板。

集驰(三端稳压电压检测芯片)电源管理产品手册

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电压检测芯片
ＣＭＯＳ输出７０ＸＸＣ系列
输出电流检测电压
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李明？（ＬＥＭＯＮＬＩ）上海集驰电子有限公司？－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－ＳｈａｎｇＨａｉＪＩＣＨＩＥｌｅｃｔｒｏｎｉｃｓＣｏ．，Ｌｔｄ－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－－Ｔｅｌ：０８６－２１－５４９３９３７７Ｆａｘ：０８６－２１－５４９３９３４４ＭｏｂｉｌｌｅＰｈｏｎｅ：０８６－１３７０１６０７９４４Ｅ－ｍａｉｌ：ｌｍｎｘ６６８＠１６３．ｃｏｍ
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低压差稳压７５ＸＸ系列（１８伏）
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74LVC1G08-Q100 2-输入AND门单片IC数据手册说明书

74LVC1G08-Q100Single 2-input AND gateRev. 3 — 25 January 2019Product data sheet1. General descriptionThe 74LVC1G08-Q100 provides one 2-input AND function.Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devicesas translators in mixed 3.3 V and 5 V applications.Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall time.This device is fully specified for partial power-down applications using I OFF. The I OFF circuitrydisables the output, preventing the damaging backflow current through the device when it ispowered down.This product has been qualified to the Automotive Electronics Council (AEC) standard Q100(Grade 1) and is suitable for use in automotive applications.2. Features and benefits•Automotive product qualification in accordance with AEC-Q100 (Grade 1)•Specified from -40 °C to +85 °C and from -40 °C to +125 °C•Wide supply voltage range from 1.65 V to 5.5 V•High noise immunity•Complies with JEDEC standard:•JESD8-7 (1.65 V to 1.95 V)•JESD8-5 (2.3 V to 2.7 V)•JESD8-B/JESD36 (2.7 V to 3.6 V)•±24 mA output drive (V CC = 3.0 V)•CMOS low power consumption•Latch-up performance ≤ 250 mA•Direct interface with TTL levels•Inputs accept voltages up to 5 V•ESD protection:•MIL-STD-883, method 3015 exceeds 2000 V•HBM JESD22-A114F exceeds 2000 V•MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)3. Ordering information4. Marking[1]The pin 1 indicator is located on the lower left corner of the device, below the marking code.5. Functional diagrammna113B AY214Fig. 1.Logic symbol mna11424&1Fig. 2.IEC logic symbol mna221ABYFig. 3.Logic diagram6. Pinning information6.1. Pinning74LVC1G08B V CCA GNDY001aab63812354Fig. 4.Pin configuration SOT353-1 (TSSOP5)and SOT753 (SC-74A)74LVC1G08A001aab639BGND n.c.V CCYT ransparent top view231546Fig. 5.Pin configuration SOT886 (XSON6)6.2. Pin description7. Functional description[1]H = HIGH voltage level; L = LOW voltage level8. Limiting valuesTable 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).[1]The input and output voltage ratings may be exceeded if the input and output current ratings are observed.[2]For TSSOP5 and SC-74A packages: above 87.5 °C the value of P tot derates linearly with 4.0 mW/K.For XSON6 package: above 118 °C the value of P tot derates linearly with 7.8 mW/K.9. Recommended operating conditions10. Static characteristicsTable 7. Static characteristicsAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).[1]All typical values are measured at V CC = 3.3 V and T amb = 25 °C.11. Dynamic characteristicsTable 8. Dynamic characteristicsVoltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7.[1]Typical values are measured at T amb = 25 °C and V CC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.[2]t pd is the same as t PLZ and t PZL.[3]C PD is used to determine the dynamic power dissipation (P D in μW).P D = C PD × V CC2 × f i × N + ∑(C L × V CC2 × f o) where:f i = input frequency in MHz;f o = output frequency in MHz;C L = output load capacitance in pF;V CC = supply voltage in V;N = number of inputs switching;∑(C L × V CC2 × f o) = sum of outputs.11.1. Waveforms and test circuit12. Package outlineTSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1Fig. 8.Package outline SOT353-1 (TSSOP5)Plastic surface-mounted package; 5 leads SOT753Fig. 9.Package outline SOT753 (SC-74A)Fig. 10.Package outline SOT886 (XSON6)13. Abbreviations14. Revision history15. Legal informationData sheet status[1]Please consult the most recently issued document before initiating orcompleting a design.[2]The term 'short data sheet' is explained in section "Definitions".[3]The product status of device(s) described in this document may havechanged since this document was published and may differ in case ofmultiple devices. The latest product status information is available onthe internet at https://.DefinitionsDraft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet.DisclaimersLimited warranty and liability — Information in this document is believedto be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracyor completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia.In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removalor replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia.Right to make changes — Nexperia reserves the right to make changesto information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted tobe suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well asfor the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect.Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above thosegiven in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.Terms and conditions of commercial sale — Nexperia products aresold subject to the general terms and conditions of commercial sale, as published at /profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer.No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.TrademarksNotice: All referenced brands, product names, service names and trademarks are the property of their respective owners.Contents1. General description (1)2. Features and benefits (1)3. Ordering information (1)4. Marking (2)5. Functional diagram (2)6. Pinning information (2)6.1. Pinning (2)6.2. Pin description (2)7. Functional description (3)8. Limiting values (3)9. Recommended operating conditions (3)10. Static characteristics (4)11. Dynamic characteristics (5)11.1. Waveforms and test circuit (5)12. Package outline (7)13. Abbreviations (10)14. Revision history (10)15. Legal information (11)© Nexperia B.V. 2019. All rights reservedFor more information, please visit: Forsalesofficeaddresses,pleasesendanemailto:*************************** Date of release: 25 January 2019Mouser ElectronicsAuthorized DistributorClick to View Pricing, Inventory, Delivery & Lifecycle Information:N experia:74LVC1G08GV-Q100,174LVC1G08GW-Q100,174LVC1G08GM-Q100X。

PL3201芯片手册V1.7

芯片手册版本1.7目录芯片手册 (1)目录 (1)PL3201芯片特点及功能概述 (4)1)特点 (4)2)功能概述 (4)电能计量部分（必须使用9.6MHz晶体）： (4)微处理器部分： (5)外围部分： (5)PL3201芯片技术指标、封装和管脚定义 (5)1)电器参数 (5)2)极限参数 (6)3)封装参数 (6)PL3201芯片工作原理及应用指南 (14)1.芯片内部功能模块框图 (14)2.各模块工作原理及应用指南 (14)1)电能计量模块 (14)电能计量工作原理 (14)计量输出设置 (15)计量部分与8051 数据交换 (15)电能计量工作过程 (16)寄存器 (16)2)增强型8051的微处理器MCU (2120)8051 MCU资源配置 (2120)程序控制部分功能 (21)上电复位与电源监测 (24)看门狗定时器 (2524)电压比较器 (2625)3)载波通信 (26)功能简述 (26)编程指南 (26)载波通信的工作步骤 (27)寄存器 (28)4)LCD/LED显示驱动 (32)功能简述 (32)LED编程指南 (32)LCD编程指南 (33)LCD循显 (34)寄存器 (3534)5)UART 功能 (36)功能简述 (36)编程指南 (36)寄存器 (36)6)FGEN可编程频率发生器功能 (37)功能简述 (37)编程指南 (37)寄存器 (37)7)TS温度频率转换器 (38)功能简述 (38)编程指南 (38)寄存器 (38)8)多协议红外通信解码功能 (39)功能简述 (39)编程指南 (39)寄存器 (40)9)ISO7816功能 (41)功能简述 (41)编程指南 (41)寄存器 (42)10)嵌入式E2PROM数据存储器 (46)功能简述 (46)编程指南 (46)寄存器 (47)11)在系统编程与下载工具 (48)功能简述 (48)编程指南 (50)程序与数据的下载 (51)12)实时钟及其数字调校 (52)功能简述 (52)编程指南 (52)寄存器 (5453)PL3201芯片的使用及典型应用举例 (55)校表 (55)单相复费率载波通信多功能电表应用 (57)电能计量应用一（电压/电流互感器采样方式） (58)电能计量应用二（锰铜电阻分压采样方式） (59)载波通讯 (60)红外通讯 (61)LCD显示驱动 (62)附录A: PL3201寄存器快速查询表 (63)PL3201特殊功能寄存器（SFR）列表 (63)电能计量单元（PMU）地址分配表 (64)（必须使用9.6MH Z晶体） (64)扩频通信单元（SSC）地址分配表（必须使用9.6MH Z晶体） (65)外部设备地址分配表 (65)PL3201芯片特点及功能概述1)特点☆ 采用0.35um 超大规模数/模混合CMOS制造工艺；☆ 拥有多项自主知识产权的SoC（System on Chip）设计；☆ 内置高精度数字多功能电能计量电路，计量标准完全符合国标GB/T 17883和GB/T 17215（等效于IEC687/1036）。

Vicor设计指南和应用手册(CHINESE)

焊接方法建议无铅引脚 (RoHS) 锡/含鉛引腳
安装选择表面安装插座系统（SurfMate）穿孔插座安装系统（InMate）
技术术语汇编
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初级控制集成电路
次级控制集成电路
图 1-3 ─ 全型、小型、微型模块的功率处理和控制基本原理（* 微型系列没有 +/- SENSE 引脚）
第4页
(852)2956-1782 vicorhk@
Rev.4.0
设计指南和应用手册
全型、小型和微型系列 DC-DC 转换器及配件模块
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(852)2956-1782 vicorhk@
Rev.4.0 第1页
1. 高密度 DC-DC 转换器技术
设计指南和应用手册
元件数目减少自然提高产品可靠性及降低成本，令模块内多出来的空间，可以放置电磁和开关元件，集中处理
功率转换，意味着模块的功率转换性能可以做得更卓越。
如有需要，可用电阻器调整输出电压高低。Vicor DC-DC 转换器模块有六种引脚类型、三种基板选择，及齐备的数据表和不同的测试报告。模块的操作温度范围在 -55℃ 到 100℃ 之间，并分成五个产品级别 — E、 C、T、H 和 M。

FPGA可编程逻辑器件芯片5SGTMC7K3F40C1N中文规格书

Switching CharacteristicsStratix V Device DatasheetTable 24 shows the maximum transmitter data rate for the clock network.Table 24. Clock Network Maximum Data Rate Transmitter Specifications (1) Clock Network ATX PLLCMU PLL (2)fPLL Non-bondedMode(Gbps)Bonded Mode (Gbps)Channel Span Non-bonded Mode (Gbps)Bonded Mode (Gbps)Channel Span Non-bonded Mode (Gbps)Bonded Mode (Gbps)Channel Span x1 (3)14.1—612.5—6 3.125—3x6 (3)—14.16—12.56— 3.1256x6 PLL Feedback (4)—14.1Side-wide —12.5Side-wide ———xN (PCIe)—8.08— 5.08———xN (Native PHY IP)8.08.0Up to 13channelsaboveandbelowPLL7.997.99Up to 13 channels above and below PLL 3.125 3.125Up to 13 channels above and below PLL—8.01 to 9.8304Up to 7channelsaboveandbelowPLL Notes to Table 24:(1)Valid data rates below the maximum specified in this table depend on the reference clock frequency and the PLL counter settings. Check theMegaWizard message during the PHY IP instantiation.(2)ATX PLL is recommended at 8 Gbps and above data rates for improved jitter performance.(3)Channel span is within a transceiver bank.(4)Side-wide channel bonding is allowed up to the maximum supported by the PHY IP.Switching CharacteristicsStratix V Device Datasheet Table 25 shows the approximate maximum data rate using the standard PCS.Table 25. Stratix V Standard PCS Approximate Maximum Date Rate (1), (3)Mode (2)TransceiverSpeed GradePMA Width20201616101088PCS/Core Width402032162010168FIFO 1C1, C2, C2L, I2, I2Lcore speed grade12.211.49.769.12 6.5 5.8 5.2 4.72 2C1, C2, C2L, I2, I2Lcore speed grade12.211.49.769.12 6.5 5.8 5.2 4.72C3, I3, I3Lcore speed grade9.89.07.847.2 5.3 4.7 4.24 3.76 3C1, C2, C2L, I2, I2Lcore speed grade8.58.58.58.5 6.5 5.8 5.2 4.72I3YYcore speed grade10.3125 10.31257.847.2 5.3 4.7 4.24 3.76C3, I3, I3Lcore speed grade8.58.57.847.2 5.3 4.7 4.24 3.76C4, I4core speed grade8.58.27.04 6.56 4.8 4.2 3.84 3.44Register 1C1, C2, C2L, I2, I2Lcore speed grade12.211.49.769.12 6.1 5.7 4.88 4.56 2C1, C2, C2L, I2, I2Lcore speed grade12.211.49.769.12 6.1 5.7 4.88 4.56C3, I3, I3Lcore speed grade9.89.07.927.2 4.9 4.5 3.96 3.6 3C1, C2, C2L, I2, I2Lcore speed grade10.312510.312510.312510.3125 6.1 5.7 4.88 4.56I3YYcore speed grade10.312510.31257.927.2 4.9 4.5 3.96 3.6C3, I3, I3Lcore speed grade8.58.57.927.2 4.9 4.5 3.96 3.6C4, I4core speed grade8.58.27.04 6.56 4.4 4.1 3.52 3.28Notes to Table 25:(1)The maximum data rate is in Gbps.(2)The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latencycan vary. In the register mode the pointers are fixed for low latency.(3)The maximum data rate is also constrained by the transceiver speed grade. Refer to Table 1 for the transceiver speed grade.。

FPGA可编程逻辑器件芯片XQVU7P-2FLQB2104I中文规格书

Interfacing to Mobile SDRAM with CoolRunner-II CPLDsTable 2: SDRAM State Machine State DescriptionState Name FunctionACTIVE_ST Assign SDRAM command value to execute an ACTIVEcommand. Assign row address to SDRAM address bus.WAIT_READ_ST Execute NOP instruction. Necessary to meet timing specificationfor t RCD.READ_ST Issue READ instruction by assigning SDRAM signals. Assigncolumn address to address bus.CAS_DELAY_ST Wait for specified CAS latency of READ operation. Enable CASlatency counter, cas_cnt_en, is asserted.READ_DATA_ST Read data from SDRAM. Assert sdram_read_en signal to datacontrol logic block. Enable rd_brst_qout counter. Remain in thisstate for length of specified burst to capture all data.WAIT_WRITE_ST Execute NOP instruction. Necessary to meet timing specificationfor t RCD.WRITE_ST Assign WRITE command values to SDRAM to issue WRITEinstruction. Assign column address to address bus.WRITE_DATA_ST Enable data write to SDRAM by asserting sdram_write_en signalto data control logic block. Enable wr_brst_qout counter. Wait forend of write burst length.WAIT_TWR Execute NOP instruction. Necessary to meet timing specificationfor write recovery, t WR.WAIT_TRP Execute NOP instruction. Necessary to meet timing specificationfor precharge command period, t RP.Device UtilizationThe SDRAM interface design utilizes a CoolRunner-II XC2C128-4TQ144 device. The systeminterface, SDRAM state machine, and SDRAM interface logic fits into this device with theutilization results shown in Table3.Table 3: CoolRunner-II Design UtilizationParameter Used Available% UtilizationI/O Pins8610086%Macrocells10212880%Product Terms18044840%Registers10012878%Function Block Inputs12632039%System InterfaceThe SDRAM design described in this document includes a generic system interface. Thesystem interface illustrates the basic control signals needed for the SDRAM logic block. Thesesignals include a system clock, reset, 24-bit address bus, 16-bit data bus, and 4-bit commandbus. Excluding the system clock, all signals are asynchronous and registered in the CPLD.Modeling of the system interface in this design is done with testbench logic. The testbench isresponsible for generating the address, data and command signals for any operation with the XAPP394 (v1.1) December 1, 2003Expanding I/O Expanding I/O Designers faced with accommodating a keypad requiring more I/O might find their existingprocessor (or ASIC) does not have enough GPIO ports. One solution is to use a CPLD as anI/O expander that reduces the I/O requirement of the processor.Figure2 shows a CPLD interfacing to the keypad rows/columns on one side, and theprocessor’s available GPIO on the other. In this example, an 8 x 8 keypad requires the samenumber of processor GPIO ports as the 4 x 4 keypad (actually one less) when a CPLD is used.Without a CPLD, the processor would require 16 GPIO ports instead of 7.Figure 2: CPLD Expands I/O and Reduces the Processor’s GPIOScanning and Encoding Besides reducing the processor’s GPIO requirements, the CPLD also scans the rows and monitors the columns for a change in state. When a key is pressed, the CPLD stops scanning and immediately sends an encoded word out to the processor. The encoded word indicates which key was pressed.In the example shown in Figure2, there are six bits used to represent the encoded word. Six bits provides 26 or 64 different values each representing a different key. However, one value needs to be used to represent the state when no keys are pressed. Therefore, only 63 keys can be represented in this example.All 64 keys most likely would not be needed in a typical application. If they were, there are many options with a programmable CPLD. For instance, a CPLD could generate an enable signal to the processor that would indicate when a key is being pressed (that is, when the encoded value was valid). This would require one more GPIO on the processor.The processor is still required to monitor for changes on its GPIO, only it would not have to deduce which key was pressed since this information is encoded in the six bit word. Debounce will also be required. This can be performed in the CPLD or the processor. Performing this inthe processor would keep the size of the CPLD to a minimum.XAPP512 (v1.1) May 6, 2005。

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