CY7C1051DV33芯片手册

PRELIMINARY 8-Mbit (512K x 16) Static RAM

CY7C1051DV33

Features

•High speed —t AA = 10 ns •Low active power

—I CC = 110 mA @ 10 ns •Low CMOS standby power —I SB2 = 20 mA •2.0V data retention

•Automatic power-down when deselected •TTL-compatible inputs and outputs

•Easy memory expansion with CE and OE features

•

Available in lead-free 48-ball FBGA and 44-pin TSOP II packages

Functional Description [1]

The CY7C1051DV33 is a high-performance CMOS Static RAM organized as 512K words by 16 bits.

Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW,then data from IO pins (IO 0–IO 7), is written into the location specified on the address pins (A 0–A 18). If Byte HIGH Enable (BHE) is LOW, then data from IO pins (IO 8–IO 15) is written into the location specified on the address pins (A 0–A 18).

Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH.If Byte LOW Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on IO 0–IO 7.If Byte HIGH Enable (BHE) is LOW, then data from memory will appear on IO 8 to IO 15. See the “Truth Table” on page 8 for a complete description of Read and Write modes.

The input/output pins (IO 0–IO 15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or a Write operation (CE LOW,and WE LOW) is in progress.

The CY7C1051DV33 is available in a 44-pin TSOP II package with center power and ground (revolutionary) pinout, as well as a 48-ball fine-pitch ball grid array (FBGA) package.

Note

1.For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at .

1415Logic Block Diagram

A 1A 2A 3A 4A 5A 6A 7A 8

COLUMN DECODER

R O W D E C O D E R

S E N S E A M P S

INPUT BUFFER

512K × 16ARRAY

A 0A 11A 13A 12A A A 16A 17A 18

A 9A 10IO 0–IO 7OE IO 8–IO 15

CE WE BLE

BHE

PRELIMINARY CY7C1051DV33

Selection Guide

–10

Unit Maximum Access Time 10ns Maximum Operating Current 110mA Maximum CMOS Standby Current

20

mA

Pin Configurations [2]

48-ball Mini FBGA

WE V CC A 11

A 10

NC A 6A 0A 3CE IO 10IO 8IO 9A 4A 5IO 11IO 13IO 12IO 14IO 15V SS A 9

A 8

OE V SS A 7IO 0BHE NC A 17A 2A 1BLE V CC IO 2IO 1IO 3IO 4IO 5IO 6IO 7A 15A 14A 13A 12NC A 18

NC

326541D E B A C F G H

A 16(Top View)

TSOP II

WE 1234567891011143132363534333740393812134144434216152930V CC A 5A 6A 7A 8A 0

A 1OE V SS A 17IO 15A 2CE IO 2IO 0IO 1BHE A 3A 418172019IO 32728252622

2123

24V SS IO 6IO 4IO 5IO 7A 16A 15BLE V CC IO 14IO 13IO 12IO 11IO 10IO 9IO 8A 14A 13A 12A 11A 9

A 10

A 18(Top View)

Note

2.NC pins are not connected on the die