折叠式共源共栅放大器设计
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2
Step 8 Step 9 Step 10
5 Benjamin Lutgen
Motivation (2)
The high voltage CMOS Technology H35 provides a high voltage capability up to 50V. In the project, the symmetrical 20V variant with thick oxide is used („xMOS20HS“) Disadvantage: • Less K’n/K’p as in 3.3V technology
= = = = = = = = = = = = = = =
1,00 123 123 1,00 123 123 417,00 Ohm 417,00 Ohm
Ratio I7 to I9
= = = = = = = = = = = = =
1,23E+02 1,23E+02 Factor i711 1,23E+02 1,23E+02 4,17E+02 4,17E+02 1,28E-01 1,28E-01 3,33E-01 4,17E-01 82,6446281 82,6446281 1,84E-01
in µA/V²
20V
12 35
3.3V
50 110
Technology Technology
K‘p K‘n
6
Benjamin Lutgen
2. Schematic Design
7
Benjamin Lutgen
Practical Version of the Amplifier
Figure 6.5-7 from Allen/Holberg [1]
Biblioteka Baidu
1. Introduction
3
Benjamin Lutgen
Given Objectives
Objective of the project: • design of an folded cascode operational amplifier • using a new high voltage technology („H35“ 20 V) Meeting these specifications Î
3. Layout Design
– High Voltage Layouting – Final Layout
• Functional Groups
2. Schematic Design
– Practical Version of the Amplifier – Schematic Description – Design Plan
4
Benjamin Lutgen
Motivation (1)
The used folded cascode topology offers the following properties: • good common-mode range • self compensation • High gain • Relatively low power-dissipation • High output resistance The special challenge of this project was the transfer of this circuit to a high voltage CMOS technology
Benjamin LUTGEN Wintersemester 2008/2009 Supervisor: Prof. Dr.-Ing. Andreas König
Benjamin Lutgen
1
Overview
1. Intoduction
– Given Objectives – Motivation
S. Nr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Characteristics Open loop Gain Gain Bandwidth Phase margin Settling Time Slew Rate Offset Input CMR Output Swing CMRR Power Dissipation Area Consumption Voltage Supply Load Capacitance Load Resistance Specification values > 100 dB 10 MHz > 60 ° < 1 µs 200 V/µs 5 µV ±6V ±8V > 100 dB Minimum Minimum 20 V 10 pF 100 kΩ
Integrated Sensor Systems
Dept. of Electrical Engineering and Information Technology
Institute of
Design of an Folded Cascode Operational Amplifier in High Voltage CMOS Technology
Step 1 Step 2
I3 I4 I5
= = = = = = = = = = = = =
2,00E-03 A Factor k 2,40E-03 A 2,40E-03 A 1V 1V 4,00E+02 4,00E+02 4,00E+02 Factor i57 4,00E+02 4,00E+02 4,00E+02 1V 1V Factor i79
Process Parameters
Characteristics Gain Factor Threshold Voltage Symbol K'n K'p VT1n VT1p Specification Values 3,90E-05 A/V2 1,20E-05 A/V 1,54 V -1,8 V
Ratio I7 to I11
Step 5 Step 6 Step 7
R1 R2 S1 S2 S3 S12 S4 S5 Pdiss
0 NOK min 3 0 NOK min 3 0 NOK min 3 0 NOK min 3 83 OK S4 and S5 have to 83 OK be bigger as here 184,00 mW
= = = =
2,00 mA 1,20 2,40 mA 2,40 mA Ratio I3 to I4,5
Transistor ratios Transistor widths
Transistor widths
@ Length
Step 3
VSD5 VSD7 S4 S5 S14 S6 S7 S13
= = = = = = =
This current mirror sink, and the current mirror source are the basic modules of the folded cascode op amp.
9 Benjamin Lutgen
Schematic Description (2)
11 Benjamin Lutgen
Design Plan (1)
Design plan from Allen/Holberg - CMOS Analog Circuit Design [1] was used for determining the values of the transistor and resistors
12
Benjamin Lutgen
Design Plan (2) Transistor Groups
The transistors in the groups must always have the same ratio. • • • • • M1,2 M3 M4,5,6,7,13,14 M8,9,10,11 M12
Characteristics Open loop Gain Gain Bandwidth Phase Margin Settling Time Slew Rate Offset Input CMR Output Swing CMRR Power Dissipation Area Consumption Voltage Supply Load Capacitance Load Resistance VDD VSS Pdiss Vin(max) Vin(min) Vout(max) Vout(min) > SR GB PM > < Symbol > Specification Values 100 dB 1,00E+07 Hz 60 ° 1,00E-06 s 2,00E+08 V/s 5,00E-06 V 6V -6 V 8V -8 V 100 dB min min 10 V -10 V 1,00E-11 F = 1,00E+05 Ohm
400 NOK max 249 400 NOK max 249 400 NOK max 249 1,00 Ratio I5 to I7 400 NOK max 249 400 NOK max 249 400 NOK max 249
2 µm
Ratio Width
Trans.
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14
• Simulation Results
– Final Solution
• • • • • Final Schematic Measurement Setup Maximizing the Gain Simulation results Measuring the Characteristics
2
Benjamin Lutgen
0 0 0
0 µm 0 µm 0 µm
Step 4
VDS9 VDS11 S9 S8 S11 S10
400 800 µm 400 800 µm 400 800 µm 400 800 µm 123 246 µm 123 246 µm 123 246 µm 123 246 µm 0 0 µm 400 800 µm 400 800 µm
Another basic module: • The differential pair with a constant common current. • M3 works as current sink
This are the currents of the pair, during a DC-sweep of +Vin 10 Benjamin Lutgen
13
Benjamin Lutgen
Design Plan (3)
Design Plan
The calculations of the design plan were realized in an ExcelSheet, providing very fast recalculations.
Given Specifications
Schematic Description (3)
Schematic of the folded cascode op amp used in the project
Based on Schematic from [1] Allen/Holberg – CMOS Analog Circuit Design
8
Benjamin Lutgen
Schematic Description (1)
This is a special current mirror sink, with the following attributes: • • • • • High output resistance Small saturation voltage Low power dissipation Self biasing High swing
• Transistor groups
– LVS Log
4. Summary and Conclusion
– – – – Comparison Specification/Achieved Values Discussion Conclusion References
– First Approach – Second Approach
Step 8 Step 9 Step 10
5 Benjamin Lutgen
Motivation (2)
The high voltage CMOS Technology H35 provides a high voltage capability up to 50V. In the project, the symmetrical 20V variant with thick oxide is used („xMOS20HS“) Disadvantage: • Less K’n/K’p as in 3.3V technology
= = = = = = = = = = = = = = =
1,00 123 123 1,00 123 123 417,00 Ohm 417,00 Ohm
Ratio I7 to I9
= = = = = = = = = = = = =
1,23E+02 1,23E+02 Factor i711 1,23E+02 1,23E+02 4,17E+02 4,17E+02 1,28E-01 1,28E-01 3,33E-01 4,17E-01 82,6446281 82,6446281 1,84E-01
in µA/V²
20V
12 35
3.3V
50 110
Technology Technology
K‘p K‘n
6
Benjamin Lutgen
2. Schematic Design
7
Benjamin Lutgen
Practical Version of the Amplifier
Figure 6.5-7 from Allen/Holberg [1]
Biblioteka Baidu
1. Introduction
3
Benjamin Lutgen
Given Objectives
Objective of the project: • design of an folded cascode operational amplifier • using a new high voltage technology („H35“ 20 V) Meeting these specifications Î
3. Layout Design
– High Voltage Layouting – Final Layout
• Functional Groups
2. Schematic Design
– Practical Version of the Amplifier – Schematic Description – Design Plan
4
Benjamin Lutgen
Motivation (1)
The used folded cascode topology offers the following properties: • good common-mode range • self compensation • High gain • Relatively low power-dissipation • High output resistance The special challenge of this project was the transfer of this circuit to a high voltage CMOS technology
Benjamin LUTGEN Wintersemester 2008/2009 Supervisor: Prof. Dr.-Ing. Andreas König
Benjamin Lutgen
1
Overview
1. Intoduction
– Given Objectives – Motivation
S. Nr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Characteristics Open loop Gain Gain Bandwidth Phase margin Settling Time Slew Rate Offset Input CMR Output Swing CMRR Power Dissipation Area Consumption Voltage Supply Load Capacitance Load Resistance Specification values > 100 dB 10 MHz > 60 ° < 1 µs 200 V/µs 5 µV ±6V ±8V > 100 dB Minimum Minimum 20 V 10 pF 100 kΩ
Integrated Sensor Systems
Dept. of Electrical Engineering and Information Technology
Institute of
Design of an Folded Cascode Operational Amplifier in High Voltage CMOS Technology
Step 1 Step 2
I3 I4 I5
= = = = = = = = = = = = =
2,00E-03 A Factor k 2,40E-03 A 2,40E-03 A 1V 1V 4,00E+02 4,00E+02 4,00E+02 Factor i57 4,00E+02 4,00E+02 4,00E+02 1V 1V Factor i79
Process Parameters
Characteristics Gain Factor Threshold Voltage Symbol K'n K'p VT1n VT1p Specification Values 3,90E-05 A/V2 1,20E-05 A/V 1,54 V -1,8 V
Ratio I7 to I11
Step 5 Step 6 Step 7
R1 R2 S1 S2 S3 S12 S4 S5 Pdiss
0 NOK min 3 0 NOK min 3 0 NOK min 3 0 NOK min 3 83 OK S4 and S5 have to 83 OK be bigger as here 184,00 mW
= = = =
2,00 mA 1,20 2,40 mA 2,40 mA Ratio I3 to I4,5
Transistor ratios Transistor widths
Transistor widths
@ Length
Step 3
VSD5 VSD7 S4 S5 S14 S6 S7 S13
= = = = = = =
This current mirror sink, and the current mirror source are the basic modules of the folded cascode op amp.
9 Benjamin Lutgen
Schematic Description (2)
11 Benjamin Lutgen
Design Plan (1)
Design plan from Allen/Holberg - CMOS Analog Circuit Design [1] was used for determining the values of the transistor and resistors
12
Benjamin Lutgen
Design Plan (2) Transistor Groups
The transistors in the groups must always have the same ratio. • • • • • M1,2 M3 M4,5,6,7,13,14 M8,9,10,11 M12
Characteristics Open loop Gain Gain Bandwidth Phase Margin Settling Time Slew Rate Offset Input CMR Output Swing CMRR Power Dissipation Area Consumption Voltage Supply Load Capacitance Load Resistance VDD VSS Pdiss Vin(max) Vin(min) Vout(max) Vout(min) > SR GB PM > < Symbol > Specification Values 100 dB 1,00E+07 Hz 60 ° 1,00E-06 s 2,00E+08 V/s 5,00E-06 V 6V -6 V 8V -8 V 100 dB min min 10 V -10 V 1,00E-11 F = 1,00E+05 Ohm
400 NOK max 249 400 NOK max 249 400 NOK max 249 1,00 Ratio I5 to I7 400 NOK max 249 400 NOK max 249 400 NOK max 249
2 µm
Ratio Width
Trans.
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14
• Simulation Results
– Final Solution
• • • • • Final Schematic Measurement Setup Maximizing the Gain Simulation results Measuring the Characteristics
2
Benjamin Lutgen
0 0 0
0 µm 0 µm 0 µm
Step 4
VDS9 VDS11 S9 S8 S11 S10
400 800 µm 400 800 µm 400 800 µm 400 800 µm 123 246 µm 123 246 µm 123 246 µm 123 246 µm 0 0 µm 400 800 µm 400 800 µm
Another basic module: • The differential pair with a constant common current. • M3 works as current sink
This are the currents of the pair, during a DC-sweep of +Vin 10 Benjamin Lutgen
13
Benjamin Lutgen
Design Plan (3)
Design Plan
The calculations of the design plan were realized in an ExcelSheet, providing very fast recalculations.
Given Specifications
Schematic Description (3)
Schematic of the folded cascode op amp used in the project
Based on Schematic from [1] Allen/Holberg – CMOS Analog Circuit Design
8
Benjamin Lutgen
Schematic Description (1)
This is a special current mirror sink, with the following attributes: • • • • • High output resistance Small saturation voltage Low power dissipation Self biasing High swing
• Transistor groups
– LVS Log
4. Summary and Conclusion
– – – – Comparison Specification/Achieved Values Discussion Conclusion References
– First Approach – Second Approach