序列检测器的设计 实验报告.doc

WHEN s5=> IF DIN = '1' THENNST <= s6;ELSE NST<=s0;END IF;
WHEN s6=> IF DIN = '1' THENNST <= s7;ELSE NST<=s0;END IF;
WHEN s7=> IF DIN = '0' THENNST <= s8;ELSE NST<=s0;END IF;
END SM1;
ARCHITECTURE BEHAVIOR OF SM1 IS
TYPE type_fstate IS (st1,st2,st3,st4,st5,st6,st7,st8,st0);
SIGNAL fstate : type_fstate;
SIGNAL reg_fstate : type_fstate;
reg_fstate <= st5;
ELSE
reg_fstate <= st0;
END IF;
output1 <= '0';
WHEN st5 =>
EDA实验报告书
姓名xxx学号xxxxxxx实验时间
课题名称
序列检测器的设计
实验目的
1.用状态机实现序列检测器的设计
2.了解一般状态机的设计与应用
设计要求
1.采用VHDL语言设计序列检测器，具体要求如下：
（1）检测序列为“10101110”。该序列从左到右依次进入检测器，如果检测到完整序列，检测器输出为‘1’，反之输出为‘0’。
ENTITY SM1 IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
input1 : IN STD_LOGIC := '0';
input2 : IN STD_LOGIC := '0';
output1 : OUT STD_LOGIC
);
WHEN s2=> IF DIN = '1' THENNST <= s3;ELSE NST<=s0;END IF;
WHEN s3=> IF DIN = '0' THENNST <= s4;ELSE NST<=s0;END IF;
WHEN s4=> IF DIN = '1' THENNST <= s5;ELSE NST<=s0;END IF;
PROCESS (fstate,input1,input2)
BEGIN
output1 <= '0';
CASE fstate IS
WHEN st1 =>
IF (((input1 = '1') AND (input2 = '1'))) THEN
reg_fstate <= st2;
ELSE
reg_fstate <= st0;
SIGNAL ST,NST: states:=s0;
BEGIN
COM : PROCESS(ST,DIN) BEGIN
CASE ST IS
WHEN s0 => IF DIN = '1' THENNST <= s1;ELSE NST<=s0;END IF;
WHEN s1=> IF DIN = '0' THENNST <= s2;ELSE NST<=s0;END IF;
END IF;
output1 <= '0';
WHEN st2 =>
IF (((input1 = '1') AND (input2 = '1'))) THEN
reg_fstate <= st3;
ELSE
reg_fstate <= st0;
END IF;
output1 <= '0';
WHEN st3 =>
设计原理图及源程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITYAAIS
PORT ( CLK ,DIN,RST : IN STD_LOGIC;
SOUT: OUT STD_LOGIC;
ENDAA;
ARCHITECTURE behav OFAAIS
TYPE states IS (s0, s1, s2, s3,s4,s5,s6,s7,s8);
（2）利用QuatusII软件生成状态转移图。
（3）对该检测器进行仿真，得到仿真波形。
2.采用状态图编辑方法设计序列检测器，检测序列为“11010101”。具体要求为
（1）对电路进行仿真，得到仿真波形。
（2）将该电路图转化成VHDL语言形式。
设计思路
序列检测器可用于检测一组或多组由二进制码组成的脉冲序列信号，当序列检测器连续收到一组串行二进制码后，如果这组码与检测器中预先设置的码相同,则输出为1，否则输出为0.由于这种检测的关键在于正确码的收到必须是连续的，这就要求检测器必须记住前一次的正确码及正确序列，直到在连续的检测中所收到的每一位码都与预置数的对应码相同。在检测过程中，任何一位不相等都将回到初始状态重新检测。
BEGIN
PROCESS (clock,reset,reg_fstate)
BEGIN
IF (reset='1') THEN
fstate <= st1;
ELSIF (clock='1' AND clock'event) THEN
fstate <= reg_fstate;
END IF;
Байду номын сангаасEND PROCESS;
ELSIF ( CLK'EVENT AND CLK='1') THENST<=NST;
END IF;
END PROCESS REG;
SOUT<='1'WHEN ST=s8 ELSE'0';
ENDbehav;
仿真波形图
实验结果
LIBRARY ieee;
USE ieee.std_logic_1164.all;
IF (((input1 = '1') AND (input2 = '1'))) THEN
reg_fstate <= st4;
ELSE
reg_fstate <= st0;
END IF;
output1 <= '0';
WHEN st4 =>
IF (((input1 = '1') AND (input2 = '1'))) THEN
WHEN s8=> IF DIN = '0' THENNST <= s2;ELSE NST<=s0;END IF;
WHEN OTHERS =>NST <= st0;
END CASE ;
END PROCESS;
REG: PROCESS (CLK,RST)
BEGIN
IFRST='1'THENST<=s0;