3842典型正激电路
UC3842开关电源各功能电路详解
UC3842开关电源各功能电路详解一、开关电源的电路组成开关电源的主要电路是由输入电磁干扰滤波器（EMI）、整流滤波电路、功率变换电路、PWM控制器电路、输出整流滤波电路组成。
辅助电路有输入过欠压保护电路、输出过欠压保护电路、输出过流保护电路、输出短路保护电路等。
开关电源的电路组成方框图如下：二、输入电路的原理及常见电路1、AC 输入整流滤波电路原理：①防雷电路：当有雷击，产生高压经电网导入电源时，由MOV1、MOV2、MOV3：F1、F2、F3、FDG1组成的电路进行保护。
当加在压敏电阻两端的电压超过其工作电压时，其阻值降低，使高压能量消耗在压敏电阻上，若电流过大，F1、F2、F3 会烧毁保护后级电路。
②输入滤波电路：C1、L1、C2、C3组成的双π型滤波网络主要是对输入电源的电磁噪声及杂波信号进行抑制，防止对电源干扰，同时也防止电源本身产生的高频杂波对电网干扰。
当电源开启瞬间，要对C5充电，由于瞬间电流大，加RT1（热敏电阻）就能有效的防止浪涌电流。
因瞬时能量全消耗在RT1电阻上，一定时间后温度升高后RT1阻值减小（RT1是负温系数元件），这时它消耗的能量非常小，后级电路可正常工作。
③整流滤波电路：交流电压经BRG1整流后，经C5滤波后得到较为纯净的直流电压。
若C5容量变小，输出的交流纹波将增大。
2、DC 输入滤波电路原理：①输入滤波电路：C1、L1、C2组成的双π型滤波网络主要是对输入电源的电磁噪声及杂波信号进行抑制，防止对电源干扰，同时也防止电源本身产生的高频杂波对电网干扰。
C3、C4 为安规电容，L2、L3为差模电感。
② R1、R2、R3、Z1、C6、Q1、Z2、R4、R5、Q2、RT1、C7组成抗浪涌电路。
在起机的瞬间，由于C6的存在Q2不导通，电流经RT1构成回路。
当C6上的电压充至Z1的稳压值时Q2导通。
如果C8漏电或后级电路短路现象，在起机的瞬间电流在RT1上产生的压降增大，Q1导通使Q2没有栅极电压不导通，RT1将会在很短的时间烧毁，以保护后级电路。
UC3842好坏的判断鉴别方法与应用电路图
•显示器的UC3842应用电路图UC3842好坏的判断鉴别方法在国内电子设备当中，电源PWM控制电路最常用的集成电路型号就是UC3842（或UTC3842）。
也就是因为常常遇到，对它也有一些之得，下面简单介绍一下UC3842好坏的判断方法：在更换完周边损坏的元件后，先不装开关管(MOSFET)，加电测量UC3842的7脚电压，若电压在10-17V间波动，其余各脚也分别有波动的电压，则说明电路已起振，UC3842基本正常;若７脚电压低，其余接脚无电压或不波动，则UC3842已损坏。
在UC3842的7、5脚间外加+17V左右的直流电压，若测8脚有+5V 电压，1、2、4、6脚也有不同的电压，则UC3842基本正常，工作电流小，自身不易损坏．它损坏的最常见原因是电源开关管(MOSFET)短路后，高电压从G极加到其6脚而致使其烧毁．而有些机型中省去了G极接地的保护二极体，则电源开关管(MOSFET)损坏时，UC3842和G极外接的限流电阻必坏．此时直接更换即可。
需要注意的是，电源开关管源极（S极）通常接１个小阻值、大功率的电阻作为过流保护检测电阻．此电阻的阻值一般在0.2-0.6之间，大于此值会出现带不起负载的现象（就是次极电压偏低）。
由于UC3842（KA3842）的工作电压和输出功率均与UC3843（KA3843）相差甚远，3842系列和3843系列在启动电压和关闭电压方面也存在着较大的区别.前者的启动电压为16V，关闭电压为10V;后者的启动电压为8.5V，关闭电压为7.6V。
这两个系列的IC不能直接代换。
如确有必要用后者代换前者时，要对电路加以改造方可。
因此，这一点在维修工作中必须要注意uc3842开关电源电路图1、UC3842的内部结构和特点UC3842是美国Unitrode公司生产的一种高性能单端输出式电流控制型脉宽调制器芯片。
UC3842为8脚双列直插式封装，其内部原理框图如图1所示。
主要由5.0V基准电压源、用来精确地控制占空比调定的振荡器、降压器、电流测定比较器、PWM锁存器、高增益E/A误差放大器和适用于驱动功率MOSFET的大电流推挽输出电路等构成。
一文解析UC3842组成的开关电源电路
一文解析UC3842组成的开关电源电路
本文主要讲了UC3842组成的开关电源电路、电路的调试以及几种3842充电器电路图，下面随小编来看看吧。
UC3842组成的开关电源电路
图2是由UC3842构成的开关电源电路，220V市电由C1、L1滤除电磁干扰，负温度系数的热敏电阻Rt1限流，再经VC整流、C2滤波，电阻R1、电位器RP1降压后加到UC3842的供电端（⑦脚），为UC3842提供启动电压，电路启动后变压器的付绕组③④的整流滤波电压一方面为UC3842提供正常工作电压，另一方面经R3、R4分压加到误差放大器的反相输入端②脚，为UC3842提供负反馈电压，其规律是此脚电压越高驱动脉冲的占空比越小，以此稳定输出电压。
④脚和⑧脚外接的R6、C8决定了振荡频率，其振荡频率的最大值可达500KHz。
R5、C6用于改善增益和频率特性。
⑥脚输出的方波信号经R7、R8分压后驱动MOSFEF功率管，变压器原边绕组①②的能量传递到付边各绕组，经整流滤波后输出各数值不同的直流电压供负载使用。
电阻R10用于电流检测，经R9、C9滤滤后送入UC3842的③脚形成电流反馈环。
所以由UC3842构成的电源是双闭环控制系统，电压稳定度非常高，当UC3842的③脚电压高于1V时振荡器停振，保护功率管不至于过流而损坏。
图2 UC3842构成的开关电源
电路的调试
此电路的调试需要注意：一是调节电位器RP1使电路起振，起振电流在1mA左右；二是起振后变压器③④绕组提供的直流电压应能使电路正常工。
3842典型应用电路全集
UC3842典型应用电路电路中的芯片有：UC3842 采用固定工作频率脉冲宽度可控调制方式，共有8 个引脚，各脚功能如下：①脚是误差放大器的输出端，外接阻容元件用于改善误差放大器的增益和频率特性；②脚是反馈电压输入端，此脚电压与误差放大器同相端的2.5V 基准电压进行比较，产生误差电压，从而控制脉冲宽度；③脚为电流检测输入端，当检测电压超过1V时缩小脉冲宽度使电源处于间歇工作状态；④脚为定时端，内部振荡器的工作频率由外接的阻容时间常数决定，f=1.8/(RT×CT)；⑤脚为公共地端；⑥脚为推挽输出端，内部为图腾柱式，上升、下降时间仅为50ns 驱动能力为±1A ；⑦脚是直流电源供电端，具有欠、过压锁定功能，芯片功耗为15mW；⑧脚为5V 基准电压输出端，有50mA 的负载能力。
电流控制型脉宽调制器UC3842工作原理及应用UC3842是美国Unitrode公司(该公司现已被TI公司收购)生产的一种高性能单端输出式电流控制型脉宽调制器芯片，可直接驱动双极型晶体管、MOSFEF 和IGBT 等功率型半导体器件，具有管脚数量少、外围电路简单、安装调试简便、性能优良等诸多优点，广泛应用于计算机、显示器等系统电路中作开关电源驱动器件。
1 UC3842 内部工作原理简介图1 示出了UC3842 内部框图和引脚图，UC3842 采用固定工作频率脉冲宽度可控调制方式，共有8 个引脚，各脚功能如下：①脚是误差放大器的输出端，外接阻容元件用于改善误差放大器的增益和频率特性；②脚是反馈电压输入端，此脚电压与误差放大器同相端的2.5V 基准电压进行比较，产生误差电压，从而控制脉冲宽度；③脚为电流检测输入端，当检测电压超过1V时缩小脉冲宽度使电源处于间歇工作状态；④脚为定时端，内部振荡器的工作频率由外接的阻容时间常数决定，f=1.8/(R T×C T)；⑤脚为公共地端；⑥脚为推挽输出端，内部为图腾柱式，上升、下降时间仅为50ns 驱动能力为±1A ；⑦脚是直流电源供电端，具有欠、过压锁定功能，芯片功耗为15mW；⑧脚为5V 基准电压输出端，有50mA 的负载能力。
UC3842典型应用电路
UC3842典型应用电路电路中的芯片有：UC3842 采用固定工作频率脉冲宽度可控调制方式，共有8 个引脚，各脚功能如下：①脚是误差放大器的输出端，外接阻容元件用于改善误差放大器的增益和频率特性；②脚是反馈电压输入端，此脚电压与误差放大器同相端的2.5V 基准电压进行比较，产生误差电压，从而控制脉冲宽度；③脚为电流检测输入端，当检测电压超过1V时缩小脉冲宽度使电源处于间歇工作状态；④脚为定时端，内部振荡器的工作频率由外接的阻容时间常数决定，f=1.8/(RT×CT)；⑤脚为公共地端；⑥脚为推挽输出端，内部为图腾柱式，上升、下降时间仅为50ns 驱动能力为±1A ；⑦脚是直流电源供电端，具有欠、过压锁定功能，芯片功耗为15mW；⑧脚为5V 基准电压输出端，有50mA 的负载能力。
电流控制型脉宽调制器UC3842工作原理及应用UC3842是美国Unitrode公司(该公司现已被TI公司收购)生产的一种高性能单端输出式电流控制型脉宽调制器芯片，可直接驱动双极型晶体管、MOSFEF 和IGBT 等功率型半导体器件，具有管脚数量少、外围电路简单、安装调试简便、性能优良等诸多优点，广泛应用于计算机、显示器等系统电路中作开关电源驱动器件。
1 UC3842 内部工作原理简介图1 示出了UC3842 内部框图和引脚图，UC3842 采用固定工作频率脉冲宽度可控调制方式，共有8 个引脚，各脚功能如下：①脚是误差放大器的输出端，外接阻容元件用于改善误差放大器的增益和频率特性；②脚是反馈电压输入端，此脚电压与误差放大器同相端的2.5V 基准电压进行比较，产生误差电压，从而控制脉冲宽度；③脚为电流检测输入端，当检测电压超过1V时缩小脉冲宽度使电源处于间歇工作状态；④脚为定时端，内部振荡器的工作频率由外接的阻容时间常数决定，f=1.8/(R T×C T)；⑤脚为公共地端；⑥脚为推挽输出端，内部为图腾柱式，上升、下降时间仅为50ns 驱动能力为±1A ；⑦脚是直流电源供电端，具有欠、过压锁定功能，芯片功耗为15mW；⑧脚为5V 基准电压输出端，有50mA 的负载能力。
UC3842电源
用UC3842设计开关电源的几个技巧用UC3842做的开关电源的典型电路见图1。
过载和短路保护，一般是通过在开关管的源极串一个电阻（R4），把电流信号送到3842的第3脚来实现保护。
当电源过载时，3842保护动作，使占空比减小，输出电压降低，3842的供电电压Vaux也跟着降低，当低到3842不能工作时，整个电路关闭，然后靠R1、R2开始下一次启动过程。
这被称为“打嗝”式（hiccup）保护。
在这种保护状态下，电源只工作几个开关周期，然后进入很长时间（几百ms到几s）的启动过程，平均功率很低，即使长时间输出短路也不会导致电源的损坏。
由于漏感等原因，有的开关电源在每个开关周期有很大的开关尖峰，即使在占空比很小时，辅助电压Vaux也不能降到足够低，所以一般在辅助电源的整流二极管上串一个电阻（R3），它和C1形成RC滤波，滤掉开通瞬间的尖峰。
仔细调整这个电阻的数值，一般都可以达到满意的保护。
使用这个电路，必须注意选取比较低的辅助电压Vaux，对3842一般为13～15V，使电路容易保护。
图2、3、4是常见的电路。
图2采取拉低第1脚的方法关闭电源。
图3采用断开振荡回路的方法。
图4采取抬高第2脚，进而使第1脚降低的方法。
在这3个电路里R3电阻即使不要，仍能很好保护。
注意电路中C4的作用，电源正常启动，光耦是不通的，因此靠C4来使保护电路延迟一段时间动作。
在过载或短路保护时，它也起延时保护的左右。
在灯泡、马达等启动电流大的场合，C4的取值也要大一点。
图1是使用最广泛的电路，然而它的保护电路仍有几个问题：1. 在批量生产时，由于元器件的差异，总会有一些电源不能很好保护，这时需要个别调整R3的数值，给生产造成麻烦；2. 在输出电压较低时，如3.3V、5V，由于输出电流大，过载时输出电压下降不大，也很难调整R3到一个理想的数值；3. 在正激应用时，辅助电压Vaux虽然也跟随输出变化，但跟输入电压HV的关系更大，也很难调整R3到一个理想的数值。
UC3842开关电源各功能电路详解
UC3842开关电源各功能电路详解一、开关电源的电路组成开关电源的主要电路是由输入电磁干扰滤波器（EMI）、整流滤波电路、功率变换电路、PWM控制器电路、输出整流滤波电路组成。
辅助电路有输入过欠压保护电路、输出过欠压保护电路、输出过流保护电路、输出短路保护电路等。
开关电源的电路组成方框图如下：二、输入电路的原理及常见电路1、AC 输入整流滤波电路原理：①防雷电路：当有雷击，产生高压经电网导入电源时，由MOV1、MOV2、MOV3：F1、F2、F3、FDG1组成的电路进行保护。
当加在压敏电阻两端的电压超过其工作电压时，其阻值降低，使高压能量消耗在压敏电阻上，若电流过大，F1、F2、F3 会烧毁保护后级电路。
②输入滤波电路：C1、L1、C2、C3组成的双π型滤波网络主要是对输入电源的电磁噪声及杂波信号进行抑制，防止对电源干扰，同时也防止电源本身产生的高频杂波对电网干扰。
当电源开启瞬间，要对C5充电，由于瞬间电流大，加RT1（热敏电阻）就能有效的防止浪涌电流。
因瞬时能量全消耗在RT1电阻上，一定时间后温度升高后RT1阻值减小（RT1是负温系数元件），这时它消耗的能量非常小，后级电路可正常工作。
③整流滤波电路：交流电压经BRG1整流后，经C5滤波后得到较为纯净的直流电压。
若C5容量变小，输出的交流纹波将增大。
2、DC 输入滤波电路原理：①输入滤波电路：C1、L1、C2组成的双π型滤波网络主要是对输入电源的电磁噪声及杂波信号进行抑制，防止对电源干扰，同时也防止电源本身产生的高频杂波对电网干扰。
C3、C4 为安规电容，L2、L3为差模电感。
② R1、R2、R3、Z1、C6、Q1、Z2、R4、R5、Q2、RT1、C7组成抗浪涌电路。
在起机的瞬间，由于C6的存在Q2不导通，电流经RT1构成回路。
当C6上的电压充至Z1的稳压值时Q2导通。
如果C8漏电或后级电路短路现象，在起机的瞬间电流在RT1上产生的压降增大，Q1导通使Q2没有栅极电压不导通，RT1将会在很短的时间烧毁，以保护后级电路。
六款uc3842开关电源电路图分享
六款uc3842开关电源电路图分享描述uc3842开关电源电路图分享（一）用UC3842做的开关电源的典型电路见图1。
过载和短路保护，一般是通过在开关管的源极串一个电阻（R4），把电流信号送到3842的第3脚来实现保护。
当电源过载时，3842保护动作，使占空比减小，输出电压降低，3842的供电电压Vaux也跟着降低，当低到3842不能工作时，整个电路关闭，然后靠R1、R2开始下一次启动过程。
这被称为“打嗝”式（hiccup）保护。
在这种保护状态下，电源只工作几个开关周期，然后进入很长时间（几百ms到几s）的启动过程，平均功率很低，即使长时间输出短路也不会导致电源的损坏。
由于漏感等原因，有的开关电源在每个开关周期有很大的开关尖峰，即使在占空比很小时，辅助电压Vaux也不能降到足够低，所以一般在辅助电源的整流二极管上串一个电阻（R3），它和C1形成RC滤波，滤掉开通瞬间的尖峰。
仔细调整这个电阻的数值，一般都可以达到满意的保护。
使用这个电路，必须注意选取比较低的辅助电压Vaux，对3842一般为13～15V，使电路容易保护。
图2、3、4是常见的电路。
图2采取拉低第1脚的方法关闭电源。
图3采用断开振荡回路的方法。
图4采取抬高第2脚，进而使第1脚降低的方法。
在这3个电路里R3电阻即使不要，仍能很好保护。
注意电路中C4的作用，电源正常启动，光耦是不通的，因此靠C4来使保护电路延迟一段时间动作。
在过载或短路保护时，它也起延时保护的左右。
在灯泡、马达等启动电流大的场合，C4的取值也要大一点。
图1是使用最广泛的电路，然而它的保护电路仍有几个问题：1. 在批量生产时，由于元器件的差异，总会有一些电源不能很好保护，这时需要个别调整R3的数值，给生产造成麻烦；2. 在输出电压较低时，如3.3V、5V，由于输出电流大，过载时输出电压下降不大，也很难调整R3到一个理想的数值；3. 在正激应用时，辅助电压Vaux虽然也跟随输出变化，但跟输入电压HV的关系更大，也很难调整R3到一个理想的数值。
uc3842开关电源电路图
uc3842开关电源电路图1、UC3842的内部结构和特点UC3842是美国Unitrode公司⽣产的⼀种⾼性能单端输出式电流控制型脉宽调制器芯⽚。
UC3842为8脚双列直插式封装，其内部原理框图如图1所⽰。
主要由5.0V基准电压源、⽤来精确地控制占空⽐调定的振荡器、降压器、电流测定⽐较器、PWM锁存器、⾼增益E/A误差放⼤器和适⽤于驱动功率MOSFET的⼤电流推挽输出电路等构成。
端1为COMP端；端2为反馈端；端3为电流测定端；端4接Rt、Ct确定锯齿波频率；端5接地；端6为推挽输出端，有拉、灌电流的能⼒；端7为集成块⼯作电源电压端，可以⼯作在8～40V；端8为内部供外⽤的基准电压5V，带载能⼒50mA。
2、电路结构与⼯作原理图2所⽰为笔者在实际⼯作中使⽤的电路图。
输⼊电压为24V直流电。
三路直流输出，分别为+5V/4A，+12V/0.3A和-12V/0.3A。
所有的⼆极管都采⽤快速反应⼆极管，核⼼PWM器件采⽤UC3842。
开关管采⽤快速⼤功率场效应管。
2.1 启动过程⾸先由电源通过启动电阻R 1提供电流给电容C2充电，当C2电压达到UC3842的启动电压门槛值16V时，UC3842开始⼯作并提供驱动脉冲，由6端输出推动开关管⼯作，输出信号为⾼低电压脉冲。
⾼电压脉冲期间，场效应管导通，电流通过变压器原边，同时把能量储存在变压器中。
根据同名端标识情况，此时变压器各路副边没有能量输出。
当6脚输出的⾼电平脉冲结束时，场效应管截⽌，根据楞次定律，变压器原边为维持电流不变，产⽣下正上负的感⽣电动势，此时副边各路⼆极管导通，向外提供能量。
同时反馈线圈向UC3842供电。
UC3842内部设有⽋压锁定电路，其开启和关闭阈值分别为16V和10V，如图3所⽰。
在开启之前，UC3842消耗的电流在1mA以内。
电源电压接通之后，当7端电压升⾄16V时UC3842开始⼯作，启动正常⼯作后，它的消耗电流约为15mA。
因为UC3842的启动电流在1mA以内，设计时参照这些参数选取R1，所以在R1上的功耗很⼩。
UC3842开关电源电路图
UC3842开关电源电路图第一篇：UC3842开关电源电路图1、UC3842的内部结构和特点UC3842是美国Unitrode公司生产的一种高性能单端输出式电流控制型脉宽调制器芯片。
UC3842为8脚双列直插式封装，其内部原理框图如图1所示。
主要由5.0V基准电压源、用来精确地控制占空比调定的振荡器、降压器、电流测定比较器、PWM锁存器、高增益E/A误差放大器和适用于驱动功率MOSFET的大电流推挽输出电路等构成。
端1为COMP 端；端2为反馈端；端3为电流测定端；端4接Rt、Ct确定锯齿波频率；端5接地；端6为推挽输出端，有拉、灌电流的能力；端7为集成块工作电源电压端，可以工作在8～40V；端8为内部供外用的基准电压5V，带载能力50mA。
2、电路结构与工作原理图2所示为笔者在实际工作中使用的电路图。
输入电压为24V直流电。
三路直流输出，分别为+5V/4A，+12V/0.3A和-12V/0.3A。
所有的二极管都采用快速反应二极管，核心PWM器件采用UC3842。
开关管采用快速大功率场效应管。
2.1 启动过程首先由电源通过启动电阻R 1提供电流给电容C2充电，当C2电压达到UC3842的启动电压门槛值16V时，UC3842开始工作并提供驱动脉冲，由6端输出推动开关管工作，输出信号为高低电压脉冲。
高电压脉冲期间，场效应管导通，电流通过变压器原边，同时把能量储存在变压器中。
根据同名端标识情况，此时变压器各路副边没有能量输出。
当6脚输出的高电平脉冲结束时，场效应管截止，根据楞次定律，变压器原边为维持电流不变，产生下正上负的感生电动势，此时副边各路二极管导通，向外提供能量。
同时反馈线圈向UC3842供电。
UC3842内部设有欠压锁定电路，其开启和关闭阈值分别为16V 和10V，如图3所示。
在开启之前，UC3842消耗的电流在1mA以内。
电源电压接通之后，当7端电压升至16V时UC3842开始工作，启动正常工作后，它的消耗电流约为15mA。
UC3842设计开关电源的几个技巧
用UC3842设计开关电源的几个技巧用UC3842做的开关电源的典型电路见图1。
过载和短路保护，一般是通过在开关管的源极串一个电阻（R4），把电流信号送到3842的第3脚来实现保护。
当电源过载时，3842保护动作，使占空比减小，输出电压降低，3842的供电电压Vaux也跟着降低，当低到3842不能工作时，整个电路关闭，然后靠R1、R2开始下一次启动过程。
这被称为“打嗝”式（hiccup）保护。
在这种保护状态下，电源只工作几个开关周期，然后进入很长时间（几百ms到几s）的启动过程，平均功率很低，即使长时间输出短路也不会导致电源的损坏。
由于漏感等原因，有的开关电源在每个开关周期有很大的开关尖峰，即使在占空比很小时，辅助电压Vaux也不能降到足够低，所以一般在辅助电源的整流二极管上串一个电阻（R3），它和C1形成RC滤波，滤掉开通瞬间的尖峰。
仔细调整这个电阻的数值，一般都可以达到满意的保护。
使用这个电路，必须注意选取比较低的辅助电压Vaux，对3842一般为13～15V，使电路容易保护。
图2、3、4是常见的电路。
图2采取拉低第1脚的方法关闭电源。
图3采用断开振荡回路的方法。
图4采取抬高第2脚，进而使第1脚降低的方法。
在这3个电路里R3电阻即使不要，仍能很好保护。
注意电路中C4的作用，电源正常启动，光耦是不通的，因此靠C4来使保护电路延迟一段时间动作。
在过载或短路保护时，它也起延时保护的左右。
在灯泡、马达等启动电流大的场合，C4的取值也要大一点。
图1是使用最广泛的电路，然而它的保护电路仍有几个问题：1.在批量生产时，由于元器件的差异，总会有一些电源不能很好保护，这时需要个别调整R3的数值，给生产造成麻烦；2. 在输出电压较低时，如3.3V、5V，由于输出电流大，过载时输出电压下降不大，也很难调整R3到一个理想的数值；3. 在正激应用时，辅助电压Vaux虽然也跟随输出变化，但跟输入电压HV的关系更大，也很难调整R3到一个理想的数值。
基于UC3842的单端正激开关电源
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3842充电器电路图大全
3842充电器电路图大全3842充电器电路图（一） UC3842组成的充电器电路图1中C1、V1～V4、C2组成滤波整流电路，变压器T为高频变压器，V5、R2、C11组成功率开关管V7的保护电路，NF为供给IC 电源的绕组。
单端输出IC为UC3842，其8脚输出5V基准电压，2脚为反相输入，1脚为放大器输出，4脚为振荡电容C9、电阻R7输入端，5脚为接地端，3脚为过流保护端，6脚为调宽单脉冲输出端，7脚为电源输入端。
R6、C7组成负反馈，IC启动瞬间由R1供给启动电压，电路启动后由NF产生电势经V6、C4、C5整流滤波后供给IC工作电压。
R12为过流保护取样电阻，V8、C3组成反激整流滤波输出电路。
R13为内负载，V9～V12及R14～R19组成发光管显示电路。
图1中V5、V6选用FR107，V8选用FR154，V7选用K792。
842充电器电路图（二） uc3842lm324充电器电路电路利用开关电源充电，以减小充电器的重量和体积。
本充电器电路的正常充电电流为250MA，涓流充电电流为200MA。
3842充电器电路图（三）基于KA3842的电动车充电器电路图常用电动车充电器根据电路结构，有一款是以KA3842驱动场效应管的单管开关电源，配合LM358双运放来实现三阶段充电方式。
原理如下：220v交流电经T0双向滤波抑制干扰，D1整流为脉动直流，再经C11滤波形成稳定的300V左右的直流电。
U1为KA3842脉宽调制集成电路。
其5脚为电源负极，7脚为电源正极，6脚为脉冲输出直接驱动场效应管Q1（K1358）3脚为最大电流限制，调整R25（2.5欧姆）的阻值可以调整充电器的最大电流。
2脚为电压反馈，可以调节充电器的输出电压。
4脚外接振荡电阻R1，和振荡电容C1.T1为高频脉冲变压器，其作用有三个。
第一是把高压脉冲将压为低压脉冲。
第二是起到隔离高压的作用，以防触电。
第三是为KA3842提供工作电源。
开关电源各功能电路详解
UC3842开关电源各功能电路详解一、开关电源的电路组成开关电源的主要电路是由输入电磁干扰滤波器（EMI）、整流滤波电路、功率变换电路、PWM 控制器电路、输出整流滤波电路组成。
辅助电路有输入过欠压保护电路、输出过欠压保护电路、输出过流保护电路、输出短路保护电路等。
开关电源的电路组成方框图如下：二、输入电路的原理及常见电路1、AC 输入整流滤波电路原理：① 防雷电路：当有雷击，产生高压经电网导入电源时，由MOV1、MOV2、MOV3：F1、F2、F3、FDG1 组成的电路进行保护。
当加在压敏电阻两端的电压超过其工作电压时，其阻值降低，使高压能量消耗在压敏电阻上，若电流过大，F1、F2、F3 会烧毁保护后级电路。
② 输入滤波电路：C1、L1、C2、C3组成的双π型滤波网络主要是对输入电源的电磁噪声及杂波信号进行抑制，防止对电源干扰，同时也防止电源本身产生的高频杂波对电网干扰。
当电源开启瞬间，要对 C5充电，由于瞬间电流大，加RT1（热敏电阻）就能有效的防止浪涌电流。
因瞬时能量全消耗在RT1电阻上，一定时间后温度升高后RT1阻值减小（RT1是负温系数元件），这时它消耗的能量非常小，后级电路可正常工作。
③ 整流滤波电路：交流电压经BRG1整流后，经C5滤波后得到较为纯净的直流电压。
若C5容量变小，输出的交流纹波将增大。
2、 DC 输入滤波电路原理：① 输入滤波电路：C1、L1、C2组成的双π型滤波网络主要是对输入电源的电磁噪声及杂波信号进行抑制，防止对电源干扰，同时也防止电源本身产生的高频杂波对电网干扰。
C3、C4 为安规电容，L2、L3为差模电感。
② R1、R2、R3、Z1、C6、Q1、Z2、R4、R5、Q2、RT1、C7组成抗浪涌电路。
在起机的瞬间，由于 C6的存在Q2不导通，电流经RT1构成回路。
当C6上的电压充至Z1的稳压值时Q2导通。
如果C8漏电或后级电路短路现象，在起机的瞬间电流在RT1上产生的压降增大，Q1导通使 Q2没有栅极电压不导通，RT1将会在很短的时间烧毁，以保护后级电路。
3842典型正激电路
CS3842AAN/DSingle CS3842A Provides Control for 500 W/200 kHz Current-Mode Power SupplyINTRODUCTIONWith the introduction of the CS3842A PWM IC,current–mode is possible for power supplies of a wide range of output power levels. It’s low cost makes the CS3842A particularly attractive in low power DC to DC converter applications. But because this IC can provide a high output current (1.0 A peak, 200 mA average), it is also capable of driving large power MOSFETS which can switch high amounts of power.Current–Mode vs. Voltage–Mode ControlIn a switching power supply, the output voltage is controlled by varying the conduction duty cycle of the power switch(es). Traditionally duty cycle control was done by comparing the amplified difference of the output voltage feedback signal and a fixed stable reference to the sawtooth waveform derived from an oscillator. This constitutes the basic voltage mode control (VMC) scheme.VMC was later improved by allowing a sample of the input voltage to vary the slope of the sawtooth waveform.This feed forward scheme provided excellent line regulation in most of the popular circuit topologies. However, the task of compensating voltage mode converters has not been simple due to its resonant peak and 40 dB/decade roll off associated with the output LC filter.In current mode control, (CMC) the control signal represents the peak inductor current and forms a second loop in the circuit (Figure 1). The advantages of current mode control are:•Instantaneous correction to line voltage variations; the inductor current slope varies with input voltage.•Stable power supply designs; the pole associated with the inductor is eliminated.•Equal current sharing in paralleled power stages when both share the same control signal and have the same current sense circuits.•No current limit amplifier is needed.•Flux balancing exists in push–pull circuits.Disadvantages:•Slope compensation is required for peak versus average inductor current error and for compensating instabilities associated with load disturbances in single ended topologies operating at greater than 50% duty cycle.Premature shutdown due to the turn on current spike caused by the reverse diode recovery of the output free wheeling diode.•Runaway conditions when half bridge topology is operated in current–mode control.Figure 1. Basic Circuit Using Current–Mode ControlV REFV OUTAPPLICATION NOTEFigure 2. Peak Current Detection is Used to Keep I AVGConstant for Varying Duty Cycles(a) Peak vs. Average Current Error(b) I AVG. is Constant for Varying DutyCycle, (Constant Load)If the current sense signal is properly filtered, noise induced problems including the turn on spike can be avoided. By deliberately adding more slope to the current sense signal, or subtracting it from the control voltage signal, the instability due to greater than 50% duty cycle operation can be overcome. Slope compensation aids in reducing uncertainty at the point of trigger in the PWM comparator when shallow current ramps are involved. It also helps the peak current appear higher than the turn–on spike.This eliminates premature shutdown.Figure 2a illustrates how peak current detection in current mode control produces a change in the average current by relying on the feed forward property of current mode to compensate for line voltage variations. If a slope equal to one–half the negative going inductor current slope is added to the current sense signal, or subtracted from the control signal, this error is corrected (Figure 2b).Current–Mode Control With the CS3842AFigure 3 shows a CS3842A block diagram containing the basic functions necessary to implement current–mode control. This device will operate from 10 V to 30 V from a low impedance voltage source or can be current fed if the current is limited to less than 30 mA. The CS3842A is designed to be driven from the rectified line voltage for start–up, requiring a current of only 0.5 mA(typ). An auxiliary supply voltage is needed when the device is used as in Figure 4. When operating with a supply voltage between 10 V and 16 V , a bootstrap circuit provides more than 16 V to overcome the device’s under–voltage lockout circuit turn–ON threshold. The wide hysteresis band (6.0 V)accommodates variations in the input voltage.Figure 3. CS3842A/3843A Block DiagramV OUTOSCV FB COMP SENSEGNDV REFV CCFigure 4. Common Off–Line Operation of CS3842AThe Oscillator SectionAfter V REF is stabilized, the timing capacitor, C T charges through R T to about 2.7 V , and then discharges to about 1.1V for every cycle of the oscillator. Since C T must begin charging from 0 volts instead of 1.1 V on the first cycle, the ON time is longer than in subsequent cycles.To avoid this ON time discrepancy the CS3842A latches the output in its low state until the end of the first cycle (Figure 5). The internal current source which discharges C T is trimmed to provide an accurate maximum duty cycle clamp without relying on external timers to synchronize the oscillator. The timing components can be selected, to set the frequency of the oscillator, and the maximum duty cycle.Figure 5. The First Pulse is Blanked Out Because itExceeds the Maximum Duty Cycle Clamp2.7 V1.1 V 0 VTypical waveforms illustrating CS3842A operation are shown in Figure 6. During the discharge time of the OSC waveform, the oscillator internally disables the output to limit the maximum duty cycle. When V IN increases, the slope of the switch current (the combination of the inductor current slope referred to the primary, the transformer magnetizing current, and any slope compensation) increases such to provide instant duty cycle correction without using the error amplifier’s dynamic range. If a step increase in load current occurs, the error amplifier shifts the control line to a higher level to allow the inductor to conduct more current.Since the rate of change of the current on the inductor is fixed by the voltage applied, (if the peak current does not intersect the control line) the duty cycle clamp will time out first and prevent the conduction time from exceeding the maximum ON time. Since the output voltage drops due to the load increase, the down–slope of the inductor current decreases,allowing the current pulse to quickly converge to a steady state value.Figure 6. CS3842A Typical WaveformsV REFV OSCReset OSC Output E/A CurrentSwitch OutputCS3842A I OUTV INOUTApplying the CS3842AA 500 W, 200 kHz power supply was designed by combining the high frequency operation of the oscillator with the high current drive capability of the CS3842A. A two transistor forward converter was chosen. The advantages of this topology are:•the voltage rating for the MOSFETs is reduced to one–half that of a single transistor forward converter (450 V compared to 900 V);•snubber networks are required only for load line shaping of the MOSFETs;•the energy stored in the leakage inductance is effectively returned to the input via clamp diodes;•the ripple current rating on the output filter capacitor is less than in flyback converters.One notable disadvantage of this topology is the limit on the maximum duty cycle which results in less efficient transformer utilization. The complete schematic of the power supply is shown in Figure 7.Input SectionTo determine the required capacitance, the input power should be approximately known and this can be done by making an estimate of the power losses expected in the circuit.Expected LossesSchottky Diodes: (80 A)(.55 V)44 W. . . . . . . . . . . . . . . . Power MOSFETs: Assume 5% of P OUT25 W. . . . . . . . . Diodes on a 12 V Output. (two diodes conductat any one time: (0.8 V)(4.0 A)(2) 6.0 W. . . . . . . . . . Power Transformer:20 W. . . . . . . . . . . . . . . . . . . . . . . . . Inductors: (Estimate)10 W. . . . . . . . . . . . . . . . . . . . . . . . Snubbers, Control Ckt, etc:20 W. . . . . . . . . . . . . . . . . . . Total Estimated Losses125 W. . . . . . . . . . . . . . . . . . . . . Expected Input Power625 W. . . . . . . . . . . . . . . . . . . . . . Since the AC input voltage is rectified, the capacitors must deliver energy at twice the line frequency.E IN+P IN2f+625(2)(60)+5.21JOULES(1)The minimum peak voltage expected is1872Ǹ*2)262VThe 2.0 V accounts for 2 diode drops on the input bridge. If we assume initially the capacitor valley voltage to be 200 V then fromE IN+12C eq(V pk2*V min2)(2)C eq+364m For C = 728 µF because the two capacitors are in series. Anticipating tolerances and going through some iterations to find a commercially available capacitor that would meet the ripple current requirements, two Sprague 1300 µf/200 V 36DX series capacitors were selected.The valley voltage is recalculated using Eqn. (2) and found to be 229 V. The capacitor conduction time is then determined.tc+cos–1(V minńV pk)2p f+1.35ms(3)The instantaneous maximum capacitor charging current isI chg+C eq(V pk*V min)ńtc+15.9A+I pk(4)Assuming a rectangular shaped charging current pulse,the RMS value is:I chg+I pk2ft cǸ+6.4A(5)The DC current isI dc+I pk(2ft c)+2.58A(6)Since the DC component of the current is zero in thecapacitors, the RMS value of the charging current becomesI rms+I chg2*I dc2Ǹ+5.86A(7)The discharge current is determined as followsI dis+I inǒT2*t cǓ2T+P IN V pkǒT2*t cǓ2T+P INV pkǒ12f*t cǓ2f+P INV pk(1*2t c f)(8)Substituting in to equation 8, we get I dis = 2.0 A. The totalRMS capacitor current isI rms tot+I rms2)I dis2Ǹ+6.19AThe manufacturer’s maximum RMS current specified at85°C and 120 Hz is 3.15 A. At less than 55°C, this value ismultiplied by a factor of 2 or 6.30 A. This is still acceptablein most commercial applications. Higher valued capacitancereduces the charging capacitor duty cycle, increases theRMS current in the capacitors, and increases the peakcharging current, which puts severe stress on the inputrectifiers.Repeating the above calculations for 50 Hz inputfrequency, the RMS current comes out to be 5.92 A, stillwithin the capacitor’s specifications.The input bridge rectifier must be chosen to handle thepeak capacitor charging current and the DC current into thepower supply. Surge current limiting during start–up shouldalso be provided.Power Transformer DesignOperating at 200 kHz, the criteria for core selection is a complicated process, and beyond the scope of this paper.Core losses and winding losses due to AC resistance increase with increasing frequency and contribute to a higher temperature rise in the transformer. The core chosen is a Magnetics Inc. PQ4040, P material. The turns ratio is:n +(V IN(min)*2V T )D max V OUT )V L )V f(10)where:V IN(min) = the minimum dc voltage above which the power supply regulates,V T = the drain to source ON voltage across a MOSFET at full load,D max = the maximum duty cycle,V OUT = the output voltage,V L = dc resistance voltage drop in the filter choke at full load, andV f = forward drop across the Schottky diode at full load.n +(200*6)(0.45)+15Note that V IN(min) is lower than the input capacitor valley voltage in order to provide some hold–up time.The saturation flux density for P material at high temperature is a little above 3000 Gauss. To prevent core saturation due to a sudden load step increase at high line, and to keep the core losses down, a safe value of 1500 Gauss is used. The minimum primary turns for a forward converter limited by 50% duty cycle is given by:Np wV IN(min) 1082D B max A e f s(11)where:A e = effective core area (cm 2)f s = switching frequency, orNp u 200 1082(1500)(2.01)(2 105)+17T To obtain the right voltages for the number of turns and to fit the wire effectively in the bobbin, the primary uses 30turns composed of six #24 AWG wires in parallel. Using 5wires in parallel as opposed to a single larger wire reduces the AC resistance in the wires caused by the skin effect. To minimize the primary leakage inductance, a split primary isused to completely surround the main secondary. A four turn auxiliary winding of #30 AWG is wound on top of the primary, separated by tape, to provide good coupling with the primary. This is again repeated in the second primary half and the two paralleled auxiliary windings.The secondary consists of two turns of two 16–mil copper foil strips 0.9” wide. The ±12 V secondary is a split 10 turn winding consisting of two #19 AWG wires. Shields were also placed between the primary and the main secondary to return any noise coupled by parasitic capacitance in the windings.The transformer was designed to provide adequate line isolation. A summary of the transformer data is:The auxiliary winding provides power to the CS3842A when the IC is in operation. The two zener diodes on the auxiliary supply circuit clamp the voltage on the reset cycle to a maximum of 27.8 V , or 208.5 V on the primary side.To determine the power available in the auxiliary winding,the magnetizing current is calculated. For the PQ–4040, P material, the inductance factor, AL, given is 5020 mH/1000turns. The primary inductance is 5020(30/1000)2 = 4.5 mH.The magnetizing current is thenI mag +V min D maxL p f s +(200)(.45)(4.5 10–3)(2 105)+100mA(12)In the auxiliary winding, the current is scaledproportionally to the turns ratio, thereforeI aux +(7.5)(100mA)+750mAAveraging this current over one cycle gives a current ofI aux (1*D .x )ń2+200mAIf the reset voltage is 27.8 V during (1 – D max ), the power available is about 3.15 W.If the control circuit needs more power than the auxiliary winding can provide, the reset voltage will start to drop. To correct this problem, a small gap may be placed in the transformer core. If the energy is more than required by the control circuitry, a bleeder resistor should be added to protect the zener diodes from excessive power dissipation.Output Filter DesignDuring t OFF , a voltage equation around the loop indicated by the current direction in Figure 8 is:V L +V OUT )V F +L D I Lt OFF(13)Figure 8. The Output Filter Circuit+–+–– V +OUTV ∆I LThe maximum OFF time is determined during the minimum duty cycle.D min +V IN(min)D max V IN(max)+194V(0.45)370V+0.23(14)t OFF +(1*D min)T S +3.85m s(15)If we select the inductor ripple current, ∆I L = 8.0 A, then the value of inductance required is, from equation (13).L +V L T OFF(max)D I L+(5.6)(3.8 106)8+2.7m H(16)The maximum DC current through the inductor is 80 A.We determine the LI 2 product requirement.LI 2+(2.7 10–6 )(80)2+17.3mJ(17)This value is used in selecting the core size. The coreselected here is a Ferroxcube EC–52–3C8. EC cores are very popular because they provide adequate space for large wire sizes required for low voltage and high current applications.Because the windings are not totally enclosed by the core better cooling is possible.The required inductance factor can be calculated fromA L +(BA e )2 10–4LI 2(18)For a flux density of 1500 Gauss:A L +ƪ(1500)(1.8)ƫ2 10–4+42mH ń1000TurnsThe ampere–turns required isNI +10BA e A L+10(1500)(1.8)42+643At(19)dividing by the current the number of turns required is N +643ń80+8TThe gap required isI g +0.4p N 2A e (10–8)L+0.4p (8)2(1.8)(10–8)2.7 10–6+0.536cm or 0.211in(20)The core can be gapped by grinding the center post. You can select a gapped core like the EC52G–3C8(2X) which has a 180 mil gap and grind it to size. Another method is to add spacers between the outer posts of the core. The following relation can be used to convert the required center post gap,l g , to the length of an equivalent gap using spacers, l ′gl Ȁg +0.3643lg(21)Substituting the required value of l g we obtain l ′g = 77 mils.In order to be able to carry the full load current, two strips of 16 mil by 1 inch copper foil was used.Filter capacitance is calculated as,C +D I L 8f s D V pp(22)where V pp is the peak–to–peak output voltage ripple desired. For this application, 80 mV was chosen. ThereforeC +88(2 105)(0.08)+62.5m FThe ESR required is:R ESR +V pp I L+0.088+10m W(23)Six 10 µF polypropylene capacitors are used yielding a combined ESR of 1.5 m Ω.Current Sense CalculationThe peak current on the primary is the sum of the peak inductor currents of the secondaries referred to the primary by their turns ratios plus the magnetizing current orI pri(pk)+8415)2ǒ4.56Ǔ)0.1+7.2A ^7.5ABecause this current would require a 5 watt current sensing resistor to develop a 1 volt signal amplitude, a current transformer was used with a turns ratio of 100.I cs +7.5ń100+75mAThe required current sense resistor becomesR cs +1ń0.075+13.3WA low pass filter was used to smooth out high frequency noise coupled to the current sense signal.Closed Loop DesignThe zero associated with the capacitor bank ESR is atf ESR +12p (1.5 10–3)(60 10–6)+1.77MHzThe two load resistance extremes in the main output are:R o(min)+5.0V ń80A +0.0625W R o(max)+5.0V ń5.0A +1.0WNote that the voltage feedback loop looks only at the 5.0 V output. The output capacitor bank and the load resistance form a moving pole with corner frequencies atf p(max)+12p R o(min)C+42kHz (24)f p(min)+1o(max)+2.65kHz (25)The output–to–control signal is expressed asV O V C +IL V CR O H f (S)+nn ȀR o 3R cs ǒ1)S R ESR C 1)S R O C Ǔ(26)where:n = primary to second turns ration ′ = current sense transformer turns ratio.At maximum loadV O C+15(100)(0.0625)+2.35,7.42dBf → oAt minimum loadV O V C+15(100)(1)3(13.3)+37.6,31.5dBf → oFor good overall stability, the unity gain loop crossovershould be chosen at a frequency less than one–fourth the switching frequency. Selecting the crossover frequency to be 42 kHz, the error amplifier is required to provide –7.42 dB gain at crossover. The compensation network is shown in Figure 9.By letting the error amplifier gain cross unity at 2.65 kHz, a good overall gain bandwidth product with adequate phase margin is possible. Calculating the corner frequency for the zero, we have.7.42+–20(log 2.65*log f z )Solving for f z we get 6.23 kHz.Figure 9. Frequency Response Diagram for Power Supply. Inset E/A Configuration10100 1 k 10 k 100 k 1 M–40–2020406080G A I N (d B )To provide –7.42 dB, the attenuation ratio should be 0.4256.The error amplifier output is attenuated by a factor of 3 inside the CS3842A. Choosing C 1 to be 2.2 nf and R 1 = 10 k Ω, R 2becomes 11.6 k Ω. The gain frequency response curves are shown in Figure 9.To provide isolated output voltage feedback to the error amplifier a small signal transformer, T4, is used. This transformer is switched at 200 kHz by using the power transformer’s 5.0 V secondary output to drive a transistor.On the secondary side of T4, one diode is used to rectify the output while another diode is is used to cancel the effect of the first diode.Other ConsiderationsWhen designing high power converters, the combined effect of high power with high frequency requires a very careful layout. All the high di/dt paths must be identified.They must be short, and away from the control circuit.Bypassing the input DC bus should be done right at the power MOSFETs while low level bypassing should be done at the V CC input of the CS3842A. The feedback signals,especially the one from the voltage feedback, go to the highimpedance input of the error amplifier and can not be bypassed without affecting the amplifier’s dynamic performance. The use of a separate low level ground is recommended.When using the CS3842A to drive inductive loads, as in the case of transformer coupled drive circuits, there is a tendency to drive the output pin below ground, thus interfering with the IC’s operation. To correct this problem,a low power Schottky diode should be connected from pins 5 to 6 to clamp the output. When the oscillator is used as a maximum duty cycle clamp, the noise on the R T /C T should be minimized.Slope compensation is not required in this application because the duty cycle is < 50% and the filter on current sense signal prevents the turn on spike from prematurely tripping the PWM comparator. To operate efficiently at light loads and reduce the ripple current on the output capacitors,the inductor current ripple is made small. Shallow inductor current ramps also reduce the peak to average inductor error to a negligible amount.Figures 10, 11, and 12 show some characteristic waveforms of this power supply.Figure 10. CS3842A Output Voltage and Current(200 mA/div)Figure 11. V DS (Top), I D (Bot.) (0.5 A/div) Low LoadFigure 12. V DS (Top), I D(Bot.) (2.0 A/div) High Load11MagneticsT1Core:Pri:Aux:Sec (5.0 V)Sec (+12 V)Magnetics Inc. P–44040–UG30T 6× #24AWG split around main secondary4T #30AWG in parallel 2T 2× .016 × .9 Cu. foil 10T C.T. 2 × #19T2Core:Pri:Secondaries:Ferroxcube 846XT250–3C816T #2214T #22T3Core:Pri:Sec:Ferroxcube 768XT188–3E2A IT100T , #32T4Core:Pri:Sec:Ter:Ferroxcube 768XT188–3E2A 8T #278T #274T #27L1Core:Winding:Ferroxcube EC52–3C88T 2× .016 × 1 Cu. foil77 mil gap on all three posts L2Core:Winding:Ferroxcube 2616PA250–3B722T 5× (2 #27 in parallel)References1.B. Holland, “Modeling, Analysis and Compensation of the Current Mode Converter,” Proceedings of Powercon 11, Paper 1–2, 19842.C. Deisch, “Simple Switching Control Method Changes Power Converter Into a Current Source,”PESC ’78 Record (IEEE Publication 78CH1337–AES), pp 300–306.ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATIONCENTRAL/SOUTH AMERICA:Spanish Phone:303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)Email:ONlit–spanish@Toll–Free from Mexico: Dial 01–800–288–2872 for Access –then Dial 866–297–9322ASIA/PACIFIC: LDC for ON Semiconductor – Asia SupportPhone:1–303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)Toll Free from Hong Kong & Singapore:001–800–4422–3781Email: ONlit–asia@JAPAN: ON Semiconductor, Japan Customer Focus Center4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031Phone: 81–3–5740–2700。
产的显示器中,电源PWM控制电路最常用的集成电路型号就是UC3842(或KA3842)
产的显示器中，电源ＰＷＭ控制电路最常用的集成电路型号就是ＵＣ３８４２（或ＫＡ３８４２）．下面简单介绍一下ＵＣ３８４２好坏的判断方法：在更换完外围损坏的元器件后，先不装开关管，加电测ＵＣ３８４２的７脚电压，若电压在１０－１７Ｖ间波动，其余各脚也分别有波动的电压，则说明电路已起振，ＵＣ３８４２基本正常；若７脚电压低，其余管脚无电压或不波动，则ＵＣ３８４２已损坏．在ＵＣ３８４２的７、５脚间外加＋１７Ｖ左右的直流电压，若测８脚有＋５Ｖ电压，１、２、４、６脚也有不同的电压，则ＵＣ３８４２基本正常，工作电流小，自身不易损坏．它损坏的最常见原因是电源开关管短路后，高电压从Ｇ极加到其６脚而致使其烧毁．而有些机型中省去了Ｇ极接地的保护二极管，则电源开关管损坏时，ＵＣ３８４２和Ｇ极外接的限流电阻必坏．此时直接更换即可．需要注意的是，电源开关管源极（Ｓ极）通常接１个小阻值大功率的电阻作为过流保护检测电阻．此电阻的阻值一般在0.2-0.6之间，大于此值会出现带不起负载的现象（就是次极电压偏低）．由于ＵＣ３８４２（ＫＡ３８４２）的工作电压和输出功率均与ＵＣ３８４3（ＫＡ３８４3）相差甚远， 3842系列和3843系列在启动电压和关闭电压方面也存在着较大的区别.前者的启动电压为16V,关闭电压为10V;后者的启动电压为8.5V，关闭电压为7.6V。
这两个系列的IC不能直接代换。
如确有必要用后者代换前者时，要对电路加以改造方可。
因此，这一点在维修工作中必须要注意．用UC3842做的开关电源的典型电路见图1。
过载和短路保护，一般是通过在开关管的源极串一个电阻（R4），把电流信号送到3842的第3脚来实现保护。
当电源过载时，3842保护动作，使占空比减小，输出电压降低，3842的供电电压Vaux也跟着降低，当低到3842不能工作时，整个电路关闭，然后靠R1、R2开始下一次启动过程。
这被称为“打嗝”式（hiccup）保护。
在这种保护状态下，电源只工作几个开关周期，然后进入很长时间（几百ms到几s）的启动过程，平均功率很低，即使长时间输出短路也不会导致电源的损坏。
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APPLICATION NOTE
INTRODUCTION
With the introduction of the CS3842A PWM IC, current–mode is possible for power supplies of a wide range of output power levels. It’s low cost makes the CS3842A particularly attractive in low power DC to DC converter applications. But because this IC can provide a high output current (1.0 A peak, 200 mA average), it is also capable of driving large power MOSFETS which can switch high amounts of power. Current–Mode vs. Voltage–Mode Control In a switching power supply, the output voltage is controlled by varying the conduction duty cycle of the power switch(es). Traditionally duty cycle control was done by comparing the amplified difference of the output voltage feedback signal and a fixed stable reference to the sawtooth waveform derived from an oscillator. This constitutes the basic voltage mode control (VMC) scheme. VMC was later improved by allowing a sample of the input voltage to vary the slope of the sawtooth waveform. This feed forward scheme provided excellent line regulation in most of the popular circuit topologies. However, the task of compensating voltage mode converters has not been simple due to its resonant peak and 40 dB/decade roll off associated with the output LC filter.
VIN
VREF ERROR AMP
RT/CT –
CLOCK S R Q LATCH IS VOUT
COMP +
Figure 1. Basic Circuit Using Current–Mode Control
© Semiconductor Components Industries, LLC, 2001
VCC 34 V Undervoltage Lock–out Circuit
Current–Mode Control With the CS3842A Figure 3 shows a CS3842A block diagram containing the basic functions necessary to implement current–mode control. This device will operate from 10 V to 30 V from a low impedance voltage source or can be current fed if the current is limited to less than 30 mA. The CS3842A is designed to be driven from the rectified line voltage for start–up, requiring a current of only 0.5 mA(typ). An auxiliary supply voltage is needed when the device is used as in Figure 4. When operating with a supply voltage between 10 V and 16 V, a bootstrap circuit provides more than 16 V to overcome the device’s under–voltage lockout circuit turn–ON threshold. The wide hysteresis band (6.0 V) accommodates variations in the input voltage.
1
April, 2001 – Rev. 1
Publication Order Number: CS3842AAN/D
CS3842AAN/D
CONTROL SIGNAL M2 IAVG. 1 IAVG. 2 IAVG. 3 M = M2/2
M2 M2
IAVG. M2 M2 M2
(a) Peak vs. Average Current Error
OSC
Oscillator
COMP SENSE
ห้องสมุดไป่ตู้
( ) Indicates CS2843A/3843A
Figure 3. CS3842A/3843A Block Diagram
2
CS3842AAN/D
VOUT VCC 120 V AC INPUT CS3842A VOUT
(b) IAVG. is Constant for Varying Duty Cycle, (Constant Load)
Figure 2. Peak Current Detection is Used to Keep IAVG Constant for Varying Duty Cycles
If the current sense signal is properly filtered, noise induced problems including the turn on spike can be avoided. By deliberately adding more slope to the current sense signal, or subtracting it from the control voltage signal, the instability due to greater than 50% duty cycle operation can be overcome. Slope compensation aids in reducing uncertainty at the point of trigger in the PWM comparator when shallow current ramps are involved. It also helps the peak current appear higher than the turn–on spike. This eliminates premature shutdown. Figure 2a illustrates how peak current detection in current mode control produces a change in the average current by relying on the feed forward property of current mode to compensate for line voltage variations. If a slope equal to one–half the negative going inductor current slope is added to the current sense signal, or subtracted from the control signal, this error is corrected (Figure 2b).
GND 16 V (8.4 V)
6.0 V (0.5 V)
Set/ Reset
5–V Reference
VREF
Internal Bias 2.50 V Output Enable NOR S + VFB – Error Amplifier R 1.0 V 2R R Current Sensing Comparator PWM Latch VOUT
In current mode control, (CMC) the control signal represents the peak inductor current and forms a second loop in the circuit (Figure 1). The advantages of current mode control are: • Instantaneous correction to line voltage variations; the inductor current slope varies with input voltage. • Stable power supply designs; the pole associated with the inductor is eliminated. • Equal current sharing in paralleled power stages when both share the same control signal and have the same current sense circuits. • No current limit amplifier is needed. • Flux balancing exists in push–pull circuits. Disadvantages: • Slope compensation is required for peak versus average inductor current error and for compensating instabilities associated with load disturbances in single ended topologies operating at greater than 50% duty cycle. Premature shutdown due to the turn on current spike caused by the reverse diode recovery of the output free wheeling diode. • Runaway conditions when half bridge topology is operated in current–mode control.