3数字信号处理器

Words and Expressions

follow v.遵循memory n.存储器

register n.寄存器access v.访问

overlap v. 重叠pipelining n. 流水线操作multiplier n. 乘法器accumulator n. 累加器shifter n.移位器reference n. 寻址mantissa n.尾数exponent n. 指数

cycle n. 机器周期customize v.定制，用户化package v.封装

digital signal processor 数字信号处理器von Neumann architecture 冯·诺伊曼结构shared single memory 单一共享存储器program instruction 程序指令

harvard architecture 哈佛结构

fetch from 从…获取

circular buffer 循环缓冲区，环形缓冲区address generator 地址产生器

fixed point 定点

floating point 浮点

binary point 二进制小数点

available precision 可用精度

dynamic range 动态范围

scale range 量程

smallest Resolvable Difference 最小分辨率scientific notation 科学计数法assembly language 汇编语言

multi-function instructions 多功能指令parallel architecture 并行结构

looping scheme 循环机制

sampling frequency 采样频率on-chip memory 片内存储器

well-matched 非常匹配

software tools 软件开发工具

low level programming language 低级编程语言high level programming language 高级编程语言third party software 第三方软件

board level product 板级产品

data register 数据寄存器

ALU=Arithmetic Logical Unit 运算逻辑单元program sequencer 程序定序器

peripheral sections 外设

single integrated circuit 单片集成电路

cellular telephone 蜂窝电话

printed circuit board 印刷电路板

licensing agreement 专利使用权转让协定custom devices 定制器件

extra memory 附加存储器

stand alone 单机

third party developer 第三方开发商multimedia operations 多媒体操作

merged into 融合

calculation-intensive algorithm运算密集型算法

Unit 5 Digital Signal Processors

Digital signal processing tasks can be performed by all processors. Specialized digital signal processors(DSPs), however, perform these tasks most efficiently and most quickly. While traditional processors follow the Von Neumann architecture[]1model, which assumes a shared single memory to be used for both program instructions and data, DSPs use the Harvard or modified Harvard architecture []2, which includes multiple program and data memories, along with multiple buses to access them. This arrangement means that much less waiting is required when instructions or numbers are fetched from memory. In fact at least one of each can be fetched simultaneously. Such overlapping of tasks is called pipelining. In addition to multiple memories and buses, all DSPs have fast multipliers, accumulators, and shifters, and many have hardware support for circular buffers. Address generators can speed up accesses to memory locations referenced by registers.

DSPs are available in two major classes: fixed point and floating point. The fixed point class represents real numbers in a fixed number of bits. The position of the binary point (similar to the decimal point) can be controlled by the programmer, and determines the range of numbers that can be represented. As the range increases, though, the available precision goes down, since fewer bits lie to the right of the binary point. In 16 bits, the formats 16.0, 15.1, 14.2, 13.3, 12.4, 11.5, 10.6, 9.7, 8.8, 7.9, 6.10, 5.11, 4.12, 3.13, 2.14, and 1.15 are possible. The dynamic range, calculated as 20log (Full Scale Range/Smallest

2= 96.3 dB.

Resolvable Difference), remains the same for all 16-bit formats, 20log16

Figure 6.3 Van Neumann architecture