万年历时钟表

本次课程设计要求显示万年历时钟表。

要求实现正常的时、分、秒计数。

二十四小时的时间计时。

本次课程设计采用黑金AX301开发平台。

相关硬件原理图和PCB图见文件夹。

一．各个设计模块描述（一）计时模块1.秒计数是由一个六十进制的计数器构成，生成元器件如下Clk：驱动秒计时器的时钟信号Clr：校准时间时清零的输入端En：使能端Sec0[3..0] sec1[3..0]：秒的高位显示，低位显示Co：进位输出端，作为分的clk输入代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity second isport (clk,clr,en:in std_logic;sec0,sec1:out std_logic_vector(3 downto 0);co:out std_logic);end second;architecture sec of second isSIGNAL cnt1,cnt0:std_logic_vector(3 downto 0);beginprocess(clk)beginif(clr='0')thencnt0<="0000";cnt1<="0000";elsif(clk'event and clk='1')thenif cnt1="0101" and cnt0="1000" thenco<='1';cnt0<="1001";elsif cnt0<"1001" thencnt0<=(cnt0+1);elsecnt0<="0000";if cnt1<"0101"thencnt1<=cnt1+1;elsecnt1<="0000";co<='0';end if;end if;end if;end if;sec1<=cnt1;sec0<=cnt0;end process;end sec;仿真图如下：2．分计数是由六十进制的计数器构成，生成元器件如下Clk：设置分输入和秒进位的或输入En：使能输入Min1[3..0] min0[3..0]:分的高位显示，低位显示Co：向时的进位输出代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity minute isport (clk,en:in std_logic;min1,min0:out std_logic_vector(3 downto 0);co:out std_logic);end minute;architecture min of minute isSIGNAL cnt1,cnt0:std_logic_vector(3 downto 0);beginprocess(clk)beginif(clk'event and clk='1')thenif en='1' thenif cnt1="0101" and cnt0="1001" thenco<='1';cnt0<="0000";cnt1<="0000";elsif cnt0<"1001" thencnt0<=(cnt0+1);elsecnt0<="0000";cnt1<=cnt1+1;co<='0';end if;end if;end if;min1<=cnt1;min0<=cnt0;end process;end min;仿真图如下：3．时计数是由二十四进制的计数器构成，生成元器件如下Clk:设置时间输入和分进位输入的或en：使能端h1[3..0] h0[3..0]:时的高位显示和低位显示代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity hour isport(clk,en:in std_logic;h1,h0:out std_logic_vector(3 downto 0));end hour;architecture beha of hour issignal cnt1,cnt0:std_logic_vector(3 downto 0);beginprocess(clk)beginif(clk'event and clk='1') thenif en='1' thenif cnt1="0010" and cnt0="0011" thencnt1<="0000";cnt0<="0000";elsif cnt0<"1001" thencnt0<=cnt0+1;elsecnt0<="0000";cnt1<=cnt1+1;end if;end if;h1<=cnt1;h0<=cnt0;end process;end beha;仿真图如下：（二）设置时间模块1.按键去抖动，生成元器件如下Clk：256hz频率输入Reset：接GNDDin：接按键Dout：输出传给按键选择器代码如下library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity debounce isport(clk,reset:in std_logic; --200HZdin:in std_logic;dout:out std_logic);end debounce;architecture a of debounce istype state is(s0,s1,s2);signal current:state;process(clk,reset,din)beginif(reset='1')thencurrent<=s0;dout<='1';elsif (clk'event and clk='1')then case current iswhen s0=>dout<='1';if(din='0')thencurrent<=s1;elsecurrent<=s0;end if;when s1=>dout<='1';if(din='0')thencurrent<=s2;elsecurrent<=s0;end if;when s2=>dout<='0';if(din='0')thencurrent<=s2;elsecurrent<=s0;end if;when others=>dout<='1'; current<=s0;end case;end if;end process;end a;仿真图如下：2.按键选择器，生成元器件如下：Clk：16hz输入Key1:按键调分的输入Key2:按键调时的输入Key3:按键秒清零的输入Led1:输出信号给分元器件Led2:输出信号给时元器件Led3:输出清零信号给秒元器件代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity ctr1 isport(clk:in std_logic; --10HZkey1,key2,key3,key4:in std_logic;led1,led2,led3,led4:out std_logic);end ctr1;architecture a of ctr1 isbeginprocess (clk)beginif(clk'event and clk='1')thenif(key1='0')thenled1<='1';led2<='0';led3<='0';led4<='0';elsif(key2='0')thenled1<='0';led2<='1';led3<='0';led4<='0';elsif(key3='0')thenled1<='0';led2<='0';led3<='1';led4<='0';elsif(key4='0')thenelseled1<='0';led2<='0';led3<='0';led4<='0'; end if;end if;end process;end a;仿真图如下：（三）整点报时模块生成元器件如下：Clk1：接512hzClk2 clk：En：使能输入M1[3..0] m0[3..0]:接分的高位输出和低位输出S1[3..0] s0[3..0]:接秒的高位输出和低位输出Speaker：连接蜂鸣器代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xiang isport(m1,m0,s1,s0:in std_logic_vector(3 downto 0);en,clk1,clk2,clk:in std_logic;speaker:out std_logic);end xiang;architecture sss_arc of xiang isbeginprocess(clk,clk1,clk2,m1,m0,s1,s0)beginif(en='1')thenspeaker<=clk;elsif(m1="0101"and m0="1001")thenif(s1="0101")thenif(s0="1001")thenelsif(s0="0001" or s0="0011" or s0="0101" or s0="0111")thenspeaker<=clk1;--512HZend if;elsespeaker<='0';end if;elsif(m0<"1001" or m1<"0101"or s1<"0101")thenspeaker<='0';end if;end process;end sss_arc;仿真图如下：（四）显示时间模块1.模八的器件控制八个数码管显示的循环，生成元器件如下Clk：输入Clr：接GNDEn：使能端Y[2..0]:输出接数码管三个接受端代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mo8 isport(clr,clk,en:in std_logic;y:out std_logic_vector(2 downto 0));end mo8;architecture beha of mo8 issignal p:std_logic_vector(2 downto 0);beginprocess(clk)beginif clk'event and clk='1' thenif en='1' thenif p="111" thenp<="000";elsif p<"111" thenp<=p+1;end if;end if;end if;y<=p;end process;end beha;仿真图如下：2.八选一的器件控制数码管的亮或不亮，生成元器件如下Sel【2..0】：连接模八器件M7[3..0] m6[3..0]:连接秒的高位和低位输出M5[3..0]:接vcc（显示横）M4[3..0] m3[3..0]:接分的高位和低位输出M2[3..0]:接vcc（显示横）M1[3..0] m0[3..0]:连接时的高位低位输出Y[3..0]:输出给数码管显示代码如下：library ieee;use ieee.std_logic_1164.all;entity mux8_1 isport(m0,m1,m2,m3,m4,m5,m6,m7:in std_logic_vector(3 downto 0); sel:in std_logic_vector(2 downto 0);y:out std_logic_vector(3 downto 0));end mux8_1;architecture arc of mux8_1 isbeginprocess(sel)begincase sel iswhen"000"=>y<=m0;when"001"=>y<=m1;when"010"=>y<=m2;when"011"=>y<=m3;when"100"=>y<=m4;when"101"=>y<=m5;when"110"=>y<=m6;when"111"=>y<=m7;when others=>y<="XXXX";end case;end process;end arc;仿真图如下：3.数码管显示器件，生成元器件如下Num[3..0]:接收八选一的输出信号Y[6..0]:驱动数码管显示代码如下：library ieee;use ieee.std_logic_1164.all;entity xianshi isport(num:in std_logic_vector(3 downto 0);y:out std_logic_vector(6 downto 0));end xianshi;architecture beha of xianshi isbeginprocess(num)begincase num iswhen"0000"=>y<="0111111";when"0001"=>y<="0000110";when"0010"=>y<="1011011";when"0011"=>y<="1001111";when"0100"=>y<="1100110";when"0101"=>y<="1101101";when"0110"=>y<="1111101";when"0111"=>y<="0000111";when"1000"=>y<="1111111"; when"1001"=>y<="1101111";when others=>y<="1000000";end case;end process;end beha;仿真图如下：（五）分频模块分频器生成的元器件如下：Clk：时钟输入Clk512:512hz给响铃模块Clk1：1hz输出给秒计数器Clk16:16hz输出给按键选择器Clk256:256hz输出给按键抖动代码如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpin isport(clk:in std_logic;-- q:out std_logic_vector(9 downto 0);clk512,clk4,clk1,clk16,clk256:out std_logic); end fenpin;architecture behave of fenpin issignal y:std_logic_vector(9 downto 0);beginprocess(clk)beginif(clk='1')thenif(y="1111111111")theny<="0000000000";clk512<=y(0);clk256<=y(1);clk16<=y(5);clk4<=y(7);clk1<=y(9);elsey<=y+'1';clk512<=y(0);clk256<=y(1);clk16<=y(5);clk4<=y(7);clk1<=y(9);end if;end if;end process;end behave;仿真图如下：闹钟模块1.比较器，比较当时显示时间与设置的闹钟时间是否相等，如相等，输出信号给蜂鸣器。