圆片级封装介绍(wafer level packaging)

Table of ContentsINFORMATION (1)1 CONTACT2 INTRODUCTION (3)2.1Overview (3)2.2History (3)3 CHOOSING A BUMPING PROCESS (5)3.1Standard Flip Chip – Bump on I/O (5)3.1.1Standard Flip Chip-Bump on I/O Process Summary (6)3.1.2I/O requirements for the SFC-Bump on I/O process (7)3.2Standard Flip Chip--Repassivation (8)3.2.1SFC-Repassivation Process Summary (9)3.3Standard Flip Chip--Redistribution (10)3.3.1SFC-Redistribution Process Summary (10)3.4Spheron TM WLCSP (12)3.4.1Spheron WLP™ Redistribution Process Flow (12)3.5Ultra CSP® (14)3.5.1Ultra CSP Process Summary (14)3.6Elite UBM™, Elite FC™, and Elite CSP™ – Electroless Ni/Au (17)3.6.1Elite UBM™ – Process Flow (17)3.6.2Elite FC™ – Process Flow (18)3.6.3Elite CSP™ – Process Flow (19)3.7Available Solder Alloys (21)3.7.1Basic Physical Properties of Solder Paste Alloys (21)3.7.2Basic Physical Properties of Pre-Formed Solder Ball Alloys (21)3.8Other Services (22)3.8.1Laser Mark (22)3.8.2“In Process” Backgrind (22)3.8.3“Post Process” Backgrind (22)3.8.4Electronic Wafer Yield Maps (23)3.8.5Post Bump Electrical Testing (23)3.8.6Dicing and Packaging (23)4 DESIGN RULES AND GUIDELINES (24)4.1Overview (24)4.2Incoming Wafer Requirements (24)4.2.1Types of Wafers (24)4.2.2SEMI Material Requirements (24)4.2.3Wafer Scribe Requirements (24)4.2.4Wafer Backside Requirements (24)4.2.5Acceptable Wafer Size (24)4.2.6Wafer Edge Exclusion Requirements (25)4.2.7Incoming Wafer Thickness (25)4.3Device Requirements (25)4.3.1Die Size (25)4.3.2Number of Sites Bumped Per Die (25)4.3.3Die Layout (25)4.3.4Unique Die on Wafer (25)4.3.5Types of Passivation (26)4.3.6Types of Final Metal (26)4.3.7Probing (26)4.3.8Ink Dots (26)4.3.9Fuse Links (27)4.3.10Nitride Passivation Openings Not Bumped (27)4.3.11Street Width (27)4.3.12Special Elite UBM, Elite FC, and Elite CSP Device Requirements (27)4.3.13Passivation Opening Sidewalls (28)4.4Alignment Feature Requirements (28)4.5What Information Does FlipChip Need For New Mask Designs? (29)CONSIDERATIONS (30)5 DESIGN5.1Pitch, UBM Size, and Bump Height Relationships (30)5.2Packaging Relationships (31)5.2.1SFC, Repassivation, and Redistribution Package Stand-Off Height (31)5.2.2UltraCSP, Spheron WLP, and EliteCSP Package Dimensions (31)5.2.3WLP Package Stand-Off Heights (32)5.3Printed-Circuit Board Layout (33)5.3.1WL-CSP Stencil and Board Design Parameters (34)5.4Reliability Testing (34)PROPERTIES (35)6 MATERIAL6.1Benzocyclobutene (BCB) (35)6.2Spheron WLP Polymer (36)6.3Solder Alloy Material Properties (37)6.4UBM Metal Properties (37)6.5SFC-Redistribution Trace Electrical Properties (38)6.6Ultra CSP Redistribution Trace Electrical Properties (38)7 GLOSSARY (39)1Contact InformationTo start your relationship with FlipChip, contact the appropriate Sales Representative. Each is an expert at learning the particular needs of your device. In addition, your FlipChip Sales Representative can discuss all aspects of pricing, logistics, cycle time, and answer any other question you may have.Worldwide Sales RepresentativesFred Hickman IIIVice President -- Sales and MarketingFlipChip International, LLCPhoenix, AZ, USA 85034Phone: 602-431-4749E-mail: fred.hickman@AsiaJay HayesSr. Director of Strategic AccountsFlipChip International, LLCMonument, CO, USAPhone: 719-481-6444E-mail: jay.hayes@California and Northwest U.S.A.Jim GrahamRegional Account ManagerFlipChip International, LLCSanta Clara, CA, USAPhone: 408-395-4765Cell: 408-761-0808E-mail: jim.graham@Southwestern U.S.A., Eastern U.S.A., Canada andGeneral Technical InquiresBret TrimmerSr. Account ManagerFlipChip International, LLCPhoenix, AZ, USAPhone: 602-431-4760Cell: 480-643-9034E-mail: bret.trimmer@Central U.S.A.Bruce BowersVice President -- Business Development FlipChip International, LLCPhoenix, AZ, USAPhone: 602-431-6634E-mail: bruce.bowers@EuropeDave McCombDirector of European Business and Sales FlipChip International, LLCHawick, Scotland, UKPhone: +44 1450 373 919E-mail: david.mccomb@EuropeDavid ClarkEuropean Sales EngineerFlipChip International, LLCIpswich, Suffolk, UKPhone: +44 7875 307 633 E-mail: david.ckark@2 Introduction2.1 OverviewThank you for your interest in FlipChip International, LLC for your wafer bumping needs. This guide will take you through the process of deciding which bumping flow is right for you. In addition, the guide will give you the basics of each process flow, incoming wafer requirements, device requirements, material properties, and a glossary, so you may have a better understanding of the bumping process.2.2 HistoryFlipChip International, LLC started out in 1996 as Flip Chip Technologies (FCT), a joint venture between Delco Electronics Systems and Kulicke & Soffa Industries (K&S). Delco brought the patented Flex-On-Cap (or FoC) flip chip process and over 30 years of experience from the automotive industry. K&S added its knowledge and leadership position as the world's largest supplier of semiconductor assembly equipment. By any measure, the company was a huge success. The company’s Flex-on-Cap (FoC) standard flip chip bumping technology quickly became the industry standard for flip chip bumping.In 1998, FCT developed and patented the Ultra CSP® Wafer Level Chip Scale Package (WL-CSP), which quickly became the industry standard for WL-CSP. FlipChip began an aggressive licensing program to bring its unique bumping technology to a broader worldwide market. Today, the semiconductor industry’s packaging heavyweights, including Amkor Technology, Advanced Semiconductor Engineering (ASE), Siliconware (SPIL), and STATS ChipPAK license and use FlipChip’s bumping technology.In 2001, K&S acquired Delco’s remaininginterest in FCT and we became the Flip ChipDivision of Kulicke & Soffa. In 2004,RoseStreet Labs, LLC, a private research anddevelopment company based in Phoenix,completed the acquisition of the assets of theFlip Chip Division from Kulicke & Soffa, throughits newly formed subsidiary -- FlipChipInternational, LLC. In early 2005, FCI acquiredIC Services, which became the Die SalesDivision of FCI (or FCI-DSD). The Die SalesDivision continues its long tradition of providingwafer thinning, dicing, Automated OpticalInspection (AOI), Waffle Pack, and Tape & Reelservices.In 2005 FlipChip acquired a license to produce Electroless Ni/Au from the Fraunhofer/IZM Institute of Berlin. The initial target applications of E-less Ni/Au are high temperature power devices and low cost RFID applications. The new process was in commercial production in 2006.In 2006, FlipChip announced that it had entered into a joint venture with Millennium Microtech to form FlipChip Millennium Shanghai (FCMS). FCMS opened in March of 2007 and provides “Turn-Key” wafer bumping and die packaging services, focusing on the Asian market.In 2007, FlipChip entered into strategic partnerships with several domestic testing houses to provide Electrical Testing as part of Turn-Key wafer processing.In addition to bumping services, FlipChip has an aggressive program to develop and generate intellectual property for future implementation at FlipChip and for our licensee’s. Our commitment to leadership and quality in wafer bumping solutions continues, ensuring that FlipChip remains the leader in developing, and bringing to market, the latest bumping technology.The main bumping facility for FlipChip is located in the World Headquarters building in Phoenix, Arizona, USA. We have a state of the art, 16,000-ft2 (4700 m2) class 1000 clean room. FlipChip is ISO9001:2000 and ISO14001 certified.FCI World Headquarters –- Phoenix, AZ Die Sales Division -– Tempe, AZFCMS Bumping Facility -- Shanghai, China RoseStreet Labs Facility -- Phoenix, AZ3 Choosing a Bumping ProcessHere we look at the different bumping services offered by FlipChip. To make it easy, we have broken our services into the different processes. Each one is perfect for a different bumping situation, from the simplest to the most complex. Look these over and decide which process will meet your needs. If you still can’t decide, give us a call! We’ll be glad let you know which process will work best for you. We are experts at matching up a standard process flow to your device. Keep in mind that we are a development driven engineering organization. For unusual devices, we can often design a custom process flow that will completely meet your needs.3.1 Standard Flip Chip – Bump on I/OOur Standard Flip Chip (SFC) process, formerly known as the Flex-on-Cap (or FoC) process, was created in the mid-1960’s by Delco for use in the automotive industry. Today, the process has 40 years and over a million bumped wafers behind it. This is the process to use when you need to place small bumps (less than 135µm in height) directly on the die I/O. Pitch capabilities in this process are 150µm or greater for a full array I/O design and 120µm or greater for a peripheral I/O design. Typically, the number of bumps per die ranges from 4 to 6000. The SFC process uses premixed solder paste for the solder bumps. This provides for outstanding control of the alloy composition across the entire wafer. Since the process is not limited to the bi-metal restraints of an electroplating process, tri-metal alloys (such as Sn/Ag/Cu) require nothing more than the selection of the proper tube of pre-mixed solder paste. As with all die processed with small bumps, these die will require the use of underfill during packaging.To take advantage of this process flow, the device must meet some minimum I/O pad requirements (described below in section 3.1.2). If the device does not meet these minimum I/O pad requirements, take a look at section 3.2, which describes the SFC Repassivation flow. If you are looking for bump heights greater than 135µm, take a look at section 3.4, which covers the UltraCSP flow – the industry standard Wafer Level Package (WLP) process flow.3.1.1 Standard Flip Chip-Bump on I/O Process SummaryThe SFC-Bump on I/O process requires the fewest process steps of any flow that FlipChip offers. Below is an outline of the flow:UBM3.1.2 I/O requirements for the SFC-Bump on I/O processSince the SFC-Bump on I/O process forms a bump directly on the device I/O, certain criteria must be followed to ensure a proper bump structure. The basic rule is what we call “The Golden Rule of Flip Chip”, which is:•The UBM must overlap the I/O passivation opening by at least 7µm and the I/O final metal pad must extend at least 5µm past the end of the UBM.Figure 1 shows the “Golden Rule” requirements for the UBM in relation to the passivation opening and the I/O metal bond pad. This rule requirement accomplishes several reliability requirements. The overlap of the UBM to the passivation opening provides a seal to the underlying I/O aluminum bond pad. The overlap of the UBM inside the I/O metal bond pad eliminates stresses that can cause silicon cratering.Figure 1. The Golden Rule of Flip ChipThe allowable size of the UBM is directly related to I/O Pitch. The bump height is strongly influenced by UBM size. Please see the section 5.1 “Pitch, UBM Size, and Bump Height Relationships” as a guide as to what size your UBM will be.If your device does not meet the requirements of the Golden Rule, your device may be a candidate for the SFC-Repassivation process, which is described in the next section.3.2 Standard Flip Chip--RepassivationThe SFC-Repassivation process is similar to the SFC-Bump on I/O process, but it is designed for die that do not meet all of the I/O final metal pad and passivation opening requirements of SFC-Bump on I/O. In this process, a layer of Benzocyclobutene (or BCB) repassivation is deposited on the die before bumping. The BCB passivation corrects for the issue of the I/O passivation opening being too large for a standard flip chip bump. It also corrects for the issue of the I/O final metal pad being too small for a standard flip chip bump. The BCB layer planarizes the device surface and gives the bump structure additional strength and robustness.As with SFC-Bump on I/O, SFC-Repassivation is designed for small bumps (less than 135µm) placed directly on the die I/O. Pitch capabilities in this process are 150µm or greater for a full array I/O design and 140µm or greater for a peripheral I/O design. The number of bumps per die typically ranges from 4 to 600. The SFC-Repassivation process uses premixed solder paste for the solder bumps. This provides for outstanding control of the alloy composition across the entire wafer. Since the process is not limited to the bi-metal restraints of an electroplating bath, tri-metal alloys (such as Sn/Ag/Cu) require nothing more than the selection of the proper tube of pre-mixed solder paste. As with all die processed with small bumps, die bumped with the SFC-Repassivation process will require the use of underfill during packaging.If your device contains bumps that will not be placed directly on the I/O, take a look at the next section (3.3), which describes the SFC-Redistribution flow. If you are looking for bump heights greater than 140µm, take a look at section 3.4, which covers the UltraCSP flow – the industry standard Wafer Level Chip Scale Package (WL-CSP) process flow.3.2.1 SFC-Repassivation Process SummaryThe SFC-Repassivation process requires relatively few process steps to complete the flow. Below is an outline of the process flow (none of the drawings are to scale):Deposit and pattern a layer of BCB passivation.Deposit three layer (Al/NiV/Cu) Under Bump Metalization (or UBM) stack.Pattern UBM pads.Deposit pre-mixed solder paste.Reflow solder.- PIQ3.3 Standard Flip Chip--RedistributionOn some die, the I/O are not located where you need to have the bumps. This is especially true when you take an existing die that is wire bonded and would like to convert it to flip chip. The SFC-Redistribution Line (or RDL) process adds “redistribution metallization” (often called “runners’ or “traces”) that let you re-route the signal path from the die peripheral I/O to the new desired bump locations. This process is usually seen as a transitional solution between a die that is designed for wire bonding and a die that is designed for flip chip. Redistribution is designed to produce bumps of less than 135µm in height, although the typical bump height is 100µm. Pitch capabilities in this process are 70µm or greater. Standard Redistribution line widths are 38µm with 38µm space between lines. For fine pitch designs, FlipChip will go down to 25µm lines and 12µm space between lines. Since the process is not limited to the bi-metal restraints of an electroplating bath, tri-metal alloys (such as Sn/Ag/Cu) require nothing more than the selection of the proper tube of pre-mixed solder paste. As with all die processed with small bumps, these die will require the use of underfill during packaging.3.3.1 SFC-Redistribution Process SummaryThe SFC-Redistribution process requires more process steps than the SFC-Bump on I/O or the SFC-Repassivation flows. Below is an outline of the SFC-Redistribution process flow (none of the drawings are to scale):Deposit and pattern first layer of BCB passivation (BCB1).Deposit four layer (Al/NiV/Cu/Ti) UBM stack.I/O Final Metal Bond padEtch UBM stack to form redistribution runners and bump pads.Deposit, pattern, and cross-link second layer of BCB passivation (BCB2).Deposit solder paste (Proprietary Process).Reflow solder.Cu UBM3.4 Spheron TM WLCSPFlipChip offers a new type of Wafer Level Chip Scale Packaging (WLCSP) that utilizes a unique dielectric material, which offers improved capacitance decoupling and reliability. In addition to the advanced polymer, Spheron WLP TM incorporates a new metal structure, which offers improved strength and electrical performance. Benefits of Spheron WLP include: improved electrical performance, reduced capacitive coupling between UBM/Solder and the underlying IC circuitry, improved solder joint reliability, significant improvement in TC performance due to die planarization/polymer film characteristics, and elimination of incoming wafer topology issues. In addition, the planarized polymer film ensures proper UBM step coverage, even over non-planarized devices. Spheron is compatible with nitrides and oxides.As with Ultra CSP, pre-formed solder balls of 250µm to 500µm are placed on the wafer and reflowed for final bump heights of 200µm to 400µm. In this process, the bumps can be placed directly on the device I/O’s or the signal may be redistributed to a more desirable die location. Typically, the number of bumps per die is 4 – 100. Die bumped with Spheron WLP typically do not require underfill. Spheron WLCSP, as well as all FlipChip packages, is classified as JEDEC Level 1 compliant.3.4.1 Spheron WLP™ Redistribution Process FlowThe Spheron WLP process may be used to bump directly on I/O or may be used to redistribute bumps to a more desirable die location. An example of the redistributed process is shown (none of the drawings are to scale).I/O Final Metal Bond Wafer Silicon Device PassivationCoat first dielectric layer (Spheron1), expose, develop, and cure.Sputter metal redistribution layer. Pattern and etch to form redistribution runners.Coat second dielectric layer (Spheron2), expose, develop, and cross-link.Deposit and pattern three layer UBM (Al/NiV/Cu).Attach pre-formed solder ball.Reflow Solder3.5 Ultra CSP®Ultra CSP® is our patented Wafer Level Chip Scale Package (or WLCSP) process. Since its introduction in 1998, Ultra CSP has become the industry standard for WLCSP. Bump heights for the process range from 200µm to 450µm. In this process, pre-formed solder balls of 250µm to 500µm are placed on the wafer and reflowed. The bumps can be placed directly on the device I/O’s or the signal may be redistributed to a more desirable die location. Typically, the number of bumps per die is 4 – 100. Die bumped with Ultra CSP do not require underfill until the bump array reaches the 6x6 to 7x7 size. Then underfill may be needed. The lack of underfill makes it easy to migrate TSOP or QFP to Ultra CSP. Ultra CSP, as well as all FlipChip packages, is classified as JEDEC Level 1 compliant.3.5.1 Ultra CSP Process SummaryThe UltraCSP process may be used to bump directly on I/O or may be used to redistribute bumps to a more desirable die location. Both processes are summarized below (none of the drawings are to scale).3.5.1.1 Ultra CSP Bump on I/O -- Process FlowDeposit and pattern a layer of BCB passivation.Deposit three layer (Al/NiV/Cu) Under Bump Metalization (or UBM) stack.Pattern UBM pads.Attach pre-formed solder ballReflow solder.3.5.1.2 UltraCSP Redistributed -- Process FlowDeposit and pattern first layer of BCB passivation (BCB1).Deposit three layer (Al/NiV/Cu) UBM stack.I/O Final Metal Bond padPattern UBM Pads and Runners.Deposit, pattern, and cross-link second layer of BCB passivation (BCB2).Attach Pre-formed Solder Ball.Reflow solder.3.6 Elite UBM™, Elite FC™, and Elite CSP™ – Electroless Ni/AuIn 2005 FlipChip acquired a license to produce Electroless Ni/Au (E-less Ni/Au) from the Fraunhofer/IZM Institute of Berlin. E-less Ni/Au is available in three configurations: EliteUBM, EliteFC, and EliteCSP. EliteUBM is simply a Ni/Au pad ranging in height from 5µm to 30µm. Typical applications for EliteUBM are low cost RFID tags. Elite packages, as well as all FlipChip packages, are classified as JEDEC Level 1 compliant.EliteFC is a Flip Chip size bump that uses the low cost E-less Ni/Au UBM. Typical bump heights are 70µm - 160µm. EliteFC can often be used as a lower cost alternative to traditional Standard Flip Chip.EliteCSP is a Wafer Level-Chip Scale Package (WL-CSP) that uses the E-less UMB structure. As with Ultra CSP, pre-formed solder balls of 250µm to 500µm are placed on the wafer and reflowed for final bump heights of 200µm to 400µm. Typical applications for EliteCSP are high power / high temperature devices.Devices that are to be bumped using any of the Elite processes need to have some special requirements met. These requirements are described in Section 4.3.12.3.6.1 Elite UBM™ – Process FlowClean Aluminum/Cu Final Metal Pad.ZincApply a thin layer of Zinc to the AlCu PadSubstitute NiP for the ZincCoat UBM with a thin layer of Gold (oxidation protection).3.6.2 Elite FC™ – Process FlowDevice PassivationClean Aluminum/Cu Final Metal Pad.ZincApply a thin layer of Zinc to the AlCu PadSubstitute NiP for the ZincCoat UBM with a thin layer of Gold (oxidation protection).Deposit pre-mixed solder paste.Reflow Solder3.6.3 Elite CSP ™ – Process FlowClean Aluminum/Cu Final Metal Pad.Apply a thin layer of Zinc to the AlCu PadSubstitute NiP for the ZincDevice Passivation ZincCoat UBM with a thin layer of Gold (oxidation protection).Attach pre-formed solder ball.Reflow Solder3.7 Available Solder AlloysFlipChip offers several different solder alloys to mach your needs. By using pre-mixed solder paste and pre-formed solder balls, alloy composition is very tightly controlled. This means that your solder balls have predictable and reliable reflow characteristics.3.7.1 Basic Physical Properties of Solder Paste AlloysThe SFC-Ball on I/O, SFC-Repassivation, and SFC-Redistribution processes use pre-mixed solder paste to form the final solder bumps. The table below gives the basic properties of the paste alloys (for complete physical properties of solder alloys, see section 6.3).Table 1. Physical Proprieties of Paste AlloysAlloy / Property Sn/Ag/Cu Lead Free (SAC 351) 63Sn37Pb Standard EutecticAlloy Composition Sn 95.5%Ag 3.5%Cu 1.0%Sn 63%Pb 37%Melting 217°C Eutectic 183°C EutecticReflow Temperature 235°C to 255°C 215°C to 225°CAlpha Emissions(counts/cm2/hr)<0.002 N/A3.7.2 Basic Physical Properties of Pre-Formed Solder Ball AlloysThe Ultra CSP, Spheron, and Polymer Collar WLP processes use pre-formed solder balls. Thestandard solder ball sizes are 0.25mm (250µm), 0.3mm (300µm), 0.35mm (350µm), 0.4mm(400µm), and 0.5mm (500µm). The basic physical properties of the pre-formed solder balls arelisted on the table below (for complete physical properties of solder alloys, see section 6.3).Table 2. Physical Proprieties of Pre-Formed Solder Ball AlloysAlloy / Property Sn/Ag/Cu LeadFree (SAC 266) Enhanced Lead FreeSn/Ag/Cu (SAC 105)Eutectic63Sn37PbHigh Lead95Pb5SnAlloy Composition Sn 96.8%Ag 2.6%Cu 0.6%Sn 98.5%Ag 1.0%Cu 0.5%DopantSn 63%Pb 37%Sn 5%Pb 95%Melting Point 218°C – 220°C 218°C – 220°C 183°CEutectic 308°C - 314°CReflow Temperature 235°C to 255°C 235°C to 255°C 215°C to225°C 325°C to 335°CAlpha Emissions (counts/cm2/hr) <0.002 <0.002 N/AN/A3.8 Other Services3.8.1 Laser MarkFor die identification and traceability, FlipChip gives you theoption of using a Laser to mark the backside of each die.FlipChip can mark any alphanumeric character down to aminimum character size of 0.20 mm square with a characterdepth of approximately 4 - 6µm. Simple graphics includingcircles, squares, triangles, etc. can be used for the optionalpin 1 indicator. We can even mark simplified graphicsconsisting of basic shapes including circles, squares,triangles, etc. for company logos. FlipChip has thecapability to mark accurately any die to a minimum diedimension of 0.8 mm. If you need custom designs, giveFlipChip a call. We can custom match a laser program foryour needs.3.8.2 “In Process” BackgrindMany times, wafers need to be thinned to meet final packaging requirements. For Ultra CSP, Spheron WLP, EliteCSP, and Polymer Collar WLP, FlipChip has the ability to backgrind wafers, during processing, just before the solder balls are applied. Wafers are course ground with a wheel of 320 – 360 grit and polished ground with a wheel of 2000 grit. Below are our backgrinding/processing capabilities. (For thickness requirements on incoming wafers, please see section 4.2.7 “Incoming Wafer Thickness.”) Please contact FlipChip if you have thinner backgrinding requirements.Table 3. Wafer Thickness After “In Process WL-CSP” BackgrindingWafer Size 6 inch (150mm) 8 inch (200mm)Minimum Wafer Thickness After Backgrind 14 mil(356µm)14 mil (456µm)3.8.3 “Post Process” BackgrindFor Standard Flip Chip (SFC), Repassivated Standard Flip Chip (RP-SFC) and Redistributed Standard Flip Chip (RP-SFC), FlipChip has the ability to backgrind wafers, after the bumping process is completed Wafers are course ground with a wheel of 320 – 360 grit and polished ground with a wheel of 2000 grit. Below are our backgrinding/processing capabilities. Please contact FlipChip if you have thinner backgrinding requirements.Table 4. Wafer Thickness After “Post Process SFC” BackgrindingWafer Size 6 inch (150mm) 8 inch (200mm)Minimum Wafer Thickness After Backgrind 12 mil(305µm)12 mil (305µm)3.8.4 Electronic Wafer Yield MapsWafer yield mapping data is either presented on paper (shipped with the wafers) or by electronic wafer maps (transmitted over secure FTP sites). FlipChip uses Simplified INF (SINF), the industry standard file format, for all electronic wafer maps. FTP sites can be easily and quickly set up for secure data transfer. Contact FlipChip for details.3.8.5 Post Bump Electrical TestingAfter bumping, FlipChip can have the dice electrically tested on a variety of test platforms including:•Advantest•Agilent / HP•Credence•Eagle•Credence•Nextest•LTX•TeradyneContact FlipChip for a complete description of electrical testing capabilities.3.8.6 Dicing and PackagingIf desired, FlipChip will have your finished wafers diced, to your specifications. After dicing, visual inspection, either by sampling or 100% will be performed. The die will then be packaged in tape-and-reel or waffle pack configurations. For complete dicing and packaging descriptions and capabilities, contact FlipChip.4 Design Rules and Guidelines4.1 OverviewFlipChip has developed a set of design rules and guidelines to ensure that your wafers will be processed successfully. These rules allow for FlipChip to use standardized process flows using industry standard process equipment. FlipChip has extensive data that shows the reliability of devices processed under these design rules. The rules presented below represent a generalization of the actual FlipChip Design Specifications, which are subject to revisions and may not apply to all devices. If you have wafers that do not meet these guidelines or if you have any questions, give FlipChip a call. Since we are a development driven engineering organization, we can often create a custom solution to for even the most unusual bumping situation. We will always work with you to ensure your total satisfaction.4.2 Incoming Wafer Requirements4.2.1 Types of WafersFlipChip can process Silicon (all types) and Silicon/Germanium wafers. Contact FlipChip if you have other types of wafers (Quartz, Sapphire, etc.), we will discuss our capabilities on non-standard wafer types. FlipChip cannot currently process GaAs wafers.4.2.2 SEMI Material RequirementsAll wafers must meet current SEMI material requirements. These specifications cover major areas such as: wafer diameter (dimension and tolerance), polish, edge profile, notches, and major and minor flat sizes, locations, and orientations. It is highly recommend that 8-inch (200 mm) wafers have a notch rather than a flat.4.2.3 Wafer Scribe RequirementsIt is highly recommended that each wafer have a unique scribe number. Typically, the device lot number and the wafer number (within the lot) are scribed on each wafer.4.2.4 Wafer Backside RequirementsFor proper processing, the backside must be smooth, without ridges, bumps, or protrusions. The backsides of incoming wafers ideally should be exposed Silicon or Silicon/Germanium. Some types of backside coatings are acceptable. Call FlipChip if your wafers are backside coated.4.2.5 Acceptable Wafer SizeFlipChip accepts wafers of the following sizes: 6 inch (150mm), and 8 inch (200mm). If you have other wafer sizes, contact FlipChip and we will discuss our capabilities on non-standard wafer sizes.。