纳米逻辑芯片制造流程
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• PLDD1 Photo (113 layer) – Implant: • P Pocket implant: (A130K30E3T30R445) • PLDD implant (F005K20E4T00) – PLDD1 Asher & Wet Strip (21+ SPM)
✓ Hot carrier effect
N-Well
P-Well
15
LDD1 Definition (Core device, 1.8V)
• NLDD1 Photo (116 layer) – Implant: • N Pocket implant (D130K25E3T30R445) • NLDD implant (A003K80E4T00) – NLDD1 Asher & Wet Strip (21+ SPM)
B160K15E3T00 B025K44E2T00 D170K70E2T00 Mattson: 21 SPM only
N_VT N pthru P WELL
13
Thick/ Thin Gate oxide define
• SAC OX RM
NLH60A (50:1 HF 65sec)
• SAC OX THK-PO PAD (3200+-400 A)
VTP IMP
A130K90E2T00
VT注入，靠近器件表面，调节器件的开启电压
• NWELL Asher
Mattson: 21
• NWELL Wet Strip
SPM only
• NWELL Anneal Precln
MRCAM (SC1+SC2)
• IMPLANT DAMAGE ANNEAL N2(PVD)
for line-end shorting & island missing ✓Composite Spacer (ONO) ✓ PSM method apply on CT layer ✓Cobalt salicide process ✓Low K IMD layer (FSG)
5
Outline
• AA Photo (120 layer) • AA Etch (5800A)
SiN/Ox+Si etch ( 80 +-2degree)
• AA Asher
Mattson ( Rcp: 1 )
• Polymer & Wet Strip NDH15APRRMSC1M ( 100:1 HF 30sec)
•
• STI Pre-CMP THK-PO PAD (3600+-250 A) , SIN (1050+-50)
• AA NIT RM
NLH90AHPO2450A (50:1 HF + H3PO4)
• THIN OXIDE THK-P PAD ( 82+-17)
• STI PAD OX RM
NLH60A (50:1 HF 65 sec)
As buffer layer to release stress, due to SIN and Si different lattice constant
1625Å Nitride 110Å PAD Oxide
•Nitride DEP (w/I scrubber )
1625+- 100A / 760oC
1000RTA010S (1000C; 10sec
P-VT P-pthru
N-Well
P-Well
12
P-Well and Vt_N adjustment
• P_Well Photo (191 layer) • Implant:
• P WELL IMP • N CHANNEL IMP • N_VT IMP • PWELL Asher • PWELL Wet Strip
• GATE2_OX PreCln
NCRRCAM
• GATE2 OX
750 C, 27+-2 A, wet
2000A poly
50Å thick gate oxide Final 70 A
32Å thin gate oxide
Thin gate
Thick gate
14
Poly Gate Definition
018LG Process Introduction (1P6M)
1
Logic Circuit: 能够 展现 精确的模拟特性，
ASIC: 为了满足消费者特定需求而专门设计的半导体 电路
• SOC与IC组成的系统相比，由于SOC能够综合并全盘考虑整个系统 的各种情况，可以在同样的工艺技术条件下实现更高性能的系统指 标 – 若采用IS方法和0.35m工艺设计系统芯片，在相同的系统复杂 度和处理速率下，能够相当于采用0.25 ~ 0.18m工艺制作的IC 所实现的同样系统的性能 – 与采用常规IC方法设计的芯片相比，采用SOC完成同样功能所 需要的晶体管数目可以有数量级的降低
STOP LAYER of STI CMP
7
STI ETCH
ADI = 0.23+-0.02
• SiON DEP(CVD)
FE DARC320 (w/I scrubber )
✓ To reduce SIN reflection and improve PR resolution as an ARC layer
• SAC OX PRECLN
NCR1DH100ARCAM (100:1 HF 240sec)
• SAC OX
110+-7A/ 920oC 45min dry O2
As implant screen oxide
110Å SAC Oxide
11
N-Well and Vt_P adjustment
• N_Well Photo(192 layer)
metal ion
• ZERO Photo
Wafer Mark (For Wafer alignment) • Scrubber Clean (TJBB) • Start oxide RM NLH320A (50:1 HF 350 sec) • Meas: Ox RM THK (25~35A) • AA OX Pre-cln
• GATE Wet Strip
NDH5APRRM (100:1 HF 10sec +SPM)
• THICK GATE OXIDE THK-P PAD (25+-5 A)
• SION RM
NLH5AHP0550A 50:1 HF +H3PO4
• GATE RE-Oxidation PreCln NRCA (SC1+SC2)
• GATE1_OX PreCln
NCR1DH100ARCAM
• GATE1_OX
800C,48A+-4 A, wet
• Dual GATE Photo (131layer) (0.45+/-0.05um)
• GATE1 ETCH
N(NLB75A)
• GATE1 Strip
SPM only
• STI THK-PO PAD ( 3150+-180 A)
• POLY DEPOSITION
POLY 2000A, 620C
• SiON DEP • POLY PHOTO (130layer)
FEDARC320
ADI 0.18+-0.015um
• Poly ARC etch + Poly etch
AEI 0.18+-0.015um
• GATE Asher
Mattson (Rcp: 1)
For ASML stepper system global Wafer alignment
NCR1DH75ARCAM
• ZERO Fully dry etch
• Pad oxide 110+-7A/ 920oC dry O2
(OX 100A + SI 1200+-200 A)
• ZERO Strip
(FEOL: device) (BEOL: interconnect)
6
Wafer Start
• WAFER START & RS CHECK
P type 8 ~ 12 ohm-cm, non-EPI wafer
• Start OX 100A dry
1. PR isolation 2. Prevent the laser mark Si recast 3. Surface cleanness 4. Backside oxidation & trap the
• Anneal(Diff)
1100 C, 2 hrs (Furnace ann.)
• HDP Fill
HDPCVD OX 5.8KA W/O AR sputter
✓ To better shallow trench filling
• Rຫໍສະໝຸດ BaiduA PRECLN
NRCAM
(SC1+ SC2)
•
• HDPCVD OX RTA
1000RTA020S (1000C, 20sec ,N2)
✓ For damage reduction by HDP and HDP ox densification
5800Å HDP 1625Å Nitride 110Å PAD Oxide
9
AA Reverse
• AAR Photo (121 layer)
AAR= (AA-0.4) +0.4) -0.2
• AAR Etch
Stop on SiN
✓ 1. Better surface flatness 2. Improved throughput by OX removing
• AAR Asher
Mattson (Rcp: 1)
• AAR wet strip
NPRRM (SPM only)
AA SiN Pad oxide
P Substrate P Substrate
AA SiN Pad oxide
P Substrate
10
STI CMP & NIT RM
• STI Pre-CMP THK-PO PAD (6100+-225 A) • STI Polish & in-situ Cln (STI_XXXX) ? CMP 是磨到NIT上。
2
VDD
VDD
IN
OUT
Y
A1
A2
CMOS反相器
与非门：Y=A1A2
3
基本电路结构：MOS器件结构
基本电路结构：CMOS
4
0.18um Process Features
✓18LG adopt 27 Photo mask , if include ESD layer ✓AA/Poly/CT/ M1~M5/ V1~V5 use DUV scanner (13 layer) ✓ “ DARC” Cap on Critical layer and Top M6 ✓ Poly & M1~M5 adopt OPC (optical proximity correction)
• AA THK STI-PO PAD (5400+-160 A)
AEI = 0.25+-0.02
16250Å Nitride 110Å PAD Oxide
8
HDP Deposition
• STI PadOX PreCln
NCR1DH75ARCAM (100:1 HF 180sec)
• STI Liner OX 1000 C,DRY OX(200+-12A)
• Implant:
• N WELL IMP
P440K15E3T00
WELL IMP注入的位置最深，用以调节井的浓度防止Latch-up效应。
• P CHANNEL IMP
P140K50E2T00
CHANNEL IMP位置较浅，加大LDD之下部位的WELL浓度，使器件工
作时该位置的耗尽层更窄，防止器件PUNCH THROUGH。
1. STI/Trench Isolation 2. Well Definition/Vt Adjust 3. Gate Formation 4. N/PMOS Formation 5. Salicide Formation 6. ILD Layer / Contact CT 7. Metal / VIA 8. Top Meta l Via 9. Passivation
NLDD 114 mask PLDD IMP
P
P
N-Well
16
PLDD 113 mask NLDD IMP
• Poly Re_Oxidation
1015C,21A RTO ( T 1C, THK 0.8 A )
a.Recover ETCH damage to GOX. b. Prevent native-oxide
For thermal budget&good oxide profile around poly gate
✓ Hot carrier effect
N-Well
P-Well
15
LDD1 Definition (Core device, 1.8V)
• NLDD1 Photo (116 layer) – Implant: • N Pocket implant (D130K25E3T30R445) • NLDD implant (A003K80E4T00) – NLDD1 Asher & Wet Strip (21+ SPM)
B160K15E3T00 B025K44E2T00 D170K70E2T00 Mattson: 21 SPM only
N_VT N pthru P WELL
13
Thick/ Thin Gate oxide define
• SAC OX RM
NLH60A (50:1 HF 65sec)
• SAC OX THK-PO PAD (3200+-400 A)
VTP IMP
A130K90E2T00
VT注入，靠近器件表面，调节器件的开启电压
• NWELL Asher
Mattson: 21
• NWELL Wet Strip
SPM only
• NWELL Anneal Precln
MRCAM (SC1+SC2)
• IMPLANT DAMAGE ANNEAL N2(PVD)
for line-end shorting & island missing ✓Composite Spacer (ONO) ✓ PSM method apply on CT layer ✓Cobalt salicide process ✓Low K IMD layer (FSG)
5
Outline
• AA Photo (120 layer) • AA Etch (5800A)
SiN/Ox+Si etch ( 80 +-2degree)
• AA Asher
Mattson ( Rcp: 1 )
• Polymer & Wet Strip NDH15APRRMSC1M ( 100:1 HF 30sec)
•
• STI Pre-CMP THK-PO PAD (3600+-250 A) , SIN (1050+-50)
• AA NIT RM
NLH90AHPO2450A (50:1 HF + H3PO4)
• THIN OXIDE THK-P PAD ( 82+-17)
• STI PAD OX RM
NLH60A (50:1 HF 65 sec)
As buffer layer to release stress, due to SIN and Si different lattice constant
1625Å Nitride 110Å PAD Oxide
•Nitride DEP (w/I scrubber )
1625+- 100A / 760oC
1000RTA010S (1000C; 10sec
P-VT P-pthru
N-Well
P-Well
12
P-Well and Vt_N adjustment
• P_Well Photo (191 layer) • Implant:
• P WELL IMP • N CHANNEL IMP • N_VT IMP • PWELL Asher • PWELL Wet Strip
• GATE2_OX PreCln
NCRRCAM
• GATE2 OX
750 C, 27+-2 A, wet
2000A poly
50Å thick gate oxide Final 70 A
32Å thin gate oxide
Thin gate
Thick gate
14
Poly Gate Definition
018LG Process Introduction (1P6M)
1
Logic Circuit: 能够 展现 精确的模拟特性，
ASIC: 为了满足消费者特定需求而专门设计的半导体 电路
• SOC与IC组成的系统相比，由于SOC能够综合并全盘考虑整个系统 的各种情况，可以在同样的工艺技术条件下实现更高性能的系统指 标 – 若采用IS方法和0.35m工艺设计系统芯片，在相同的系统复杂 度和处理速率下，能够相当于采用0.25 ~ 0.18m工艺制作的IC 所实现的同样系统的性能 – 与采用常规IC方法设计的芯片相比，采用SOC完成同样功能所 需要的晶体管数目可以有数量级的降低
STOP LAYER of STI CMP
7
STI ETCH
ADI = 0.23+-0.02
• SiON DEP(CVD)
FE DARC320 (w/I scrubber )
✓ To reduce SIN reflection and improve PR resolution as an ARC layer
• SAC OX PRECLN
NCR1DH100ARCAM (100:1 HF 240sec)
• SAC OX
110+-7A/ 920oC 45min dry O2
As implant screen oxide
110Å SAC Oxide
11
N-Well and Vt_P adjustment
• N_Well Photo(192 layer)
metal ion
• ZERO Photo
Wafer Mark (For Wafer alignment) • Scrubber Clean (TJBB) • Start oxide RM NLH320A (50:1 HF 350 sec) • Meas: Ox RM THK (25~35A) • AA OX Pre-cln
• GATE Wet Strip
NDH5APRRM (100:1 HF 10sec +SPM)
• THICK GATE OXIDE THK-P PAD (25+-5 A)
• SION RM
NLH5AHP0550A 50:1 HF +H3PO4
• GATE RE-Oxidation PreCln NRCA (SC1+SC2)
• GATE1_OX PreCln
NCR1DH100ARCAM
• GATE1_OX
800C,48A+-4 A, wet
• Dual GATE Photo (131layer) (0.45+/-0.05um)
• GATE1 ETCH
N(NLB75A)
• GATE1 Strip
SPM only
• STI THK-PO PAD ( 3150+-180 A)
• POLY DEPOSITION
POLY 2000A, 620C
• SiON DEP • POLY PHOTO (130layer)
FEDARC320
ADI 0.18+-0.015um
• Poly ARC etch + Poly etch
AEI 0.18+-0.015um
• GATE Asher
Mattson (Rcp: 1)
For ASML stepper system global Wafer alignment
NCR1DH75ARCAM
• ZERO Fully dry etch
• Pad oxide 110+-7A/ 920oC dry O2
(OX 100A + SI 1200+-200 A)
• ZERO Strip
(FEOL: device) (BEOL: interconnect)
6
Wafer Start
• WAFER START & RS CHECK
P type 8 ~ 12 ohm-cm, non-EPI wafer
• Start OX 100A dry
1. PR isolation 2. Prevent the laser mark Si recast 3. Surface cleanness 4. Backside oxidation & trap the
• Anneal(Diff)
1100 C, 2 hrs (Furnace ann.)
• HDP Fill
HDPCVD OX 5.8KA W/O AR sputter
✓ To better shallow trench filling
• Rຫໍສະໝຸດ BaiduA PRECLN
NRCAM
(SC1+ SC2)
•
• HDPCVD OX RTA
1000RTA020S (1000C, 20sec ,N2)
✓ For damage reduction by HDP and HDP ox densification
5800Å HDP 1625Å Nitride 110Å PAD Oxide
9
AA Reverse
• AAR Photo (121 layer)
AAR= (AA-0.4) +0.4) -0.2
• AAR Etch
Stop on SiN
✓ 1. Better surface flatness 2. Improved throughput by OX removing
• AAR Asher
Mattson (Rcp: 1)
• AAR wet strip
NPRRM (SPM only)
AA SiN Pad oxide
P Substrate P Substrate
AA SiN Pad oxide
P Substrate
10
STI CMP & NIT RM
• STI Pre-CMP THK-PO PAD (6100+-225 A) • STI Polish & in-situ Cln (STI_XXXX) ? CMP 是磨到NIT上。
2
VDD
VDD
IN
OUT
Y
A1
A2
CMOS反相器
与非门：Y=A1A2
3
基本电路结构：MOS器件结构
基本电路结构：CMOS
4
0.18um Process Features
✓18LG adopt 27 Photo mask , if include ESD layer ✓AA/Poly/CT/ M1~M5/ V1~V5 use DUV scanner (13 layer) ✓ “ DARC” Cap on Critical layer and Top M6 ✓ Poly & M1~M5 adopt OPC (optical proximity correction)
• AA THK STI-PO PAD (5400+-160 A)
AEI = 0.25+-0.02
16250Å Nitride 110Å PAD Oxide
8
HDP Deposition
• STI PadOX PreCln
NCR1DH75ARCAM (100:1 HF 180sec)
• STI Liner OX 1000 C,DRY OX(200+-12A)
• Implant:
• N WELL IMP
P440K15E3T00
WELL IMP注入的位置最深，用以调节井的浓度防止Latch-up效应。
• P CHANNEL IMP
P140K50E2T00
CHANNEL IMP位置较浅，加大LDD之下部位的WELL浓度，使器件工
作时该位置的耗尽层更窄，防止器件PUNCH THROUGH。
1. STI/Trench Isolation 2. Well Definition/Vt Adjust 3. Gate Formation 4. N/PMOS Formation 5. Salicide Formation 6. ILD Layer / Contact CT 7. Metal / VIA 8. Top Meta l Via 9. Passivation
NLDD 114 mask PLDD IMP
P
P
N-Well
16
PLDD 113 mask NLDD IMP
• Poly Re_Oxidation
1015C,21A RTO ( T 1C, THK 0.8 A )
a.Recover ETCH damage to GOX. b. Prevent native-oxide
For thermal budget&good oxide profile around poly gate