电子元器件ZXCT1050中文资料_数据手册_IC数据表

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ZXCT1009FTA中文资料(Diodes)中文数据手册「EasyDatasheet - 矽搜」

The wide input voltage range of 20V down to as low as 2.5V make it suitable for a range of applications. A minimum operating current of just 4µA, combined with a SOT23 package make it a unique solution for portable battery equipment. The SM8 device offers an alternative package option.
RLIM(MAX) = R OUT [VIN(MIN) - （VDP + V OUT(MAX) )]/V OUT(MAX)
VIN(MIN) =最低电源工作电压 VDP =压差 VOUT(MAX) =最大工作输出电压
该器件的功耗,P PD = IOUT (V IN -V OUT ) W
D 是由下式给出：
应用信息
以下文本描述了如何扩展到的输出电压的负载电流.
VSENSE = V IN - V LOAD VOUT = 0.01 x V SENSE x ROUT 1
E.g.
1A的电流通过一个100mV的输出代表
电压：
重新排列
1 对于溃败给：
ROUT = V OUT /(V SENSE x 0.01) ROUT = 0.1 / (0.1 x 0.01) = 100Ω
芯片中文手册,看全文,戳
应用信息
锂离子电池充电器电路
（续）
上图显示支持的ZXCT1009 Benchmarq bq2954充电管理IC.大多数支持组件为bq2954 的为了清楚而省略. 这种设计还采用了发光二极管FZT789A高电流超ßPNP作为在DC-DC升压开关晶体管升降压转换器和FMMT451作为驱动NPN为 FZT789A.该电路可以被配置充电到4 锂离子电池在1.25A的充电电流.充电可端接在最大电压,可选的最低电流,或最大超时.开关的频率 PWM循环大约为120kHz.

电子元器件ZXCT1010中文资料_数据手册_IC数据表

ZXCT1010Enhanced high-side current monitorDescriptionOrdering informationThe ZXCT1010 is a high side current sense monitor. Using this device eliminates the need to disrupt the ground plane when sensing a load current.t is an enhanced version of the ZXCT1009offering reduced typical output offset and improved accuracy at low sense voltage.The wide input voltage range of 20V down to as low as 2.5V make it suitable for a range of applications. A minimum operating current of just 4␮A, combined with its SOT23-5 package make suitable for portable battery equipment.Features•Low cost, accurate high-side current sensing•Output voltage scaling •Up to 2.5V sense voltage • 2.5V – 20V supply range •300nA typical offset current • 3.5␮A quiescent current •1% typical accuracy •SOT23-5 packageApplications•Battery chargers •Smart battery packs •DC motor control •Over current monitor •Power management•Programmable current sourcePinout informationTypical application circuitDevicePackage Device marking Reel size (inches)Tape width (mm)Quantity per reel ZXCT1010E5TASOT23-5101783000https:///Pin informationAbsolute maximum ratingsOperation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability.Pin Name Description 1N/C Not connection2GND Ground connection3I OUTOutput current, proportional to V IN - V LOAD4V SENSE+Supply voltage5V SENSE-Connection to load/batteryVoltage on any pin (relative to GND pin)-0.6 to 20V (relative to GND)Continuous output current 25mAContinous sense voltageV IN + 0.5V > V SENSE > V IN - 5V Ambient operating temperature range -40 to 85°C Storage temperature -55 to 150°C Package power dissipation T amb = 25°C SOT23-5300mWhttps:///Electrical characteristicsTest conditions T amb = 25°C, V IN = 5V, R OUT = 100⍀NOTES:(a)Includes input offset voltage contribution (b)V SENSE = V IN -V LOAD(c)-20dBm = 63mVp-p into 50⍀Symbol ParameterConditionsLimits UnitMin.Typ.Max.V IN V CC range 2.520V I OUT (a)Output currentV SENSE = 0V 00.310␮A V SENSE = 10mV 85100115␮A V SENSE = 100mV 0.975 1.00 1.025mAV SENSE = 200mV 1.95 2.00 2.05mA V SENSE = 1V9.710.010.3mA I Q Ground pin current V SENSE = 0V3.58␮A V SENSE (b)Sense voltage2500mV I SENSE-V SENSE- input current 100nAAcc AccuracyR SENSE = 0.1⍀ V SENSE = 200mV-2.52.5%Gm Transconductance, I OUT /V SENSE 10000␮A/VBWBandwidthRF P IN = -20dBm (c)V SENSE = 10mV DC 300kHz VSENSE= 100mV DC 2MHzhttps:///Typical characteristicsPower dissipationThe maximum allowable power dissipation of the device Array for normal operation (P max), is a function of the packagejunction to ambient thermal resistance (⍜ja), maximumjunction temperature (Tj max), and ambient temperature(T amb), according to the expression:Pmax = (Tj max – T amb) / ⍜jaThe device power dissipation, P D is given by theexpression:P D=I OUT.(V IN-V OUT) WattsApplications informationThe following lines describe how to scale a load current to an output voltage.V SENSE = V IN - V LOADV OUT = 0.01 x V SENSE x R OUT(1)For example:https:/// A 1A current is to be represented by a 100mV output voltage:1Choose the value of R SENSE to give 50mV > V SENSE > 500mV at full load.For example V SENSE = 100mV at 1.0A. R SENSE = 0.1/1.0 => 0.1⍀.2Choose R OUT to give V OUT = 100mV, when V SENSE = 100mV.Rearranging (1)for R OUT gives:R OUT = V OUT /(V SENSE x 0.01)R OUT = 0.1 / (0.1 x 0.01) = 100⍀Schematic diagramTypical circuit applicationWhere R LOAD represents any load including DC Array motors, a charging battery or further circuitrythat requires monitoring, R SENSE can beselected on specific requirements of accuracy,size and power rating.Li-Ion charger circuitThe figure below shows the ZXCT1010 supporting the Benchmarq bq2954 charge managementIC. Most of the support components for the bq2954 are omitted for clarity. This design also usesthe Zetex FZT789A high current Super-␤ PNP as the switching transistor in the DC-DC step downconverter and the FMMT451 as the drive NPN for the FZT789A. The circuit can be configured to https:///charge up to four Li-Ion cells at a charge current of 1.25A. Charge can be terminated on maximumvoltage, selectable minimum current, or maximum time out. Switching frequency of the PWMloop is approximately 120kHz.Bi-directional current sensingThe ZXCT1010 can be used to measure current bi-Array directionally, if two devices are connected as shownopposite.If the voltage V1 is positive with respect to the voltage V2the lower device will be active, delivering a proportionaloutput current to R OUT. Due to the polarity of the voltageacross Rsense, the upper device will be inactive and will notcontribute to the current delivered to R OUT. When V2 is morepositive than V1, current will be flowing in the oppositedirection, causing the upper device to be active instead.Non-linearity will be apparent at small values of V SENSE dueto offset current contribution. Devices can use separateoutput resistors if the current direction is to be monitoredindependently.https:///Bi-directional transfer functionPCB trace shunt resistor for low cost solution The figure opposite shows output characteristics of the device when using a PCB resistive trace for a low cost solution in replacement for a conventional shunt resistor. The graph shows the linear rise in voltage across the resistor due to the PTC of the material and demonstrates how this rise in resistance value over temperature compensates for the NTC of the device. The figure below shows a PCB layout suggestion.The resistor section is 25mm x 0.25mm giving approximately 150mW using 1oz copper. The data for the normalised graph was obtained using a 1A load current and a 100W output resistor. An electronic version of the PCB layout is available at /isenseLayout shows area of shunt resistor compared to ZSOT23-5package (not actual size).https:///https:///Intentionally left blankPackage outline - SOT23-5Note: Controlling dimensions are in millimeters. Approximate dimensions are provided in inchesDIM MillimetersInchesMin.Max.Min.Max.A 0.90 1.450.03540.0570A10.000.150.000.0059A20.90 1.300.03540.0511b 0.200.500.00780.0196C 0.090.260.00350.0102D 2.70 3.100.10620.1220E 2.20 3.200.08660.1181E1 1.301.800.05110.0708e 0.95 REF 0.0374 REF e1 1.90 REF0.0748 REFL 0.100.600.00390.0236a°0°30°0°30°https:///。

电子元器件ZXCT1080中文资料_数据手册_IC数据表

ZXCT1080High voltage high-side current monitorDescriptionOrdering informationThe ZXCT1080 is a high side current sense monitor with a gain of 10 and a voltage output. Using this device eliminates the need to disrupt the ground plane when sensing a load current.The wide input voltage range of 60V down to as low as 3V make it suitable for a range of applications; including systems operating from industrial 24-28V rails and -48V rails.The separate supply pin (V CC ) allows the device to continue functioning under short circuit conditions, giving an end stop voltage at the output.The ZXCT1080 has an extended ambient operating temperature range of -40°C to 125°C enabling it to be used in a wide range of applications including automotive.Features•3V to 60V continuous high side voltage •Accurate high-side current sensing •-40 to 125°C temperature range •Output voltage scaling x10• 4.5V to 12V V CC range •Low quiescent current:•70µA supply pin •50µA I SENSE+•SOT23-5 package Applications•Industrial applications current measurement •Battery management •Over current monitor •Power management•Automotive current measurementPin connectionsTypical application circuitDevicePackage Part mark Reel size (inches)Tape width (mm)Quantity perreelZXCT1080E5TASOT23-51080783000https://Absolute maximum ratingsContinuous voltage on S- and S+-0.6 and 65V Voltage on all other pins-0.6V and +14VDifferential sense voltage, V SENSE 800mV Operating temperature -40 to 125°C Storage temperature-55 to 150°C Maximum junction temperature 125°CPackage power dissipation300mW * at T A = 25°COperation above the absolute maximum rating may cause device failure. Operation at the absolute maximum ratings, for extended periods, may reduce device reliability.V SENSE is defined as the differential voltage between S+ and S- pins.*Assumes ⍜JA = 420°C/WRecommended operating conditionsPin function tableParameterMin.Max.Units V IN Common-mode sense+ input range 360V V CCSupply voltage range4.512V V SENSE Differential sense input voltage range 00.15V V OUT Output voltage range 0 1.5V T AAmbient temperature range-40125°CPin Name Description1V CC This is the analogue supply and provides power to internal circuitry 2GND Ground pin3OUT Output voltage pin. NMOS source follower with 20µA bias to ground 4S+This is the positive input of the current monitor and has an input range from 60V down to 3V. The current through this pin varies with differential sense voltage5S-This is the negative input of the current monitor and has an input range from 60V down to 3Vhttps://Electrical characteristicsTest conditions T A = 25°C, V IN = 12V, V CC = 5 V, V SENSE (a) = 100mV unless otherwise stated.NOTES:(a)V SENSE = "V SENSE+" - "V SENSE-"(b)The ZXCT1080 operates from a positive power rail and the internal voltage-current converter current flow is unidirectional; these result in the output offset voltage for V SENSE = 0V always being positive.(c)For V SENSE > 10mV, the internal voltage-current converter is fully linear. This enables a true offset to be defined and used. V O(10) is expressed as the variance about an output voltage of 100mV>(d)Temperature dependent measurements are extracted from characterization and simulation results.(e)All Min and Max specifications over full temperature range are guaranteed by design and characterisationSymbol ParameterConditions T A Min (e).Typ.Max (e).Units I CC V CC supply current V CC = 12V, V SENSE (a) = 0V 25°C 4080120µAfull range 145I S+S+ input current V SENSE (a) = 0V25°C 152742µA full range 60I S-S- input current25°C 154080nA V O(0)Zero V SENSE (a) error (b)25°C 035mV V O(10)Output offset voltage (c)V SENSE (a) = 10mV 25°C -25+25mV full range -55+55Gain⌬V OUT /⌬V SENSE (a)V SENSE (a) = 10mV to150mV 25°C 9.91010.1V/V full range9.810.2V OUT TC (d)V OUT variation withtemperature 30ppm/°C Acc Total output error -33%I OH Output source current⌬V OUT = -30mV 1mA I OL Output sink current⌬V OUT = +30mV20µA PSRR V CC supply rejection ratioV CC = 4.5V to 12V 5460dB CMRR Common-mode sense rejection ratio V IN = 60V to 3V 6880dB BW-3dB small signal bandwidthV SENSE (a) (AC) = 10mV PP500kHz https://Typical characteristicsTest conditions unless otherwise stated: T A = 25°C, V CC = 5V, V SENSE+ =12V, V SENSE = 100mVTypical characteristicsTest conditions unless otherwise stated: T A = 25°C, V CC = 5V, V SENSE+ =12V, V SENSE = 100mVTypical characteristicsTest conditions unless otherwise stated: T A = 25°C, V CC = 5V, V SENSE+ =12V, V SENSE = 100mVhttps://Application informationThe ZXCT1080 has been designed to allow it to operate with 5V supply rails while sensing common mode signals up to 60V. This makes it well suited to a wide range of industrial and power supply monitoring applications that require the interface to 5V systems while sensing much higher voltages.To allow this its V CC pin can be used independently of S+.Figure 1 shows the basic configuration of the ZXCT1080.Figure 1Typical configuration of ZXCT1080Load current from the input is drawn through R SENSE developing a voltage V SENSE across the inputs of the ZXCT1080.The internal amplifier forces V SENSE across internal resistance R GT causing a current to flow through MOSFET M1. This current is then converted to a voltage by R G . A ratio of 10:1 between R G and R GT creates the fixed gain of 10. The output is then buffered by the unity gain buffer.The gain equation of the ZXCT1080 is:The maximum recommended differential input voltage, V SENSE , is 150mV; it will howeverwithstand voltages up to 800m ⍀. This can be increased further by the inclusion of a resistor, R LIM ,between S- pin and the load; typical value is of the order of 10k .V OUT I L R SENSE R GRGT---------1×I L R SENSE ×10×==https://Figure 2Protection/error sources for ZXCT1080Capacitor C D provides high frequency transient decoupling when used with R LIM ; typical values are of the order 10pFFor best performance R SENSE should be connected as close to the S+ (and SE NSE ) pins;minimizing any series resistance with R SENSE .When choosing appropriate values for R SENSE a compromise must be reached between in-line signal loss (including potential power dissipation effects) and small signal accuracy.Higher values for R SENSE gives better accuracy at low load currents by reducing the inaccuracies due to internal offsets. For best operation the ZXCT1080 has been designed to operate with V SENSE of the order of 50mV to 150mV.Current monitors' basic configuration is that of a unipolar voltage to current to voltage converter powered from a single supply rail. The internal amplifier at the heart of the current monitor may well have a bipolar offset voltage but the output cannot go negative; this results in current monitors saturating at very low sense voltages.As a result of this phenomenon the ZXCT1080 has been specified to operate in a linear manner over a V SENSE range of 10mV to 150mV range, however it will still be monotonic down to VSENSE of 0V.It is for this very reason that Zetex has specified an input offset voltage (V O(10)) at 10mV. The output voltage for any V SENSE voltage from 10mV to 150mV can be calculated as follows:Alternatively the load current can be expressed as:V OUT V SENSE ()xG V O 10()+=I L V OUT V O 10()–()GxR SENSE------------------------------------------=https://Package details - SOT23-5Note: Controlling dimensions are in millimeters. Approximate dimensions are provided in inchesDIM MillimetersInchesMin.Max.Min.Max.A - 1.00-0.0393A10.010.100.00030.0039A20.840.900.03300.0354b 0.300.450.01180.0177c 0.120.200.00470.0078D 2.90 BSC 0.114 BSCE 2.80 BSC 0.110 BSC E1 1.60 BSC 0.062 BSC e 0.95 BSC 0.0374 BSC e1 1.90 BSC0.0748 BSCL 0.300.500.01180.0196L20.25 BSC 0.010 BSC a°4°12°4°12°https://ZXCT1080DefinitionsProduct changeZetex Semiconductors reserves the right to alter, without notice, specifications, design, price or conditions of supply of any product or service. Customers are solely responsible for obtaining the latest relevant information before placing orders.Applications disclaimerThe circuits in this design/application note are offered as design ideas. It is the responsibility of the user to ensure that the circuit is fit for the user’s application and meets with the user’s requirements. No representation or warranty is given and no liability whatsoever is assumed by Zetex with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Zetex does not assume any legal responsibility or will not be held legally liable (whether in contract,tort (including negligence), breach of statutory duty, restriction or otherwise) for any damages, loss of profit, business, contract,opportunity or consequential loss in the use of these circuit applications, under any circumstances.Life supportZetex products are specifically not authorized for use as critical components in life support devices or systems without the express written approval of the Chief Executive Officer of Zetex Semiconductors plc. As used herein:A. Life support devices or systems are devices or systems which:1.are intended to implant into the bodyor 2.support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in thelabelling can be reasonably expected to result in significant injury to the user.B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected tocause the failure of the life support device or to affect its safety or effectiveness.ReproductionThe product specifications contained in this publication are issued to provide outline information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services concerned.Terms and ConditionsAll products are sold subjects to Zetex’ terms and conditions of sale, and this disclaimer (save in the event of a conflict between the two when the terms of the contract shall prevail) according to region, supplied at the time of order acknowledgement.For the latest information on technology, delivery terms and conditions and prices, please contact your nearest Zetex sales office.Quality of productZetex is an ISO 9001 and TS16949 certified semiconductor manufacturer.To ensure quality of service and products we strongly advise the purchase of parts directly from Zetex Semiconductors or one of our regionally authorized distributors. For a complete listing of authorized distributors please visit: /salesnetworkZetex Semiconductors does not warrant or accept any liability whatsoever in respect of any parts purchased through unauthorized sales channels.ESD (Electrostatic discharge)Semiconductor devices are susceptible to damage by ESD. Suitable precautions should be taken when handling and transporting devices.The possible damage to devices depends on the circumstances of the handling and transporting, and the nature of the device. The extent of damage can vary from immediate functional or parametric malfunction to degradation of function or performance in use over time.Devices suspected of being affected should be replaced.Green complianceZetex Semiconductors is committed to environmental excellence in all aspects of its operations which includes meeting or exceeding regulatory requirements with respect to the use of hazardous substances. Numerous successful programs have been implemented to reduce the use of hazardous substances and/or emissions.All Zetex components are compliant with the RoHS directive, and through this it is supporting its customers in their compliance with WEEE and ELV directives.Product status key:“Preview”Future device intended for production at some point. Samples may be available“Active”Product status recommended for new designs“Last time buy (LTB)”Device will be discontinued and last time buy period and delivery is in effect“Not recommended for new designs”Device is still in production to support existing designs and production“Obsolete”Production has been discontinuedDatasheet status key:“Draft version”This term denotes a very early datasheet version and contains highly provisional information, which may change in any manner without notice.“Provisional version”This term denotes a pre-release datasheet. It provides a clear indication of anticipated performance.However, changes to the test conditions and specifications may occur, at any time and without notice.“Issue”This term denotes an issued datasheet containing finalized specifications. However, changes tospecifications may occur, at any time and without notice.https://。

CTM1050datasheet

CTM1050广州致远电子有限公司工业通讯网络事业部———————————————概述CTM1050是一款带隔离的高速CAN 收发器芯片，该芯片内部集成了所有必需的CAN 隔离及CAN 收、发器件，这些都被集成在不到3平方厘米的芯片上。

芯片的主要功能是将CAN 控制器的逻辑电平转换为CAN 总线的差分电平并且具有DC 2500V 的隔离功能及ESD 保护作用。

和TJA1050一样，该芯片符合ISO 11898标准，因此，它可以和其他遵从ISO 11898标准的CAN 收发器产品互操作。

——————————————产品特性具有隔离、ESD 保护功能；完全符合ISO11898标准的CAN 收发器；通讯速率最高达1Mbps；隔离电压：DC 2500V；电磁辐射EME 极低；电磁抗干扰EMI 性极高；无需外加元件可直接使用；至少可连接110个节点；高低温特性好，能满足工业级产品技术要求。

注：CTM1050T 除具有以上特性外，还具有TVS 管防总线过压。

————————————产品应用 ◆ 汽车电子 ◆ 仪器、仪表 ◆ 石油化工 ◆ 电力监控 ◆ ……—————————————订购信息型号温度范围封装CTM1050 -40℃—+85℃ DIP-8Pin CTM1050T-40℃—+85℃DIP-8Pin————————————————————————————————典型应用图 1 CTM1050应用示例如图1所示为CTM1050的应用示例，该芯片可以连接任何一款CAN 协议控制器，实现CAN 节点的收发与隔离功能。

在以往的设计方案中需要光耦、DC/DC 隔离、CAN 收发器等其他元器件才能实现带隔离的CAN 收发电路，但现在您只需利用一片CTM1050接口芯片就可以实现带隔离的CAN 收发电路，隔离电压可以达到DC 2500V ，其接口简单，使用方便，是嵌入式系统的理想选择！共享修订历史版本日期原因Rev X1 2006/6/8 内部制定初稿Rev 1.0 2006/6/16 第一次发布Rev 1.1 2006/11/11 数据手册升级共享目录销售信息 (2)技术支持 (2)1. 功能简介 (3)2. 引脚信息 (4)2.1 CTM1050引脚信息 (4)3. CTM1050特性参数 (5)3.1 参数列表 (5)3.2 电气特性 (5)3.3 绝缘特性 (6)4. 机械尺寸 (7)4.1 CTM1050机械尺寸 (7)5. 电路连接 (8)5.1 CTM1050电路连接 (8)6. 声明 (9)共享销售信息如果需要购买本产品，请在办公时间（星期一至五上午8:30~11:50；下午1:30~5:30；星期六上午8:30~11:50）拨打电话咨询广州致远电子有限公司。

STA1050中文资料

Power MOS ■ 8-bit 2channels general purpose ADC
Digital Servo
■ Automatic fine gain/balance/offset adjustment for tracking and focus
■ Embedded 16bit servo DSP (33.8688MHz) with programmable sampling rate
2
Pin function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
System description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
fade/
mute/ deemph
+
3/11
A
B
C
D
I/V OFFSET GAIN ADC
E
F
DAC ANALOG PLL filter
1.7Kx32 PRAM DSP
A+C B+D E F 256x16 XRAM
A+C
DECIM. TrackCount 256x16 YRAM
B+D
+ JumpSpeed
2/11
元器件交易网
STA1050
1
Block diagram
Figure 1. Block diagram
master clock

TJA1050中文资料_数据手册_参数

2003年10月22日 4飞利浦半导体产品SPECI FI CATION高速CAN收发器 TJA1050功能说明 TJA1050是CAN协议之间的接口控制器和物理总线.它主要用于使用波特率的高速汽车应用 60 KBAUD到1 MBAUD.它提供差分传输总线能力和差分接收器能力 CAN协议控制器.它完全兼容 “ISO 11898”标准.限流电路保护发射机输出阶段由意外短路造成的损坏虽然电力正常或负电源电压在这种故障状态下功耗会增加.热保护电路可保护IC免受损坏通过关闭发射机如果结温超过约165的值 C.因为发射机消耗大部分功率和功率 IC的耗散和温度降低.所有其他 IC功能继续运行.发射机关闭状态当引脚TXD变为高电平时复位.热保护当总线短路时尤其需要电路. CANH和CANL引脚不受汽车的保护电瞬变（根据 “ISO 7637”;参见图4）.控制引脚S允许选择两种工作模式：高速模式或静音模式.高速模式是正常的操作模式，并且是通过将引脚S连接到地面来选择.这是默认设置模式，如果引脚S未连接.但是，要确保EMI在仅使用高速应用的应用中表现出色模式，建议将引脚S连接到地面.在静音模式下，发射器被禁用.所有其他 IC功能继续运行.无声模式是通过连接引脚S到V CC进行选择，可用于防止网络通信被阻塞，到期到一个失控的CAN控制器. “TXD主导超时”定时器电路阻止总线线路被驱动到永久主导状态（阻塞）所有网络通信）如果引脚TXD被强制由硬件和/或软件永久为低应用失败.定时器由否定触发边沿TXD引脚.如果持续低电平的话 TXD引脚超过内部定时器值，发送器为残疾，驾驶巴士进入隐性状态.定时器由引脚TXD上的上升沿复位.表格1 CAN收发器的功能表; X =不在乎 V CC TXD小号 CANH CANL总线状态 RXD 4.75 V至5.25 V低低（或 FL替罪羊）高低优势低 4.75 V至5.25 V X高 0.5V CC 0.5V CC隐性高 4.75 V至5.25 V高（飞利浦半导体产品SPECI FI CATION高速CAN收发器 TJA1050手册，全页面宽度 50 80 0 020三十 10 MGT231 40 F（MHZ） 20 40 60一个（D B μV）图9高达50 MHZ的典型电磁发射（峰值幅度测量）.数据速率为500千比特/秒.手册，全页面宽度 10 80 0 04 6 2 MGT233 8 F（MHZ） 20 40 60一个（D B μV）图10高达10 MHZ的典型电磁发射（峰值幅度测量和峰值包络振幅）.数据速率为500千比特/秒. 图1方框图.钉扎符号销描述 TXD 1传输数据输入;读入数据从CAN控制器到总线线路司机 GND 2地面 V CC 3电源电压 RXD 4接收数据输出;读出来从公交线路到公交车的数据 CAN控制器 V REF五参考电压输出 CANL 6低级CAN总线 CANH 7高级CAN总线小号 8选择高速模式的输入或静音模式手册，HALFPAGE 1 2 3 4 8 7 6五 MGS375 TJA1050T小号 CANH GND CANL VREF RXD VCC TXD图2引脚配置

电子元器件zdt1053中文资料_数据手册_IC数据表

Cobo ton toff
21
30
pF
VCB=10V, f=1MHz
90
ns
IC=2A, IB=20mA, VCC=50V
750
ns
IC=2A, IB=±20mA, VCC=50V
*Measured under pulsed conditions. Pulse width=300µs. Duty cycle ≤2%
55.6
°C/ W
45.5
°C/ W
* The power which can be dissipated assuming the device is mounted in a typical manner on a PCB with copper equal to 2 inches square.
Cobo ton toff
21
30
pF
VCB=10V, f=1MHz
90
ns
IC=2A, IB=20mA, VCC=50V
750
ns
IC=2A, IB=±20mA, VCC=50V
*Measured under pulsed conditions. Pulse width=300µs. Duty cycle ≤2%
1200
150
220
30
50
15
IC=10mA, VCE=2V* IC=1A, VCE=2V* IC=2A, VCE=2V* IC=5A, VCE=2V* IC=10A, VCE=2V*
140
MHz
IC=50mA, VCE=10V
f=100MHz
Output Capacitance Switching Times

tja1050中文资料

1 接口电路设计中的关键问题1.1光电隔离电路光电隔离电路虽然能增强系统的抗干扰能力，但也会增加CAN总线有效回路信号的传输延迟时间，导致通信速率或距离减少。

82C250等型号的CAN收发器本身具备瞬间抗干扰、降低射频干扰(RFI)以及实现热防护的能力，其具有的电流限制电路还提供了对总线的进一步保护功能。

因此，如果现场传输距离近、电磁干扰小，可以不采用光电隔离，以使系统达到最大的通信速率或距离，并且可以简化接口电路。

如果现场环境需要光电隔离，应选用高速光电隔离器件，以减少CAN总线有效回路信号的传输延迟时间，如高速光电耦合器6N137，传输延迟时间短，典型值仅为48 ns，已接近TTL电路传输延迟时间的水平。

1.2 电源隔离光电隔离器件两侧所用电源Vdd与Vcc必须完全隔离，否则，光电隔离将失去应有的作用。

电源的隔离可通过小功率DC/DC电源隔离模块实现，如外形尺寸为DIP-14标准脚位的5 V 双路隔离输出的小功率DC/DC模块。

1.3 上拉电阻图1中的CAN收发器82C250的发送数据输入端TXD与光电耦合器6N137的输出端OUT相连，注意TXD必须同时接上拉电阻R3。

一方面，R3保证6N137中的光敏三极管导通时输出低电平，截止时输出高电平；另一方面，这也是CAN 总线的要求。

具体而言，82C250的TXD端的状态决定着高、低电平CAN 电压输入/输出端CANH、CANL的状态(见表1)。

CAN总线规定，总线在空闲期间应呈隐性，即CAN 网络中节点的缺省状态是隐性，这要求82C25O 的TXD端的缺省状态为逻辑1(高电平)。

为此，必须通过R3确保在不发送数据或出现异常情况时，TXD端的状态为逻辑1(高电平)。

1.4总线阻抗匹配CAN总线的末端必须连接2个120Ω的电阻，它们对总线阻抗匹配有着重要的作用，不可省略。

否则，将大大降低总线数据通信时的可靠性和抗干扰性，甚至有可能导致无法通信。

1.5 其它抗干扰措施为提高接口电路的抗干扰能力，还可考虑以下措施：(1)在82C25O的CANH、CANL端与地之间并联2个30 pF的小电容，以滤除总线上的高频干扰，防止电磁辐射。

tja1050中文资料

tja1050中文资料嵌入式架构有多重要？要做到嵌入式应用的代码逻辑清晰，且避免重复的造轮子，没有好的应用架构怎么行?如果没有好的架构，移植将会是一件很痛苦的事情。

如果没有好的架构，复用是最大的难题，没法更大限度的复用原有的代码。

如果没有好的架构，一旦驱动改了，所有的地方都要改，费时费力且很容易出错。

如果没有好的架构，应用层中穿插着硬件驱动层的代码，看着会是一片混乱，逻辑不清，代码维护起来会很困难。

接下来嵌入式ARM便和大家分享一下，嵌入式架构那些事儿……01嵌入式系统的基本架构嵌入式系统一般由软件和硬件两个部分组成，基中嵌入式处理器、存储器和外部设备构成整个系统的硬件基础。

嵌入式系统的软件部分可以分为三个层次，分别是系统软件、支撑软件和应用软件，其中系统软件和支撑软件是基础，应用软件是最能体现整个嵌入式系统的特点和功能部分。

硬件架构嵌入式系统的核心部件是各种类型的嵌入式处理器：（1）嵌入式微处理器：在功能上跟普通微处理器基本一致，但是它具有体积小、功耗低、成本低及可靠性高的优点。

（2）嵌入式微控制器：双称单片机，一般以某一种微处理器内核为核心，整个计算机系统都集成到一块芯片中，与嵌入式微处理器相比，最大特点是单片化。

（3）嵌入式数字信号处理器：一种专门用于信号处理的处理器，DSP （Digital Signal Processor）是芯片内部采用程序和数据分开的结构，具有专门的硬件乘法器，广泛采用流水线操作，提供特殊的DSP 指令。

（4）嵌入式片上系统：一种在一块芯片上集成很多功能模块的复杂系统，在大量生产时，生产成本也远远低于单片部件组成的电路板系统。

软件架构大多数人参与的是嵌入式软件设计，更多的是接触的是上层软件系统部分，可以分为两大类型嵌入式软件应用工程师以及嵌入式驱动工程师。

前者主要负责linux APP 设计，负责应用层业务开发，主要具备如下几个专业技能：1.熟悉网络编程、TCP/IP协议、IIC、SPI协议2.熟悉多线程管理、进程间通信、文件IO操作3.了解基本的shell编程4.熟悉数据库操作5.了解QT或者Android后者负责驱动开发，更加涉及底层。

ZXCTN 9004(V2.08.31)分组传送产品硬件描述

2 设备子架 ............................................................................................2-1
2.1 子架结构 ............................................................................................................2-1 2.2 风扇插箱 ............................................................................................................2-2 2.3 子架板位资源 .....................................................................................................2-3
3.5.1 单板功能 ..................................................................................................3-4 3.5.2 单板原理 ..................................................................................................3-5 3.5.3 面板说明 ..................................................................................................3-6 3.5.4 指示灯状态 ...............................................................................................3-7 3.5.5 告警、性能、事件 ....................................................................................3-8 3.6 P90S1-2XGE-XFP ............................................................................................ 3-11 3.6.1 单板功能 ................................................................................................ 3-11 3.6.2 单板原理 ................................................................................................ 3-11 3.6.3 面板说明 ................................................................................................ 3-13 3.6.4 指示灯状态 ............................................................................................. 3-13 3.6.5 告警、性能、事件 .................................................................................. 3-13 3.7 P90S1-4XGE-XFP ............................................................................................ 3-15 3.7.1 单板功能 ................................................................................................ 3-15 3.7.2 单板原理 ................................................................................................ 3-16

ISO1050中文资料_数据手册_参数

器件型号 ISO1050
器件信息(1)
封装
封装尺寸（标称值）
SOP (8)
9.50mm × 6.57mm
SOIC (16)
10.30mm x 7.50mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
简化电路原理图
CANH RXD
CANL
TXD
1பைடு நூலகம்
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLLS983
ISO1050
ZHCS321I – JUNE 2009 – REVISED JANUARY 2015

目录
1 特性.......................................................................... 1 2 应用.......................................................................... 1 3 说明.......................................................................... 1 4 修订历史记录 ........................................................... 2 5 Pin Configuration and Functions ......................... 5 6 Specifications......................................................... 6

CTM1050

CTM1050———————————————概述CTM1050是一款带隔离的高速CAN 收发器芯片，该芯片内部集成了所有必需的CAN 隔离及CAN 收、发器件，这些都被集成在不到3平方厘米的芯片上。

芯片的主要功能是将CAN 控制器的逻辑电平转换为CAN 总线的差分电平并且具有DC 2500V 的隔离功能及ESD 保护作用。

该芯片符合ISO 11898标准，因此，它可以和其他遵从ISO 11898标准的CAN 收发器产品互操作。

注：CTM1050T 除具有以上特性外，还具有TVS 管防总线过压。

在以往的设计方案中需要光耦、DC/DC 隔离、CAN 收发器等其他元器件才能实现带隔离的CAN 收发电路，但现在您只需利用一片CTM1050接口芯片就可以实现带隔离的CAN 收发电路，隔离电压可以达到DC 2500V ，其接口简单，使用方便，是嵌入式系统的理想选择！修订历史版本日期原因Rev X1 2006/6/8 内部制定初稿Rev 1.0 2006/6/16 第一次发布Rev 1.1 2006/11/11 数据手册升级Rev 1.20 2006/06/30 数据手册模版升级目录1. 功能简介 (2)2. 引脚信息 (3)2.1 CTM1050引脚信息 (3)3. CTM1050特性参数 (4)3.1 参数列表 (4)3.2 电气特性 (4)3.3 绝缘特性 (5)4. 机械尺寸 (6)4.1 CTM1050机械尺寸 (6)5. 电路连接 (7)5.1 CTM1050电路连接 (7)5.2 网络拓扑结构 (7)6. 声明 (8)7. 销售与服务网络 (1)1.功能简介CTM1050芯片采用全灌封工艺，内部集成CAN-bus所必须的收发电路，完全电气隔离电路，隔离电压（DC2500V）。

tja1050中文资料

tja1050中文资料集成电路（英语：integrated circuit，缩写作IC），或称微电路（microcircuit）、微芯片（microchip）、晶片/芯片（chip）在电子学中是一种把电路（主要包括半导体设备，也包括被动组件等）小型化的方式，并时常制造在半导体晶圆表面上。

晶体管发明并大量生产之后，各式固态半导体组件如二极管、晶体管等大量使用，取代了真空管在电路中的功能与角色。

到了20世纪中后期半导体制造技术进步，使得集成电路成为可能。

相对于手工组装电路使用个别的分立电子组件，集成电路可以把很大数量的微晶体管集成到一个小芯片，是一个巨大的进步。

集成电路的规模生产能力，可靠性，电路设计的模块化方法确保了快速采用标准化集成电路代替了设计使用离散晶体管。

集成电路对于离散晶体管有两个主要优势：成本和性能。

成本低是由于芯片把所有的组件通过照相平版技术，作为一个单位印刷，而不是在一个时间只制作一个晶体管。

性能高是由于组件快速开关，消耗更低能量，因为组件很小且彼此靠近。

2006年，芯片面积从几平方毫米到350 mm²，每mm²可以达到一百万个晶体管。

第一个集成电路雏形是由杰克·基尔比于1958年完成的，其中包括一个双极性晶体管，三个电阻和一个电容器，相较于现今科技的尺寸来讲，体积相当庞大。

电子显微镜下碳纳米管微计算机芯片体的场效应画面根据一个芯片上集成的微电子器件的数量，集成电路可以分为以下几类：小型集成电路（SSI英文全名为Small Scale Integration）：逻辑门10个以下或晶体管100个以下。

中型集成电路（MSI英文全名为Medium Scale Integration）：逻辑门11~100个或晶体管101~1k个。

大规模集成电路（LSI英文全名为Large Scale Integration）：逻辑门101~1k个或晶体管1,001~10k个。

ZXCT1009FTA中文资料(diodeszetex)中文数据手册「EasyDatasheet - 矽搜」

ZXCT1009
典型特征（续）
原理图 ,示意图
引脚说明引脚名称
Vsense+ VsenseIout
引脚功能电源电压
连接加载/电池输出电流,正比于V
SOT23 包装后缀 - ˚F
接线图
in -Vload SM8 包装后缀 - T8
顶视图
顶视图
4
第 10期 - 2007年 7月
芯片中文手册,看全文,戳
REEL SIZE 7”
7”
TAPE WIDTH 8mm
12mm
单位数量
REEL 3000台
1000台
PARTMARKING 109
ZXCT1009
包
SOT23 SM8
第 10期 - 2007年 7月 1
芯片中文手册,看全文,戳
ZXCT1009
绝对最大额定值
任何引脚电压
连续输出电流,I 连续检测电压,V 工作温度,T
10000 0
300 2
Max. 20 15 120 1.025 2.05 10.2 2500 100
2.5
UNIT
V µA µA mA mA mA mV nA
% µA/V
kHz MHz
第 10期 - 2007年 7月 2
芯片中文手册,看全文,戳
典型特征
ZXCT1009
10m V = 5V
特征成本低,精确高端电流检测
输出电压调整
高达2.5V检测电压 2.5V - 20V电源电压范围 4μA静态电流 1％典型精度 SOT23和SM8包
应用
电池充电器智能电池组直流电机控制过电流监控器电源管理电平转换可编程电流源
应用电路

恩智浦半导体 i.MX RT1050 数据手册说明书

恩智浦半导体数据手册：技术数据文件编号：IMXRT1050CEC第1.3版，2019年3月恩智浦保留根据需要更改生产规格细节的权利，以改进其产品设计。

MIMXRT1051DVL6AMIMXRT1051DVL6BMIMXRT1051DVJ6BMIMXRT1052DVL6AMIMXRT1052DVL6BMIMXRT1052DVJ6B适用于消费类产品的i.MXRT1050跨界处理器封装信息塑料封装196引脚MAPBGA，10 x 10 mm，0.65 mm间距196引脚MAPBGA，12 x 12 mm，0.8 mm间距订购信息参见第5页的表11 i.MX RT1050简介i.MX RT1050处理器属于全新的处理器系列，采用恩智浦先进的Arm®Cortex®-M7内核，运行速度高达600 MHz，可提供高CPU性能和实时响应。

i.MX RT1050处理器具有512 KB片内RAM，可灵活配置为TCM或通用片内RAM。

i.MX RT1050集成了先进的电源管理模块、DCDC和LDO，可降低外部电源的复杂性并简化上下电序列。

i.MXRT1050还提供各类存储器接口，包括SDRAM、RAW NAND、闪存、NOR闪存、SD/eMMC、四通道SPI；以及各类外设连接接口，包括WLAN、Bluetooth™、GPS、显示器和摄像头传感器。

i.MXRT1050还提供丰富的音频和视频功能，包括LCD显示器、基本2D图形、摄像头接口、SPDIF和I2S音频接口。

1. i.MX RT1050简介 (1)1.1. 特性 (2)1.2. 订购信息 (5)2. 架构概述 (8)2.1. 功能框图 (8)3. 模块列表 (9)3.1. 特殊信号考量 (15)3.2. 未使用模拟接口的推荐连接 (16)4. 电气特性 (18)4.1. 芯片级条件 (18)4.2. 系统电源和时钟 (25)4.3. I/O参数 (30)4.4. 系统模块 (36)4.5. 外部存储器接口 (41)4.6. 显示和图形 (51)4.7. 音频 (54)4.8. 模拟 (57)4.9. 通信接口 (64)4.10. 定时器 (77)5. 启动模式配置 (79)5.1. 启动模式配置引脚 (79)5.2. 启动设备接口分配 (79)6. 封装信息和触点分配 (84)6.1. 10 x 10 mm封装信息 (84)6.2. 12 x 12 mm封装信息 (96)7. 修订记录 (108)i.MX RT1050简介i.MX RT1050配备模拟接口，例如ADC、ACMP和TSC。

CC1050PWG3中文资料

CC1050Single Chip Very Low Power RF Transmitter Applications•Very low power UHF wireless data transmitters•315 / 433 / 868 and 915 MHz ISM/SRD band systems •RKE – Remote Keyless Entry •Home automation•Wireless alarm and security systems •AMR – Automatic Meter Reading •Low power telemetry•Game Controllers and advanced toysProduct DescriptionCC1050 is a true single-chip UHF trans-mitter designed for very low power and very low voltage wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands at 315, 433, 868 and 915 MHz, but can easily be programmed for operation at other frequencies in the 300-1000 MHz range.The main operating parameters of CC1050 can be programmed via an easy-to-interface serial bus, thus making CC1050 a very flexible and easy to use transmitter. In a typical system CC1050 will be used together with a microcontroller and a few external passive components. CC1050 is based on Chipcon’s SmartRF®technology in 0.35 µm CMOS.Features•True single chip UHF RF transmitter •Very low current consumption •Frequency range 300 – 1000 MHz •Programmable output power –20 to12 dBm•Small size (TSSOP-24 package)•Low supply voltage (2.1 V to 3.6 V) •Very few external components required •Single-ended antenna connection •FSK data rate up to 76.8 kBaud •Complies with EN 300 220 and FCC CFR47 part 15•Programmable frequency in 250 Hz steps makes crystal temperature driftcompensation possible without TCXO •Suitable for frequency hopping protocols•Development Kit available•Easy-to-use software for generating the CC1050 configuration dataTable of ContentsAbsolute Maximum Ratings (4)Operating Conditions (4)Electrical Specifications (4)Pin Assignment (7)Application Circuit (9)Configuration Overview (10)Configuration Software (11)3-wire Serial Configuration Interface (12)Microcontroller Interface (14)Signal interface (15)Frequency programming (17)VCO (17)VCO and PLL self-calibration (17)VCO current control (21)Power management (21)Output Matching (24)Output power programming (25)Crystal oscillator (26)Optional LC Filter (27)System Considerations and Guidelines (28)PCB Layout Recommendations (29)Antenna Considerations (29)Configuration registers (30)Package Description (TSSOP-24) (38)Soldering Information (38)Plastic Tube Specification (38)Carrier Tape and Reel Specification (38)Ordering Information (39)General Information (39)Address Information (40)Absolute Maximum RatingsParameter Min.Max. Units ConditionSupply voltage, VDD -0.3 5.0 VVoltage on any pin -0.3 VDD+0.3,max 5.0V Input RF level 10 dBmStorage temperature range -50 150 °CReflow soldering temperature 260 °C T = 10 sUnder no circumstances the absolute maximum ratings given above should be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device.Caution! ESD sensitive device.Precaution should be used when handlingthe device in order to prevent permanentdamage.Operating ConditionsParameter Min. Typ. Max. Unit Condition / NoteRF Frequency Range 300 1000 MHz Programmable in steps of 250 Hz Operating ambient temperature range -40 85 °CSupply voltage 2.1 3.0 3.6 V Note: The same supply voltageshould be used for digital (DVDD)and analogue (AVDD) power. Electrical SpecificationsTc = 25°C, VDD = 3.0 V if nothing else statedParameter Min. Typ. Max. Unit Condition / Note Transmit SectionTransmit data rate 0.6 76.8 kBaud NRZ or Manchester encoding.76.8 kBaud equals 76.8 kbit/susing NRZ coding. See page 15. Binary FSK frequency separation 0 65 kHz The frequency separation isprogrammable in 250 Hz steps.65 kHz is the maximumguaranteed separation at 1 MHzreference frequency. Largerseparations can be achieved athigher reference frequencies. Output power433 MHz 868 MHz -20-20128dBmdBmDelivered to 50 Ω load.The output power isprogrammable.RF output impedance 433/868 MHz 110 / 70 ΩTransmit mode. For matchingdetails see p.24.Parameter Min. Typ. Max. Unit Condition / NoteSpurious emission -36 dBm Complies with EN 300 220 Harmonics -20 dBc An external LC should be used toreduce harmonics emission tocomply with SRD requirements.See p.27.Frequency SynthesiserSectionCrystal Oscillator Frequency 3 16 MHz Crystal frequency can be 3-4, 6-8or 9-16 MHz. Recommendedfrequencies are 3.6864, 7.3728,11.0592 and 14.7456. See page26 for details.Crystal frequency accuracy requirement ± 50± 25ppm433MHz868 MHzThe crystal frequency accuracyand drift (ageing andtemperature dependency) willdetermine the frequency accuracyof the transmitted signal.Crystal operation Parallel C3 and C4 are loadingcapacitors, see page 26Crystal load capacitance 121212 221616303016pFpFpF3-8 MHz, 22 pF recommended6-8 MHz, 16 pF recommended9-16 MHz, 16 pF recommendedCrystal oscillator start-up time 41.52 msmsms3.6864 MHz, 16 pF load7.3728 MHz, 16 pF load16 MHz, 16 pF loadOutput signal phase noise -80 dBc/Hz At 100 kHz offset from carrier PLL lock time 200 µs Up to 1 MHz frequency stepPLL turn-on time, crystal oscillatoron in power down mode250 µs Crystal oscillator runningDigital Inputs/OutputsLogic "0" input voltage 00.3*VDD VLogic "1" input voltage 0.7*VDD VDD VLogic "0" output voltage 0 0.4 V Output current -2.5 mA,3.0 V supply voltageLogic "1" output voltage 2.5 VDD V Output current 2.5 mA,3.0 V supply voltageLogic "0" input current NA -1 µA Input signal equals GNDLogic "1" input current NA 1 µA Input signal equals VDDDI setup time 20 ns TX mode, minimum time DI mustbe ready before the positive edgeof DCLKDI hold time 10 ns TX mode, minimum time DI mustbe held after the positive edge ofDCLKParameter Min. Typ. Max. Unit Condition / Note Serial interface (PCLK, PDATA andPALE) timing specificationSee Table 2 page 13 Current ConsumptionPower Down mode 0.2 1 µA Oscillator core offCurrent Consumption,transmit mode 433/868 MHz:P=0.01mW (-20dBm) P=0.3mW (-5dBm)P=1mW (0dBm)P=3mW (5dBm)P=6mW (8dBm)P=16mW (12dBm)5.5/8.07.3/10.09.1/14.213.3/17.715.9/24.923.3/NAmAmAmAmAmAmAThe output power is delivered to a50Ω loadCurrent Consumption, crystal osc. Current Consumption, crystal osc. and biasCurrent Consumption, crystal osc., bias and synthesiser 30801054004.05.5µAµAµAµAmAmA3-8 MHz, 16 pF load9-14 MHz, 12 pF load14-16 MHz, 16 pF load< 500 MHz> 500 MHzPin AssignmentPin no. Pin name Pin type Description1 AVDD Power (A) Power supply (3 V) for analog modules (PA)2 AGND Ground (A) Ground connection (0 V) for analog modules (PA)3 AGND Ground (A) Ground connection (0 V) for analog modules (PA)4 AGND Ground (A) Ground connection (0 V) for analog modules (VCO and prescaler)5 L1 Analog inputConnection no 1 for external VCO tank inductor 6 L2 Analog input Connection no 2 for external VCO tank inductor7 AVDDPower (A) Power supply (3 V) for analog modules (VCO and prescaler) 8CHP_OUTAnalog outputCharge pump current output when external loop filter is used The pin can also be used as PLL Lock indicator. Output is high when PLL is in lock.9 R_BIASAnalog output Connection for external precision bias resistor (82 k Ω, ± 1%) 10 AGND Ground (A) Ground connection (0 V) for analog modules (backplane) 11 AVDD Power (A) Power supply (3 V) for analog modules (general) 12 AGND Ground (A) Ground connection (0 V) for analog modules (general) 13 XOSC_Q2 Analog output Crystal, pin 2 14 XOSC_Q1 Analog input Crystal, pin 1, or external clock input 15 AGND Ground (A) Ground connection (0 V) for analog modules (guard) 16 DGND Ground (D) Ground connection (0 V) for digital modules (substrate) 17 DVDD Power (D) Power supply (3 V) for digital modules 18 DGND Ground (D) Ground connection (0 V) for digital modules 19 DI Digital input Data input in transmit mode 20 DCLK Digital output Clock for data in transmit mode 21 PCLKDigital input Programming clock for 3-wire bus 22 PDATA Digital input/output Programming data for 3-wire bus. Programming data input for write operation, programming data output for read operation 23 PALE Digital input Programming address latch enable for 3-wire bus 24 RF_OUT RF output RF signal output to antennaA=Analog, D=Digital(Top View)AGND AGNDAGNDL1L2AVDDAGNDPALEPDATA PCLKDCLKDIDGNDDVDDDGNDAGND XOSC_Q1AGNDXOSC_Q2RF_OUT AVDDCHP_OUTR_BIASAVDDCircuit DescriptionFigure 1. Simplified block diagramA simplified block diagram of CC1050 is shown in Figure 1. Only signal pins are shown.The voltage controlled oscillator (VCO) output signal is fed directly to the power amplifier (PA). The RF output is frequency shift keyed (FSK) by the digital bit stream fed to the pin DI. The single ended PA makes the antenna interface and matching very easy. The frequency synthesiser generates the local oscillator signal which is fed to the PA in transmit mode. The frequency synthesiser consists of a crystal oscillator (OSC), phase detector (PD), charge pump (CHARGE PUMP), VCO, and frequency dividers (/R and /N). An external crystal must be connected to XOSC, and only an external inductor is required for the VCO.The 3-wire digital serial interface (CONTROL) is used for configuration.DCLKDICHP_OUTRF_OUTXOSC_Q1R_BIASApplication CircuitVery few external components arerequired for the operation of CC1050. A typical application circuit is shown Figure 2. Component values are shown in Table 1.Output matchingC1, C2 and L2 are used to match the transmitter to 50 Ω. See Output Matching p.24 for details.VCO inductorThe VCO is completely integrated except for the inductor L1. For further details see p. 17.Component values for the matching network and VCO inductor are easily calculated using the SmartRF® Studio software. Crystal oscillatorC3 and C4 are the loading capacitors for the crystal. See page 26 for details. Additional filteringAdditional filtering (e.g. a low pass LC-filter) may be used in order to reduce the harmonic emission. See also Optional LC Filter p.27 for further information.Power supply decoupling and filtering Power supply decoupling and filtering must be used (not shown in the application circuit). The placement and size of the decoupling capacitors and the power supply filtering are very important to achieve the optimum performance. Chipcon provides a reference design (CC1050EB) that should be followed very closely.Figure 2. Typical CC1050application circuitItem 315 MHz 433 MHz 868 MHz 915 MHzC1 5.6 pF, 5%, C0G, 0603 12 pF, 5%, C0G, 0603 4.7 pF, 5%, C0G, 0603 4.7 pF, 5%, C0G, 0603 C2 8.2 pF, 5%, C0G, 0603 6.8 pF, 5%, C0G, 0603 5.6 pF, 5%, C0G, 0603 5.6 pF, 5%, C0G, 0603 C3* 15 pF, 5%, C0G, 0603 15 pF, 5%, C0G, 0603 15 pF, 5%, C0G, 0603 15 pF, 5%, C0G, 0603 C4* 15 pF, 5%, C0G, 0603 15 pF, 5%, C0G, 0603 15 pF, 5%, C0G, 0603 15 pF, 5%, C0G, 0603 L1 56 nH, 5%, 0603 33 nH, 5%, 0603 5.6 nH, 5%, 0603 5.6 nH, 5%, 0603L2 20 nH, 10%, 0805 6.2 nH, 10%, 0805 2.5 nH, 10%, 0805 2.5 nH, 10%, 0805R1 82 kΩ, 1%, 0603 82 kΩ, 1%, 0603 82 kΩ, 1%, 0603 82 kΩ, 1%, 0603XTAL 14.7456 MHz crystal,16 pF load 14.7456 MHz crystal,16 pF load14.7456 MHz crystal,16 pF load14.7456 MHz crystal,16 pF loadNotes:Items shaded are different for different frequencies.Component values for 868 and 915 MHz are equal.*) C3 and C4 will depend on the crystal load capacitance, see page 26.Table 1. Bill of materials for the application circuit Configuration OverviewCC1050 can be configured to achieve the best performance for different applications. Through the programmable configuration registers the following key parameters can be programmed:•Transmit mode / power-down / power-up mode•RF output power• Frequency synthesiser key parameters: RF output frequency, FSKfrequency separation (deviation), crystal oscillator reference frequency •Crystal oscillator power-up / power down• Data rate and data format (NRZ, Manchester coded or UART interface) •Synthesiser lock indicator mode •Modulation spectrum shapingConfiguration SoftwareChipcon provides users of CC1050 with a software program, SmartRF® Studio (Windows interface) that generates all necessary CC1050 configuration data based on the user's selections of various parameters. These hexadecimal numbers will then be the necessary input to the microcontroller for the configuration of CC1050. In addition the program will provide the user with the component values needed for the output matching circuit and the VCO inductor.Figure 3 shows the user interface of the CC1050 configuration software.Figure 3. SmartRF® Studio user interface3-wire Serial Configuration InterfaceCC1050 is configured via a simple 3-wire interface (PDATA, PCLK and PALE). There are 19 8-bit configuration registers, each addressed by a 7-bit address. A Read/Write bit initiates a read or write operation. A full configuration of CC1050 requires sending 19 data frames of 16 bits each (7 address bits, R/W bit and 8 data bits). The time needed for a full configuration depend on the PCLK frequency. With a PCLK frequency of 10 MHz the full configuration is done in less than 30 µs. Setting the device in power down mode requires sending one frame only and will in this case take less than 2 µs. All registers are also readable.In each write-cycle 16 bits are sent on the PDATA-line. The seven most significant bits of each data frame (A6:0) are the address-bits. A6 is the MSB (Most Significant Bit) of the address and is sent as the first bit. The next bit is the R/W bit (high for write, low for read). During address and R/W bit transfer the PALE (Program Address Latch Enable) must be kept low. The 8 data-bits are then transferred (D7:0). See Figure 4.The timing for the programming is also shown in Figure 4 with reference to Table 2. The clocking of the data on PDATA is done on the negative edge of PCLK. When the last bit, D0, of the 8 data-bits has been loaded, the data word is loaded in the internal configuration register.The configuration data is stored in internal RAM and is valid after power-down mode, but not when the power-supply is turned off. The registers can be programmed in any order.The configuration registers can also be read by the microcontroller via the same configuration interface. The seven address bits are sent first, then the R/W bit set low to initiate the data read-back. CC1050 then returns the data from the addressed register. PDATA is in this case used as an output and must be tri-stated (or set high n the case of an open collector pin) by the microcontroller during the data read-back (D7:0). The read operation is illustrated in Figure 5.Figure 4. Configuration registers write operationPCLKPDATA PALET TFigure 5. Configuration registers read operationParameter SymbolMin Max UnitsConditionsPCLK, clock frequencyF CLOCK- 10 MHz PCLK low pulse durationT CL,min50nsThe minimum time PCLK must be low.PCLK high pulse durationT CH,min 50 ns The minimum time PCLK must be high.PALE setup timeT SA10 - ns The minimum time PALE must be low before negative edge of PCLK.PALE hold timeT HA 10 - ns The minimum time PALE must be held low after the positive edge of PCLK.PDATA setup time T SD 10 - ns The minimum time data on PDATA must be ready before the negative edge of PCLK.PDATA hold timeT HD 10 - ns The minimum time data must be held at PDATA, after the negative edge of PCLK.Rise time T rise 100 ns The maximum rise time for PCLK and PALEFall timeT fall100nsThe maximum fall time for PCLK and PALENote: The set-up- and hold-times refer to 50% of VDD.Table 2. Serial interface, timing specificationPCLKPALEPDATAMicrocontroller InterfaceUsed in a typical system, CC1050 will interface to a microcontroller. This microcontroller must be able to:• Program CC1050 into different modes via the 3-wire serial configurationinterface (PDATA, PCLK and PALE). •Interface to the synchronous data signal interface (DI and DCLK). •Optionally the microcontroller can do data encoding / decoding. •Optionally the microcontroller can monitor the frequency lock status frompin CHP_OUT (LOCK).Connecting the microcontrollerThe microcontroller uses 3 output pins for the configuration interface (PDATA, PCLK and PALE). PDATA should be a bi-directional pin for data read-back. The DI pin is used for data to be transmitted. DCLK providing the data timing should be connected to a microcontroller input. Optionally another pin can be used to monitor the LOCK signal (available at the CHP_OUT pin). This signal is logic level high when the PLL is in lock. SeeFigure 6. The microcontroller pins connected to PDATA and PCLK can be used for other purposes when the configuration interface is not used. PDATA and PCLK are high impedance inputs as long as PALE high. PALE has an internal pull-up resistor and should be left open (tri-stated by the microcontroller) or set to a high level during power down mode in order to prevent a trickle current flowing in the pull-up.Figure 6. Microcontroller interfaceSignal interfaceThe signal interface consists of DI and DCLK and is used for the data to be transmitted. DI is the data input line and DCLK provides a synchronous clock during data transmission.The CC1050 can be used with NRZ (Non-Return-to-Zero) data or Manchester (also known as bi-phase-level) encoded data.CC1050 can be configured for three different data formats:Synchronous NRZ mode. CC1050 provides the data clock at DCLK, and DI is used as data input. Data is clocked into CC1050 at the rising edge of DCLK. The data is modulated at RF without encoding. CC1050 can be configured for the data rates 0.6, 1.2, 2.4, 4.8, 9.6, 19.2, 38.4 or 76.8 kbit/s. See Figure 7.Synchronous Manchester encoded mode. CC1050 provides the data clock at DCLK, and DI is used as data input. Data is clocked into CC1050 at the rising edge of DCLK and should be in NRZ format. The data is modulated at RF with Manchester code. The encoding is done by CC1050. In this mode CC1050 can be configured for the data rates 0.3, 0.6, 1.2, 2.4, 4.8, 9.6, 19.2 or 38.4 kbit/s. The 38.4 kbit/s rate corresponds to the maximum 76.8 kBaud due to the Manchester encoding. See Figure 8.Transparent Asynchronous UART mode. In transmit mode DI is used as data input. The data is modulated at RF without synchronisation or encoding. Data rates in the range from 0.6 to 76.8 kBaud can be used. See Figure 9.Manchester encodingIn the Synchronous Manchester encoded mode CC1050 uses Manchester coding when modulating the data. The Manchester code is based on transitions; a “0” is encoded as a low-to-high transition, a “1” is encoded as a high-to-low transition. See Figure 10.The Manchester code ensures that the signal has a constant DC component, which is necessary in some FSK demodulators. Using this mode also ensures compatibility with CC400/CC900 designs.FSK modulating signal (NRZ),DCLK DI “RF”Clock provided by CC1050internal in CC1050Data provided by microcontrollerFigure 7. Synchronous NRZ modeFSK modulating signal (Manchester encoded),DCLK DI “RF”Clock provided by CC1050internal in CC1050Data provided by microcontroller (NRZ)Figure 8. Synchronous Manchester encoded modeFSK modulating signal,DCLK DI “RF”DCLK is not usedinternal in CC1050Data provided by UART (TXD)Figure 9. Transparent Asynchronous UART modeFigure 10. Manchester encodingFrequency programmingThe operation frequency is set byprogramming the frequency word in the configuration registers. There are two frequency words registers, termed A and B, which can be programmed to two different frequencies in order to switch fast between two different channels. Frequency word A or B is selected by theF_REG bit in the MAIN register.The frequency word is 24 bits (3 bytes) located in FREQ_2A:FREQ_1A:FREQ_0A and FREQ_2B:FREQ_1B:FREQ_0B for the A and B word respectively.The FSK frequency separation is programmed in the FSEP1:FSEP0 registers (11 bits).The frequency word FREQ is calculated by:163848192+⋅=FREQffrefVCOwhere the reference frequency is the crystal oscillator clock divided by REFDIV (4 bits in the PLL register), a number between 2 and 15:REFDIVff xoscref=The equation above gives the VCO frequency, that is, f VCO is the f0 frequency for transmit mode (lower FSK frequency).The upper FSK frequency is given by:f1 = f0 + f sepwhere f sep is set by the separation word:16384FSEPffrefsep⋅=VCOOnly one external inductor (L1) is required for the VCO. The inductor will determine the operating frequency range of the circuit. It is important to place the inductoras close to the pins as possible in order to reduce stray inductance. It is recommended to use a high Q, low tolerance inductor for best performance. Typical tuning range for the integrated varactor is 20-25%.Component values for various frequencies are given in Table 1. Component values for other frequencies can be found using the SmartRF® Studio software.VCO and PLL self-calibrationTo compensate for supply voltage, temperature and process variations the VCO and PLL must be calibrated. The calibration is done automatically and sets maximum VCO tuning range and optimum charge pump current for PLL stability. After setting up the device at the operating frequency, the self-calibration can be initiated by setting the CAL_START bit. The calibration result is stored internally in the chip, and is valid as long as power is not turned off. If large supply voltage variations (more than 0.5 V) or temperature variations (more than 40 degrees) occur after calibration, a new calibration should be performed. The self-calibration is controlled through the CAL register (see configuration registers description p. 30). The CAL_COMPLETE bit indicates complete calibration. The user can poll this bit, or simply wait for 26 ms (calibration wait time when CAL_WAIT = 1). The wait time is proportional to the internal PLL reference frequency. The lowest permitted reference frequency (1 MHz) gives 26 ms wait time, which is therefore the worst case.Referencefrequency [MHz]Calibration time[ms]2.4 112.0 131.5 181.0 26The CAL_COMPLETE bit can also be monitored at the CHP_OUT (LOCK) pin (configured by LOCK_SELECT[3:0]) and used as an interrupt input to the microcontroller.The CAL_START bit must be set to 0 by the microcontroller after the calibration is done.There are separate calibration values for the two frequency registers. If the two frequencies, A and B, differ more than 1 MHz, or different VCO currents are used (VCO_CURRENT[3:0] in the CURRENT register) the calibration should be done separately. The CAL_DUAL bit in the CAL register controls dual or separate calibration.The single calibration algorithm using separate calibration for two frequencies is illustrated in Figure 11.In Figure 12 the dual calibration algorithmis shown.Frequency register A and B are used forThe result of the calibration is stored‘Current’ is the VCO current to be usedCalibration time depend on the referenceThe result of the calibration is storedtwo different channelsforfrequency FREQ_A and can be read fromthe status registers TEST0 and TEST2when F_REG = 0for both frequenciesPA is turned off to prevent spurious emissionFrequency register B is calibrated secondfrequency, see text.forfrequency FREQ_B and can be read fromthe status registers TEST0 and TEST2when F_REG = 1Figure 11. Single calibration algorithm for two different frequenciesFrequency registers A and B are both usedfor both frequenciesfor Figure 12. Dual calibration algorithmVCO current controlThe VCO current is programmable and should be set according to operating frequency and output power. Recommended settings for the VCO_CURRENT bits in the CURRENT register are shown in the tables on page 32. The bias current for the PA buffers are also programmable. Recommended settings for the PA_DRIVE bits in the CURRENT register are shown in the tables on page 32.Power managementCC1050 offers great flexibility for power management in order to meet strict power consumption requirements in battery operated applications. Power Down mode is controlled through the MAIN register. There are separate bits to control the TX part, the frequency synthesiser and the crystal oscillator. This individual control can be used to optimise for lowest possible current consumption in a certain application. A typical power-on and initialising sequence for minimum power consumption is shown in Figure 13 and Figure 14.PALE should be tri-stated or set to a high level during power down mode in order to prevent a trickle current from flowing in the internal pull-up resistor.PA_POW should be set to 00h during power down mode to ensure lowest possible leakage current.Calibration is performed according Reset and turn on the *Time to wait depends on the crystal frequency to calibration algorithmcrystal oscillator coreand the load capacitanceFigure 13. Initializing sequence*Time to wait depends on the crystal frequencyand the load capacitanceWaiting for the PLL to lockWaiting for the PA to ramp upFigure 14. Sequence for activating TX modeOutput MatchingA few passive external components ensures match in TX mode. The matching network is shown in Figure 15. Component values for various frequenciesare given in Table 1. Component values for other frequencies can be found using the configuration software.Figure 15. Output matching networkCC1050AVDD=3VOutput power programmingThe RF output power is programmable and controlled by the PA_POW register. Table 3 shows the closest programmable value for output powers in steps of 1 dB. The typical current consumption is also shown. In power down mode the PA_POW should be set to 00h for minimum leakage current.RF frequency 433 MHz RF frequency 868 MHz Output power[dBm]PA_POW[hex] Current consumption,typ. [mA]PA_POW[hex]Current consumption,typ. [mA]-20 01 5.5 02 8.0-19 01 5.5 02 8.0-18 01 5.5 02 8.0-17 02 5.7 03 8.3-16 02 5.7 03 8.3-15 02 5.7 04 8.5-14 02 5.7 04 8.5-13 03 6.0 05 8.7-12 03 6.0 05 8.7-11 04 6.2 06 8.9-10 04 6.2 06 8.9-9 05 6.5 07 9.1 -8 05 6.5 08 9.4 -7 06 6.8 09 9.6 -6 07 7.0 0A 9.8 -5 08 7.3 0B 10.0 -4 09 7.5 0D 10.4 -3 0A 7.8 0E 10.6 -2 0C 8.3 0F 10.9 -1 0D 8.5 40 13.40 0F 9.1 50 14.21 40 10.5 60 15.02 50 11.5 70 15.73 50 11.5 80 16.34 60 12.4 90 17.05 70 13.3 A0 17.76 80 14.7 C0 19.17 90 15.1 E0 20.08 A0 15.9 FF 24.99 C0 17.610 E0 19.211 F0 20.012 FF 23.3Table 3. Output power settings and typical current consumption。

CW1055电池保护IC说明书_V1.5

过放解除电压
过流 1 检测电压
过流 2 检测电压
短路检测电压负载检测电压充电器检测电压休眠检测电压预充电启动电压异常电池检测电压充电过温检测温度充电过温保护解除迟滞温度放电过温检测温度
VC1=VC2=VC3=VC4=3.7V VC5=2.0→3.7V
VC1=VC2=VC3=VC4=VC5=3.7V VINI=0→0.2V
引脚描述
10
VC1 电池 1 正极连接端子
11
CB1 电池 1 均衡控制端子
12
VSS 芯片接地端子，连接电池 1 负极
13
REG 电源端口
14
RCOT 充电过温检测电阻连接端口
15
RDOT 放电过温检测电阻连接端口
16
CIT
过流延时设置端子
17
CDT 过放电延时设置端子
18
CCT 过充电延时设置端子
12 VSS 13 REG 14 RCOT 15 RDOT
VINI 19 CCT 18 CDT 17 CIT 16
图 2.引脚排列图
名称
SEL1 VC5 CB5 VC4 CB4 VC3 CB3 VC2 CB2
3、4、5 串电池选择引脚 1 电池 5 正极连接端子电池 5 均衡控制端子电池 4 正极连接端子电池 4 均衡控制端子电池 3 正极连接端子电池 3 均衡控制端子电池 2 正极连接端子电池 2 均衡控制端子
CW1055ALBT CW1055ALCT CW1055ALDT CW1055ALET CW1055ALFT CW1055ALGT CW1055ALHT CW1055ALIT CW1055ALJT CW1055ALKT CW1055ALLT

ZXCT1109中文资料(Diodes)中文数据手册「EasyDatasheet - 矽搜」

VSENSE5 (AC) = 10mV PP, RGAIN = 2.5kΩ
TA 25°C -40°C 125°C 25°C -40°C 125°C 25°C -40°C 125°C 25°C -40°C 125°C 25°C -40°C 125°C
25°C
25°C 25°C -40°C 125°C
25°C
0 0 100 200 300 400 500 600 V (mV)
输出电流与V
9.0
V
= 0V
8.0 V = 0V
7.0
6.0 (µA)
5.0
I 4.0
3.0
2.0
V = 20V V = 3.7V
1.0
0.0 -40 -25 -10 5
20 35 50 65 80 95 110 125
温度（℃）
输入电流与环境温度
0
VS- - 1
V
0
VS+ - 2.5
TA
环境温度范围
-40
125
°C
Notes.
4. For the ZXCT1107 and ZXCT1109 pin 1 (OUT) actsasboth the output pin and substrate connection. Thismeansthat for the
7. Defined asdifference between actual output current and 40 µA; measured at V currentsof the device.
SENSE =10mV. Thiswill include an error due to bias
TA 25°C -40°C 125°C 25°C -40°C 125°C 25°C -40°C 125°C 25°C -40°C 125°C 25°C -40°C 125°C 25°C -40°C 125°C 25°C -40°C 125°C

IRU1050CT资料

IRU1050TYPICAL APPLICATIONDESCRIPTIONThe IRU1050 is a low dropout three-terminal adjustable regulator with minimum of 5A output current capability.This product is specifically designed to provide well regu-lated supply for low voltage IC applications such as Pentium ™ P54C ™,P55C ™ as well as GTL+ termination for Pentium Pro ™ and Klamath ™ processor applications.The IRU1050 is also well suited for other processors such as Cyrix ™, AMD and Power PC ™ applications.The IRU1050 is guaranteed to have <1.3V dropout at full load current making it ideal to provide well regulated outputs of 2.5V to 3.3V with 4.75V to 7V input supply.5A LOW DROPOUT POSITIVEADJUSTABLE REGULATOR Notes: Pentium P54C, P55C, Klamath, Pentium Pro,VRE are trademarks of Intel Corp. Cyrix M2 is trademark of Cyrix Corp.Power PC is trademark of IBM Corp.PACKAGE ORDER INFORMATIONT J (°C) 2-PIN PLASTIC 3-PIN PLASTIC 2-PIN PLASTIC 3-PIN PLASTIC TO-252 (D-Pak) TO-263 (M) Ultra Thin-Pak TM (P) TO-220 (T) 0 To 150 IRU1050CD IRU1050CM IRU1050CP IRU1050CTData Sheet No. PD94126Figure 1 - Typical Application of IRU1050 in a 5V to 3.38V regulator designedto meet the Intel P54C ™ processors.Low Voltage Processor Applications such as:P54C ™, P55C ™, Cyrix M2™,POWER PC ™, AMD GTL+ TerminationPENTIUM PRO ™, KLAMATH ™Low Voltage Memory Termination Applications Standard 3.3V Chip Set and Logic ApplicationsFEATURESAPPLICATIONSGuaranteed < 1.3V Dropout at Full Load Current Fast Transient Response1% Voltage Reference Initial Accuracy Output Current Limiting Built-In Thermal Shutdown元器件交易网IRU1050ABSOLUTE MAXIMUM RATINGSInput Voltage (V IN ) .................................................... 7VPower Dissipation ..................................................... Internally Limited Storage Temperature Range ...................................... -65°C To 150°C Operating Junction Temperature Range ..................... 0°C To 150°CELECTRICAL SPECIFICATIONSUnless otherwise specified, these specifications apply over C IN =1m F, C OUT =10m F, and T J =0 to 1508C.Typical values refer to T J =258C.Note 1: Low duty cycle pulse testing with Kelvin con-nections is required in order to maintain accurate data.Note 2: Dropout voltage is defined as the minimum dif-ferential voltage between V IN and V OUT required to main-tain regulation at V OUT . It is measured when the outputvoltage drops 1% below its nominal value.Note 3: Minimum load current is defined as the mini-mum current required at the output in order for the out-put voltage to maintain regulation. Typically the resistor dividers are selected such that it automatically main-tains this current.PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS V REF D Vo I ADJ Reference VoltageLine Regulation Load Regulation (Note 1)Dropout Voltage (Note 2)Current Limit Minimum Load Current (Note 3)Thermal Regulation Ripple Rejection Adjust Pin Current Adjust Pin Current ChangeTemperature Stability Long Term Stability RMS Output NoiseIo=10mA, T J =258C, V IN -Vo=1.5V Io=10mA, V IN -Vo=1.5Io=10mA, 1.3V<(V IN -Vo)<7V V IN =3.3V, V ADJ =0V, 10mA<Io<5A Note 2, Io=4A Io=5A V IN =3.3V, D Vo=100mV V IN =3.3V, V ADJ =0V 30ms Pulse, V IN -Vo=3V, Io=5A f=120Hz, Co=25m F Tantalum,Io=2.5A, V IN -Vo=3V Io=10mA, V IN -Vo=1.5V, T J =258C,Io=10mA, V IN -Vo=1.5V Io=10mA, V IN -Vo=1.5V, T J =258C V IN =3.3V, V ADJ =0V, Io=10mA T J =1258C, 1000Hrs T J =258C, 10Hz<f<10KHz 1.2381.2255.160 1.251.251.150.0170550.20.50.30.003 1.2621.2750.20.41.21.3100.0212051V%%V AmA %/W dBm A m A %%%VoIRU1050IntroductionThe IRU1050 adjustable Low Dropout (LDO) regulator is a three-terminal device which can easily be programmed with the addition of two external resistors to any volt-ages within the range of 1.25 to 5.5 V. This regulator unlike the first generation of the three-terminal regula-tors such as LM117 that required 3V differential between the input and the regulated output, only needs 1.3V dif-ferential to maintain output regulation. This is a key re-quirement for today’s microprocessors that need typi-cally 3.3V supply and are often generated from the 5V supply. Another major requirement of these micropro-cessors such as the Intel P54C ™ is the need to switch the load current from zero to several amps in tens ofnanoseconds at the processor pins, which translates to an approximately 300 to 500ns current step at the regu-lator. In addition, the output voltage tolerances are also extremely tight and they include the transient response as part of the specification.For example Intel VRE ™specification calls for a total of ±100mV including initial tolerance, load regulation and 0 to 4.6A load step.The IRU1050 is specifically designed to meet the fast current transient needs as well as providing an accurate initial voltage, reducing the overall system cost with the need for fewer output capacitors.PIN DESCRIPTIONSPIN # PIN SYMBOL PIN DESCRIPTIONFigure 2 - Simplified block diagram of the IRU1050.A resistor divider from this pin to the V OUT pin and ground sets the output voltage.The output of the regulator. A minimum of 10m F capacitor must be connected from this pin to ground to insure stability.The input pin of the regulator. Typically a large storage capacitor is connected from this pin to ground to insure that the input voltage does not sag below the minimum drop out voltage during the load transient response. This pin must always be 1.3V higher than V OUT in order for the device to regulate properly.BLOCK DIAGRAM123Adj V OUTV INV INAdjV OUTAPPLICATION INFORMATIONIRU1050Output Voltage SettingThe IRU1050 can be programmed to any voltages in the range of 1.25V to 5.5V with the addition of R1 and R2external resistors according to the following formula:Where:V REF = 1.25V Typically I ADJ = 50m A TypicallyR1 and R2 as shown in Figure 3:Figure 3 - Typical application of the IRU1050for programming the output voltage.The IRU1050 keeps a constant 1.25V between the out-put pin and the adjust pin. By placing a resistor R1 across these two pins a constant current flows through R1, add-ing to the I ADJ current and into the R2 resistor producing a voltage equal to the (1.25/R1)3R2 + I ADJ 3R2 which will be added to the 1.25V to set the output voltage.This is summarized in the above equation. Since the minimum load current requirement of the IRU1050 is 10mA, R1 is typically selected to be 121V resistor so that it automatically satisfies the minimum current re-quirement. Notice that since I ADJ is typically in the range of 50m A it only adds a small error to the output voltage and should only be considered when a very precise out-put voltage setting is required. For example, in a typical 3.3V application where R1=121V and R2=200V the er-ror due to I ADJ is only 0.3% of the nominal set point.Load RegulationSince the IRU1050 is only a three-terminal device, it is not possible to provide true remote sensing of the output voltage at the load. Figure 4 shows that the best load regulation is achieved when the bottom side of R2 is connected to the load and the top side of R1 resistor is connected directly to the case or the V OUT pin of the regulator and not to the load. In fact, if R1 is connected to the load side, the effective resistance between theregulator and the load is gained up by the factor of (1+R2/R1), or the effective resistance will be R P(eff)=R P 3(1+R2/R1). It is important to note that for high current applica-tions, this can represent a significant percentage of the overall load regulation and one must keep the path from the regulator to the load as short as possible to mini-mize this effect.Figure 4 - Schematic showing connectionfor best load regulation.StabilityThe IRU1050 requires the use of an output capacitor as part of the frequency compensation in order to make the regulator stable. Typical designs for microprocessor ap-plications use standard electrolytic capacitors with a typical ESR in the range of 50 to 100m V and an output capacitance of 500 to 1000m F. Fortunately as the ca-pacitance increases, the ESR decreases resulting in a fixed RC time constant. The IRU1050 takes advantage of this phenomena in making the overall regulator loop stable. For most applications a minimum of 100m F alu-minum electrolytic capacitor such as Sanyo MVGX se-ries, Panasonic FA series as well as the Nichicon PL series insures both stability and good transient response.Thermal DesignThe IRU1050 incorporates an internal thermal shutdown that protects the device when the junction temperature exceeds the maximum allowable junction temperature.Although this device can operate with junction tempera-tures in the range of 1508C, it is recommended that the selected heat sink be chosen such that during maxi-mum continuous load operation the junction tempera-ture is kept below this number. The example below shows the steps in selecting the proper regulator heat sink for the worst case current consumption using Intel 200MHz microprocessor as the load.O U TV IV R LPARASITIC LINE V OUT = V REF 3 1+ +I ADJ 3R2R2R1( )IRU1050Assuming the following specifications:The steps for selecting a proper heat sink to keep the junction temperature below 1358C is given as:1) Calculate the maximum power dissipation using:2) Select a package from the regulator data sheet and record its junction to case (or tab) thermal resistance.Selecting TO-220 package gives us:3) Assuming that the heat sink is black anodized, cal-culate the maximum heat sink temperature allowed:Assume, u cs=0.05°C/W (heat-sink-to-case thermal resistance for black anodized)4) With the maximum heat sink temperature calculated in the previous step, the heat-sink-to-air thermal re-s i s t a n c e (u SA ) is calculated by first calculating the temperature rise above the ambient as follows:5) Next, a heat sink with lower u SA than the one calcu-lated in Step 4 must be selected. One way to do this is to simply look at the graphs of the “Heat Sink Temp Rise Above the Ambient” vs. the “Power Dissipation”and select a heat sink that results in lower tempera-ture rise than the one calculated in previous step.The following heat sinks from AAVID and Thermalloy meet this criteria.P D = I OUT 3(V IN - V OUT )P D = 4.63(5 - 3.5) = 6.9WV IN = 5V V OUT = 3.5V I OUT(MAX) = 4.6A T A = 358Cu JC = 2.78C/WT S = T J - P D 3(u JC + u CS )T S = 135 - 6.93(27 + 0.05) = 1168Cu SA = = = 11.78C/WD T P D 816.9D T = T S - T A = 116 - 35 = 818C ∆T = Temperature Rise Above Ambient Note: For further information regarding the above com-panies and their latest product offerings and application support contact your local representative or the num-bers listed below:AAVID.................PH# (603) 528 3400Thermalloy...........PH# (214) 243-4321Designing for Microprocessor ApplicationsAs it was mentioned before, the IRU1050 is designed specifically to provide power for the new generation of the low voltage processors requiring voltages in the range of 2.5V to 3.6V generated by stepping down the 5V sup-ply. These processors demand a fast regulator that sup-ports their large load current changes. The worst case current step seen by the regulator is anywhere in the range of 1 to 7A with the slew rate of 300 to 500ns which could happen when the processor transitions from “Stop Clock” mode to the “Full Active” mode. The load current step at the processor is actually much faster, in the or-der of 15 to 20ns, however, the decoupling capacitors placed in the cavity of the processor socket handle this transition until the regulator responds to the load current levels. Because of this requirement the selection of high frequency low ESR and low ESL output capacitor is imperative in the design of these regulator circuits.Figure 5 shows the effects of a fast transient on the output voltage of the regulator. As shown in this figure,the ESR of the output capacitor produces an instanta-neous drop equal to the (D V ESR =ESR 3D I) and the ESL effect will be equal to the rate of change of the output current times the inductance of the capacitor. (D V ESL =L 3D I/D t). The output capacitance effect is a droop in the output voltage proportional to the time it takes for the regulator to respond to the change in the current,(D Vc=D t 3D I/C) where D t is the response time of the regulator.Air Flow (LFM)0 100 200 300 400 Thermalloy 6021PB 6021PB 6073PB 6109PB 7141DAAVID 534202B 534202B 507302 575002 576802BIRU1050D Vc = = = 1.2mVD t 3 D I 2 3 4.6C 7500C IN = = 1530m F4.6 3 500.15ESR =(V IN - V OUT - D V - V DROP )D IESR = = 0.032V(5 - 3.5 - 1.2 - 0.15)4.6ESR [ = 8m V374.6Type of V OUT I MAX Max Allowed Processor Nominal Output Tolerance Intel-P54C VRE 3.50 V 4.6 A ±100 mVFigure 5 - Typical regulator responseto the fast load current step.An example of a regulator design to meet the Intel P54C ™VRE specification is given below.Assume the specification for the processor as shown in Table 1:Table 1 - Processor SpecificationThe first step is to select the voltage step allowed in the output due to the output capacitor’s ESR:1) Assuming the regulator’s initial accuracy plus the re-sistor divider tolerance is ≈ ±53mV (±1.5% of 3.5V nominal), then the total step allowed for the ESR and the ESL is −47mV.Assuming that the ESL drop is −10mV, the remain-ing ESR step will be −37mV. Therefore the output capacitor ESR must be:The Sanyo MVGX series is a good choice to achieve both price and performance goals. The 6MV1500GX,1500m F, 6.3V has an ESR of less than 36m V typi-cal. Selecting 5 of these capacitors in parallel has an ESR of ≈ 7.2m V which achieves our design goal.The next step is to calculate the drop due to the ca-pacitance discharge and make sure that this drop in voltage is less than the selected ESL drop in the previous step.R2 = 3R1 = 3121 = 217.8V V OUT V REF -1( ) 3.51.25-1( )2) The output capacitance is 531500m F = 7500m FWhere:D t = 2m s is the regulator response timeTo set the output DC voltage, we need to select R1 and R2:3) Assuming R1=121V , 0.1%:Select R2=218V , 0.1%Selecting both R1 and R2 resistors to be 0.1% toler-ance, results in the least amount of error introducedby the resistor dividers leaving ≈ ±1.3% error budget for the IRU1050 reference which is within the initial accuracy of the device.Finally, the input capacitor is selected as follows:4) Assuming that the input voltage can drop 150mV be-fore the main power supply responds, and that the main power supply response time is ≈ 50m s, then the minimum input capacitance for a 4.6A load step is given by:The ESR should be less than:Where:V DROP L Input voltage drop allowed in step 4D V L Maximum regulator dropout voltage D I L Load current stepSelecting two Sanyo 1500m F, the same type as the output capacitors, meets our requirements.IRU1050Layout ConsiderationThe output capacitors must be located as close to the V OUT terminal of the device as possible. It is recom-mended to use a section of a layer of the PC board as a plane to connect the V OUT pin to the output capacitors to prevent any high frequency oscillation that may result due to excessive trace inductance.Figure 6 shows the completed schematic for our ex-ample.Figure 6 - Final schematic for the Intel VRE application.IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105TAC Fax: (310) 252-7903Visit us at for sales contact informationData and specifications subject to change without notice. 02/01IRU1050(D) TO-252 Package2-PinSYMBOL A B C D E F GH J K L M N O P Q R R1S MIN 6.4775.0040.6867.4179.7030.6354.521&1.522.1840.7621.0165.9691.01600.5340.428MAX6.7315.2070.8388.17910.0840.8894.623&1.622.3880.8641.1186.2231.1180.1020.6860.588NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.7LC JR0.31 TYP R0.51 TYP 2.286 BSCIRU1050(M) TO-263 Package3-PinSYMBOLA B C D E G H K L M N P R S U V MIN 10.058.284.310.661.1414.731.400.002.490.332.286082.41MAX 10.3128.7634.5720.911.4015.751.680.2542.740.582.794882.676.50 REF 7.75 REF2.54 REF NOTE: ALL MEASUREMENTSARE IN MILLIMETERS.C LIRU1050(P) Ultra Thin-Pak TM2-PinNOTE: ALL MEASUREMENTSARE IN MILLIMETERS.SYMBOLA A1BCDE G G1H K L M N P R U V MIN 5.915.546.021.700.630.172.164.459.420.760.020.890.250.94282.92MAX 6.175.796.272.030.790.332.414.709.681.270.131.140.251.19683.305.08 NOMIRU105011Rev. 1.808/20/02(T) TO-220 Package3-PinSYMBOL A a b b1C1CP D E e e1e3F H1J1L Q R MIN 4.06380.631.140.383.71D 14.229.782.294.831.141.145.942.2913.7162.625.588MAX4.837.581.021.520.563.96D 15.06210.542.795.331.401.406.552.9214.222.876.17NOTE: ALL MEASUREMENTS ARE IN MILLIMETERS.12Rev. 1.808/20/02IRU1050PKG DESIG D M P TPACKAGE DESCRIPTIONTO-252, (D-Pak)TO-263Ultra Thin-Pak TM TO-220PARTS PER TUBE75507550PARTS PER REEL 25007502500---PACKAGE SHIPMENT METHODPIN COUNT 2323T & R OrientationFig A Fig B Fig C ---Feed Direction Figure A Feed DirectionFigureBIR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105TAC Fax: (310) 252-7903Visit us at for sales contact informationData and specifications subject to change without notice. 02/01Feed Direction FigureC。