数字滤波器的外文翻译
图像处理中值滤波器中英文对照外文翻译文献
中英文资料对照外文翻译一、英文原文A NEW CONTENT BASED MEDIAN FILTERABSTRACTIn this paper the hardware implementation of a contentbased median filter suitabl e for real-time impulse noise suppression is presented. The function of the proposed ci rcuitry is adaptive; it detects the existence of impulse noise in an image neighborhood and applies the median filter operator only when necessary. In this way, the blurring o f the imagein process is avoided and the integrity of edge and detail information is pre served. The proposed digital hardware structure is capable of processing gray-scale im ages of 8-bit resolution and is fully pipelined, whereas parallel processing is used to m inimize computational time. The architecturepresented was implemented in FPGA an d it can be used in industrial imaging applications, where fast processing is of the utm ost importance. The typical system clock frequency is 55 MHz.1. INTRODUCTIONTwo applications of great importance in the area of image processing are noise filtering and image enhancement [1].These tasks are an essential part of any image pro cessor,whether the final image is utilized for visual interpretation or for automatic an alysis. The aim of noise filtering is to eliminate noise and its effects on the original im age, while corrupting the image as little as possible. To this end, nonlinear techniques (like the median and, in general, order statistics filters) have been found to provide mo re satisfactory results in comparison to linear methods. Impulse noise exists in many p ractical applications and can be generated by various sources, including a number of man made phenomena, such as unprotected switches, industrial machines and car ign ition systems. Images are often corrupted by impulse noise due to a noisy sensor or ch annel transmission errors. The most common method used for impulse noise suppressi on n forgray-scale and color images is the median filter (MF) [2].The basic drawback o f the application of the MF is the blurringof the image in process. In the general case,t he filter is applied uniformly across an image, modifying pixels that arenot contamina ted by noise. In this way, the effective elimination of impulse noise is often at the exp ense of an overalldegradation of the image and blurred or distorted features[3].In this paper an intelligent hardware structure of a content based median filter (CBMF) suita ble for impulse noise suppression is presented. The function of the proposed circuit is to detect the existence of noise in the image window and apply the corresponding MFonly when necessary. The noise detection procedure is based on the content of the im age and computes the differences between the central pixel and thesurrounding pixels of a neighborhood. The main advantage of this adaptive approach is that image blurrin g is avoided and the integrity of edge and detail information are preserved[4,5]. The pro posed digital hardware structure is capable of processing gray-scale images of 8-bitres olution and performs both positive and negative impulse noise removal. The architectt ure chosen is based on a sequence of four basic functional pipelined stages, and parall el processing is used within each stage. A moving window of a 3×3 and 5×5-pixel im age neighborhood can be selected. However, the system can be easily expanded to acc ommodate windows of larger sizes. The proposed structure was implemented using fi eld programmable gate arrays (FPGA). The digital circuit was designed, compiled and successfully simulated using the MAX+PLUS II Programmable Logic Development S ystem by Altera Corporation. The EPF10K200SFC484-1 FPGA device of the FLEX1 0KE device family was utilized for the realization of the system. The typical clock fre quency is 55 MHz and the system can be used for real-time imaging applications whe re fast processing is required [6]. As an example,the time required to perform filtering of a gray-scale image of 260×244 pixels is approximately 10.6 msec.2. ADAPTIVE FILTERING PROCEDUREThe output of a median filter at a point x of an image f depends on the values of t he image points in the neighborhood of x. This neighborhood is determined by a wind ow W that is located at point x of f including n points x1, x2, …, xn of f, with n=2k+1. The proposed adaptive content based median filter can be utilized for impulse noisesu p pression in gray-scale images. A block diagram of the adaptive filtering procedure is depicted in Fig. 1. The noise detection procedure for both positive and negative noise is as follows:(i) We consider a neighborhood window W that is located at point x of the image f. Th e differences between the central pixel at point x and the pixel values of the n-1surr ounding points of the neighborhood (excluding thevalue of the central pixel) are co mputed.(ii) The sum of the absolute values of these differences is computed, denoted as fabs(x ). This value provides ameasure of closeness between the central pixel and its su rrounding pixels.(iii) The value fabs(x) is compared to fthreshold(x), which is anappropriately selected positive integer threshold value and can be modified. The central pixel is conside red to be noise when the value fabs(x) is greater than thethreshold value fthresho d(x).(iv) When the central pixel is considered to be noise it is substituted by the median val ue of the image neighborhood,denoted as fk+1, which is the normal operationof the median filter. In the opposite case, the value of the central pixel is not altered and the procedure is repeated for the next neighborhood window.From the noised etection scheme described, it should be mentioned that the noise detection level procedure can be controlled and a range of pixel values (and not only the fixedvalues of 0 and 255, salt and pepper noise) is considered asimpulse noise.In Fig. 2 the results of the application of the median filter and the CBMF in the gray-sca le image “Peppers” are depicted.More specifically, in Fig. 2(a) the original,uncor rupted image“Peppers” is depicted. In Fig. 2(b) the original imagedegraded by 5% both positive and negative impulse noise isillustrated. In Figs 2(c) and 2(d) the resultant images of the application of median filter and CBMF for a 3×3-pixel win dow are shown, respectively. Finally, the resultant images of the application of m edian filter and CBMF for a 5×5-pixelwindow are presented in Figs 2(e) and 2(f). It can be noticed that the application of the CBMF preserves much better edges a nddetails of the images, in comparison to the median filter.A number of different objective measures can be utilized forthe evaluation of these results. The most wi dely used measures are the Mean Square Error (MSE) and the Normalized Mean Square Error (NMSE) [1]. The results of the estimation of these measures for the two filters are depicted in Table I.For the estimation of these measures, the result ant images of the filters are compared to the original, uncorrupted image.From T able I it can be noticed that the MSE and NMSE estimatedfor the application of t he CBMF are considerably smaller than those estimated for the median filter, in all the cases.Table I. Similarity measures.3. HARDWARE ARCHITECTUREThe structure of the adaptive filter comprises four basic functional units, the mo ving window unit , the median computation unit , the arithmetic operations unit , and th e output selection unit . The input data of the system are the gray-scale values of the pi xels of the image neighborhood and the noise threshold value. For the computation of the filter output a3×3 or 5×5-pixel image neighborhood can be selected. Image input d ata is serially imported into the first stage. In this way,the total number of the inputpin s are 24 (21 inputs for the input data and 3 inputs for the clock and the control signalsr equired). The output data of the system are the resultant gray-scale values computed f or the operation selected (8pins).The moving window unit is the internal memory of the system,used for storing th e input values of the pixels and for realizing the moving window operation. The pixel values of the input image, denoted as “IMAGE_INPUT[7..0]”, areimported into this u nit in serial. For the representation of thethreshold value used for the detection of a no Filter Impulse noise 5% mse Nmse(×10-2) 3×3 5×5 3×3 5×5Median CBMF 57.554 35.287 130.496 84.788 0.317 0.194 0.718 0.467ise pixel 13 bits are required. For the moving window operation a 3×3 (5×5)-pixel sep entine type memory is used, consisting of 9 (25)registers. In this way,when the windoP1 P2 P3w is moved into the next image neighborhood only 3 or 5 pixel values stored in the memory are altered. The “en5×5” control signal is used for the selection of the size of th e image window, when“en5×5” is equal to “0” (“1”) a 3×3 (5×5)-pixel neighborhood is selected. It should be mentioned that the modules of the circuit used for the 3×3-pix el window are utilized for the 5×5-pixel window as well. For these modules, 2-to-1mu ltiplexers are utilized to select the appropriate pixel values,where necessary. The mod ules that are utilized only in the case of the 5×5-pixel neighborhood are enabled by th e“en5×5” control signal. The outputs of this unit are rows ofpixel values (3 or 5, respe ctively), which are the inputs to the median computation unit.The task of the median c omputation unit is to compute themedian value of the image neighborhood in order to substitutethe central pixel value, if necessary. For this purpose a25-input sorter is utili zeed. The structure of the sorter has been proposed by Batcher and is based on the use of CS blocks. ACS block is a max/min module; its first output is the maximumof the i nputs and its second output the minimum. The implementation of a CS block includes a comparator and two 2-to-1 multiplexers. The outputs values of the sorter, denoted a s “OUT_0[7..0]”…. “OUT_24[7..0]”, produce a “sorted list” of the 25 initial pixel val ues. A 2-to-1 multiplexer isused for the selection of the median value for a 3×3 or 5×5-pixel neighborhood.The function of the arithmetic operations unit is to computethe value fabs(x), whi ch is compared to the noise threshold value in the final stage of the adaptive filter.The in puts of this unit are the surrounding pixel values and the central pixelof the neighb orhood. For the implementation of the mathematical expression of fabs(x), the circuit of this unit contains a number of adder modules. Note that registers have been used to achieve a pipelined operation. An additional 2-to-1 multiplexer is utilized for the selec tion of the appropriate output value, depending on the “en5×5” control signal. From th e implementation point of view, the use of arithmetic blocks makes this stage hardwar e demanding.The output selection unit is used for the selection of the appropriateoutput value of the performed noise suppression operation. For this selection, the corresponding no ise threshold value calculated for the image neighborhood,“NOISE_THRES HOLD[1 2..0]”,is employed. This value is compared to fabs(x) and the result of the comparison Classifies the central pixel either as impulse noise or not. If thevalue fabs(x) is greater than the threshold value fthreshold(x) the central pixel is positive or negative impulse noise and has to be eliminated. For this reason, the output of the comparison is used as the selection signal of a 2-to-1 multiplexer whose inputs are the central pixel and the c orresponding median value for the image neighborhood. The output of the multiplexer is the output of this stage and the final output of the circuit of the adaptive filter.The st ructure of the CBMF, the computation procedure and the design of the four aforeme n tioned units are illustrated in Fig. 3.ImagewindoeFigure 1: Block diagram of the filtering methodFigure 2: Results of the application of the CBMF: (a) Original image, (b) noise corrupted image (c) Restored image by a 3x3 MF, (d) Restored image by a 3x3 CBMF, (e) Restored image by a 5x5 MF and (f) Restored image by a 5x5 CBMF.4. IMPLEMENTATION ISSUESThe proposed structure was implemented in FPGA,which offer an attractive com bination of low cost, high performance and apparent flexibility, using the software pa ckage+PLUS II of Altera Corporation. The FPGA used is the EPF10K200SFC484-1 d evice of the FLEX10KE device family,a device family suitable for designs that requir e high densities and high I/O count. The 99% of the logic cells(9965/9984 logic cells) of the device was utilized to implement the circuit . The typical operating clock frequ ency of the system is 55 MHz. As a comparison, the time required to perform filtering of a gray-scale image of 260×244 pixelsusing Matlab® software on a Pentium 4/2.4 G Hz computer system is approximately 7.2 sec, whereas the corresponding time using h ardware is approximately 10.6 msec.The modification of the system to accommodate windows oflarger sizes can be done in a straightforward way, requiring onlya small nu mber of changes. More specifically, in the first unit the size of the serpentine memory P4P5P6P7P8P9SubtractorarryMedianfilteradder comparatormuitiplexerf abc(x)valueand the corresponding number of multiplexers increase following a square law. In the second unit, the sorter module should be modified,and in the third unit the number of the adder devicesincreases following a square law. In the last unit no changes are requ ired.5. CONCLUSIONSThis paper presents a new hardware structure of a content based median filter, ca pable of performing adaptive impulse noise removal for gray-scale images. The noise detection procedure takes into account the differences between the central pixel and th e surrounding pixels of a neighborhood.The proposed digital circuit is capable ofproce ssing grayscale images of 8-bit resolution, with 3×3 or 5×5-pixel neighborhoods as op tions for the computation of the filter output. However, the design of the circuit is dire ctly expandableto accommodate larger size image windows. The adaptive filter was d eigned and implemented in FPGA. The typical clock frequency is 55 MHz and the sys tem is suitable forreal-time imaging applications.REFERENCES[1] W. K. Pratt, Digital Image Processing. New York: Wiley,1991.[2] G. R. Arce, N. C. Gallagher and T. Nodes, “Median filters:Theory and applicat ions,” in Advances in ComputerVision and Image Processing, Greenwich, CT: JAI, 1986.[3] T. A. Nodes and N. C. Gallagher, Jr., “The output distributionof median type filte rs,” IEEE Transactions onCommunications, vol. COM-32, pp. 532-541, May1984.[4] T. Sun and Y. Neuvo, “Detail-preserving median basedfilters in imageprocessing,” Pattern Recognition Letters,vol. 15, pp. 341-347, Apr. 1994.[5] E. Abreau, M. Lightstone, S. K. Mitra, and K. Arakawa,“A new efficient approachfor the removal of impulsenoise from highly corrupted images,” IEEE Transa ctionson Image Processing, vol. 5, pp. 1012-1025, June 1996.[6] E. R. Dougherty and P. Laplante, Introduction to Real-Time Imaging, Bellingham:SPIE/IEEE Press, 1995.二、英文翻译基于中值滤波的新的内容摘要在本设计中的提出了基于中值滤波的硬件实现用来抑制脉冲噪声的干扰。
signal.butter 滤波器的计算的公式
信号滤波是数字信号处理领域中的重要内容，它可以有效地消除噪音和干扰，提高信号的质量和可靠性。
而 signal.butter 滤波器作为一种常用的数字滤波器，在实际应用中具有广泛的使用价值。
本文将从signal.butter 滤波器的计算公式入手，深入探讨其原理、应用和优缺点，以帮助读者更好地理解和应用这一主题。
一、signal.butter 滤波器的计算公式signal.butter 函数是 Python 中 scipy.signal 模块中的一个函数，用于设计数字 Butterworth 滤波器。
它的计算公式如下：```pythonb, a = signal.butter(N, Wn, btype='low', analog=False,output='ba', fs=None)```其中，参数含义如下：- N：滤波器的阶数，代表滤波器的复杂度，对应于滤波器的极点个数。
- Wn：归一化的截止频率，取值范围为 0 < Wn < 1，对于数字滤波器而言，截止频率 Wn 实际上代表了模拟滤波器的截止频率除以采样频率的一半。
- btype：滤波器的类型，可选值为 'low'、'high'、'bandpass'、'bandstop'，分别代表低通、高通、带通和带阻滤波器。
- analog：是否为模拟滤波器，如果为 True，则设计模拟滤波器；如果为 False，则设计数字滤波器。
- output：输出类型，可选值为 'ba'、'zpk'、'sos'，分别代表输出传递函数系数、零极点、二阶级联滤波器表示。
- fs：采样频率，用于指定数字滤波器的采样频率。
根据以上计算公式，我们可以灵活设置滤波器的阶数、截止频率、类型等参数，根据实际需求来设计滤波器，以实现对信号的滤波处理。
数字滤波器概念及设计
数字滤波器概念及设计数字滤波器概念及设计•数字滤波器分类•滤波器相关函数•常见滤波器•o平均滤波器o平滑滤波器o限幅滤波器o中值滤波器数字滤波器(digital filter)是一个离散时间系统，通常按照预定的算法，将输入的离散时间信号或数字信号转化为所要求的离散时间或数值信号，相对于模拟滤波器而言，数字滤波器具有精度高、可靠性高、灵活性好、可程序控制调试的优点。
数字滤波器分类滤波器可以分为经典滤波器和现代滤波器两类经典滤波器：经典滤波器（classical filter),其原理是假定期望信号和噪声各占不同频段，滤波后去除噪声频段的信号，保留期望频段的信号。
•按频率分类：•(1)低通滤波器：low-pass filter•(2)高通滤波器：high-pass filter•(3)带通滤波器：band-pass filter•(4)带阻滤波器：band-stop filter•(5)全通滤波器：all-pass filter•按单位冲击响应特性分类：•(1)无限冲击响应滤波器:infinite impulse respance•(2)有限冲击响应滤波器：finite impulse respance•其中有限冲击响应滤波器可以参考FIR数字滤波器,该文介绍了有限冲击响应滤波器的设计方法，和代码实现。
•现代滤波器：•现代滤波器又称为统计最优滤波器(statistical optimal filter),与经典滤波器不同，统计最优滤波器是依据某些统计最优规则，从带噪声的测试信号中对由用信号或信号参数进行估计。
•（1）维纳滤波器：Wiener filter•（2）卡尔曼滤波器：Kalman filter•（3）自适应滤波器：adaptive filter•现代滤波器中，卡尔曼滤波器比较常见，其公式推导和实现方法可以参考卡尔曼滤波原理介绍及算法实现,该文介绍了详细的推导公式和代码实现。
滤波器相关函数当ak全为0时，滤波器称为有限冲击响应滤波器，当不全为0时，称为无限冲击响应滤波器。
信号分析与处理英语单词
1.滤波器（filter）2.信号(signal)3.信息（information）4.函数（function）5.消息（message）6.知识（knowledge）7.频率(frequency)8.幅度(amplitude)9.相位(phase)10.模拟信号(analog signal)11.量化信号(quantized signal)12.抽样信号(sampling signal)13.数字信号(digital signal)14.确定性信号(determinate)15.随机信号(random)16.周期信号(periodic)17.非周期信号(nonperiodic)18.时限信号(time finite)19.频限信号(frequency finite)20.频谱分析(frequency spectrum)21.时域(Time domain)22.频域(Frequency domain)23.指数信号(exponential)24.复指数函数(complex exponential)25.欧拉公式(Euler's formula)26.阶跃(step)27.符号(signum)28.单位冲激(unit impulse)29.移位（shift）30.反褶（reverse）31.尺度倍乘(scaling)32.微分(differential)33.积分(integration)34.定积分(definite integration)35.奇与偶(odd & even)36.线形系统（Linear System）37.实部与虚部(real & imaginary)38.正交(orthogonal)39.谐波(harmonic)40.卷积(convolution)41.齐次性（homogeneity）42.叠加性（additivity）43.矢量（vector）44.三角函数（trigonometric function）45.完备(perfect)46.傅里叶级数（Fourier series）。
数字滤波器的截止频率
数字滤波器的截止频率数字滤波器（Digital Filters）是数字信号处理中非常重要的一个概念，它可以对数字信号进行去噪、衰减特定频率分量等处理。
数字滤波器有很多种类型，如FIR （Finite Impulse Response）滤波器、IIR（Infinite Impulse Response）滤波器、Butterworth滤波器等。
其中，数字滤波器的截止频率是非常重要的参数，下文将详细介绍数字滤波器的截止频率和相关概念。
一、数字滤波器的概念和分类数字滤波器是数字信号处理中用于对数字信号进行滤波处理的一种算法。
数字信号处理是一种利用数字电路或计算机对信号进行数字化处理的技术。
数字滤波器可以分为两大类：有限长冲激响应（FIR）滤波器和无限长冲激响应（IIR）滤波器。
FIR滤波器是由有限长的冲激响应组成的数字滤波器，其特点是具有线性相位，所以能够保持信号的波形特征。
IIR滤波器由无限长的冲激响应组成，具有递归结构，其特点是能够实现高阶滤波器的设计，但在设计过程中需要关注其稳定性和相位响应特性。
二、数字滤波器的截止频率数字滤波器的截止频率又称为截止频带，是指滤波器对于输入信号的某一频率分量进行截止（即衰减）的频率。
截止频率的选择是数字滤波器设计中非常重要的一环，直接关系到滤波器的性能。
截止频率是由滤波器的截止频带宽和截止频率位置两个参数决定的。
例如，一个FIR低通滤波器，其截止频率为500 Hz，截止频带宽为100 Hz，则其在0-400 Hz的带内不做滤波，而在500-2500 Hz的带外进行完全滤波。
在数字滤波器设计中，有几种不同的表示方式可以用来描述截止频率，分别如下：1. 离散时间模拟滤波器（DTAF）的截止频率DTAF滤波器是一种与线性时不变系统等效的差分方程，其截止频率以nyquist为单位表示，即采样频率的一半。
例如，若采样频率为2 kHz，则DTAF滤波器的截止频率为1 kHz。
数字信号处理(DSP)专业词汇
系统：system 信号：signal模拟信号：analog signal 数字信号：digital signal模/数转换：analog-to-digital conversion 频谱：spectrum数字滤波：digital filtering 滤波器：filter采样：sample 保持：hold数字代码：digital code 量化电平：quantization level时域：time domain 频域：frequency domain低频：low frequency 高频：high frequency低通滤波器：low pass filter 高通滤波器：high pass filter带通滤波器：band pass filter 带阻滤波器：band stop filter零阶保持信号:zero order hold signal 平滑：smooth采样周期：sampling period 频率分量:frequency elements图像处理：image processing 传感器：sensor电压：voltage 电流：current•anti-aliasing filter 抗混叠滤波器•anti-imaging filter 抗镜像滤波器•sampling interval 采样间隔•=sampling period 采样周期•sampling frequency 采样频率•=sampling rate 采样速率•sampling theorem 采样定理•Nyquist sampling rate 奈奎斯特采样率•Nyquist frequency 奈奎斯特频率•Nyquist range 奈奎斯特范围•oversampling 过采样undersampling 欠采样•quantization step 量化步长quantization noise量化噪声•bit rate 比特率•数字函数：digital function 合成函数：composite function •二维数字信号：two-dimensional digital signal•语音信号：speech signal 量化方案：quantization scheme •脉冲函数：impulse function 单位脉冲函数：unit impulse function •阶跃函数：step function 幂函数:power function •指数函数: exponential function 正弦函数：sine function•余弦函数：cosine function 复平面：complex plain•欧拉恒等式：Euler’s identity 模拟频率：analog frequency •数字频率:digital frequency 采样间隔：sampling interval •相移：phase shift 像素：pixel•灰度级：gray scale•roll-off 滚降gain 增益•pass band 通带stop band 阻带•bandwidth 带宽linear system 线性系统•superposition 叠加原理time-invariant 时不变•causal system因果系统difference equation差分方程•filter coefficient滤波器系数recursive filter 递归滤波器•nonrecursive filter 非递归滤波器finite word length effect有限字长效应•impulse response 脉冲响应infinite impulse response （IIR)无限脉冲响应•finite impulse response (FIR)有限脉冲响应•moving average filter 滑动平均滤波器•step response 阶跃响应•z transform z变换•region of convergence 收敛域•inverse z transform 逆z变换•transfer function 传输函数•partial fraction expansion 部分分式展开•cover-up method 覆盖法•zero 零点pole 极点•marginally stable 临界稳定unstable 不稳定•傅立叶变换：Fourier Transform•滤波器形状：filter shape•频率响应:frequency response•频率特性：frequency characteristics•离散时间傅立叶变换：Discrete Time Fourier Transform•幅度响应：magnitude response•相位响应：phase response•传输函数：transfer function•相位差：phase difference•采样频率：sampling frequency•white noise 白噪声•magnitude spectrum 幅度频谱•phase spectrum 相位频谱•discrete Fourier series（DFS)离散傅里叶级数•有限脉冲响应滤波器：finite impulse response filter•无限脉冲响应滤波器：infinite impulse response filter•相位失真：phase distortion•理想低通滤波器：idle low pass filter•窗函数：window function 稳定性：stability•通带波纹：pass band ripple•阻带波纹：stop band ripple•通带边缘频率:pass band edge frequency•过渡带宽度：transition width•矩形窗：Rectangular Window•汉宁窗：Hanning Window•哈明窗:Hamming Window•布莱克曼窗:Blackman Window•凯塞窗:Kaiser Window•项数:number of terms 衰减:attenuation•增益:gain•采样频率:sampling frequency•infinite impulse response filter(IIR)无限脉冲响应滤波器•bilinear transformation 双线性变换•prewarping equation 预扭曲方程•Butterworth filter 巴特沃斯滤波器•Chebyshev Type I filter 切比雪夫I 型滤波器•Chebyshev Type II filter 切比雪夫II 型滤波器•elliptic filter 椭圆滤波器•Impulse invariance method 脉冲响应不变法•discrete Fourier transform (DFT) 离散傅里叶变换•inverse DFT 逆离散傅里叶变换•phase spectrum 相位频谱•frequency spacing频率间隔•resolution分辨率•smear模糊•spectral leakage 频谱泄漏•spectrogram频谱图•fast Fourier transform (FFT) 快速傅里叶变换•butterfly 蝶形。
外文翻译--数字滤波器的仿真与实现
毕业设计(论文)外文资料翻译院系电子信息工程专业电子信息工程学生姓名班级学号外文出处百度文库附件：1.外文资料翻译译文（约3000汉字）；2.外文资料原文(与课题相关的1万印刷符号左右)。
英文原文The simulation and the realization of the digital filter With the information age and the advent of the digital world, digital signal processing has become one of today's most important disciplines and door technology. Digital signal processing in communications, voice, images, automatic control, radar, military, aerospace, medical and household appliances, and many other fields widely applied. In the digital signal processing applications, the digital filter is important and has been widely applied.1、figures Unit on :Analog and digital filtersIn signal processing, the function of a filter is to remove unwanted parts of the signal, such as random noise, or to extract useful parts of the signal, such as the components lying within a certain frequency range.The following block diagram illustrates the basic idea.There are two main kinds of filter, analog and digital. They are quite different in their physical makeup and in how they work. An analog filter uses analog electronic circuits made up from components such as resistors, capacitors and op amps to produce the required filtering effect. Such filter circuits are widely used in such applications as noise reduction, video signal enhancement, graphic equilibrium in hi-fi systems, and many other areas. There are well-established standard techniques for designing an analog filter circuit for a given requirement. At all stages, the signal being filtered is an electrical voltage or current which is the direct analogue of the physical quantity (e.g. a sound or video signal or transducer output) involved. A digital filter uses a digital processor to performnumerical calculations on sampled values of the signal. The processor may be a general-purpose computer such as a PC, or a specialized DSP (Digital Signal Processor) chip. The analog input signal must first be sampled and digitized using an ADC (analog to digital converter). The resulting binary numbers, representing successive sampled values of the input signal, are transferred to the processor, which carries out numerical calculations on them. These calculations typically involve multiplying the input values by constants and adding the products together. If necessary, the results of these calculations, which now represent sampled values of the filtered signal, are output through a DAC (digital to analog converter) to convert the signal back to analog form.Note that in a digital filter, the signal is represented by a sequence of numbers, rather than a voltage or current.The following diagram shows the basic setup of such a system.Unit refers to the input signals used to filter hardware or software. If the filter input, output signals are separated, they are bound to respond to the impact of the Unit is separated, such as digital filters filter definition. Digital filter function, which was to import sequences X transformation into export operations through a series Y.According to figures filter function 24-hour live response characteristics, digital filters can be divided into two, namely, unlimited long live long live the corresponding IIR filter and the limited response to FIR filters. IIR filters have theadvantage of the digital filter design can use simulation results, and simulation filter design of a large number of tables may facilitate simple. It is the shortcomings of the nonlinear phase; Linear phase if required, will use the entire network phase-correction. Image processing and transmission of data collection is required with linear phase filters identity. And FIR linear phase digital filter to achieve, but an arbitrary margin characteristics. Impact from the digital filter response of the units can be divided into two broad categories : the impact of the limited response (FIR) filters, and unlimited number of shocks to (IIR) digital filters.FIR filters can be strictly linear phase, but because the system FIR filter function extremity fixed at the original point, it can only use the higher number of bands to achieve their high selectivity for the same filter design indicators FIR filter called band than a few high-IIR 5-10 times, the cost is higher, Signal delay is also larger. But if the same linear phase, IIR filters must be network-wide calibration phase, the same section also increase the number of filters and net work complexity. FIR filters can be used the recursive method, not in a limited precision of a shock, and into the homes and quantitative factors of uncertainty arising from the impact of errors than IIR filter small number, and FIR filter can be used FFT algorithms, the computational speed. But unlike IIR filter can filter through the simulation results, there is no ready-made formula FIR filter must use computer-aided design software (such as MATLAB) to calculate. So, a broader application of FIR filters, and IIR filters are not very strict requirements on occasions.Unit from sub-functions can be divided into the following four categories :(1) Low-filter (LPF);(2) high-filter (HPF);(3) belt-filter (BPF);(4) to prevent filter (BSF).The following chart dotted line for the ideals of the filter frequency characteristics :2、MATLAB introducedMATLAB is a matrix laboratory (Matrix Laboratory) is intended. In addition to an excellent value calculation capability, it also provides professional symbols terms, word processing, visualization modeling, simulation and real-time control functions. MATLAB as the world's top mathematical software applications, with a strong engineering computing, algorithms research, engineering drawings, applications development, data analysis and dynamic simulation, and other functions, in aerospace, mechanical manufacturing and construction fields playing an increasingly important role. And the C language function rich, the use of flexibility, high-efficiency goals procedures. High language both advantages aswell as low level language features. Therefore, C language is the most widely used programming language. Although MATLAB is a complete, fully functional programming environment, but in some cases, data and procedures with the external environment of the world is very necessary and useful. Filter design using MATLAB, could be adjusted with the design requirements and filter characteristics of the parameters, visual simple, greatly reducing the workload for the filter design optimization.In the electricity system protection and secondary computer control, many signal processing and analysis are based on are certain types sinusoidal wave and the second harmonics of the system voltage and current signals (especially at D process), are mixed with a variety of complex components, the filter has been installed power system during the critical components. Current computer protection and the introduction of two digital signal processing software main filter. Digital filter design using traditional cumbersome formula, the need to change the parameters after recalculation, especially in high filters, filter design workload. Uses MATLAB signal processing boxes can achieve rapid and effective digital filter design and simulation.MATLAB is the basic unit of data matrix, with its directives expression mathematics, engineering, commonly used form is very similar, it is used to solve a problem than in MATLAB C, Fortran and other languages End precision much the same thing. The popular MATLAB 5.3/Simulink3.0 including hundreds of internal function with the main pack and 30 types of tool kits (Toolbox). kits can be divided into functional tool kits and disciplines toolkit. MATLAB tool kit used to expand the functional symbols terms, visualization modeling simulation, word processing and real-time control functions. professional disciplines toolkit is a stronger tool kits, tool kits control, signal processing tool kit, tool kits, etc. belonging to such communicationsMATLAB users to open widely welcomed. In addition to the internal function, all the packages MATLAB tool kits are readable document and the document could be amended, modified or users through original program the construction of new procedures to prepare themselves for kits.3、Digital filter designDigital filter design of the basic requirementsDigital filter design must go through three steps :(1) Identification of indicators : In the design of a filter, there must be some indicators. These indicators should be determined on the basis of the application. In many practical applications, digital filters are often used to achieve the frequency operation. Therefore, indicators in the form of general jurisdiction given frequency range and phase response. Margins key indicators given in two ways. The first is absolute indicators. It provides a function to respond to the demands of the general application of FIR filter design. The second indicator is the relative indicators. Its value in the form of answers to decibels. In engineering practice, the most popular of such indicators. For phase response indicators forms, usually in the hope that the system with a linear phase frequency bands human. Using linear phase filter design with the following response to the indicators strengths：①it only contains a few algorithms, no plural operations；②there is delay distortion, only a fixed amount of delay; ③the filter length N (number of bands for N-1), the volume calculation for N/2 magnitude.(2) Model approach : Once identified indicators can use a previous study of the basic principles and relationships, a filter model to be closer to the target system.(3) Achieved : the results of the above two filters, usually by differential equations, system function or pulse response to describe. According to this description of hardware or software used to achieve it.4、Introduction of DSPToday, DSP is widely used in the modern techno logy and it has been the key part of many products and played more and mo re important role in our daily life Recently, Northwestern Poly technical University Aviation Microelectronic Center has completed the design of digital signal processor co re NDSP25, which is aiming at TM S320C25 digital signal processor of Texas Instrument TM S320 series. By using top 2dow n design flow NDSP25 is compatible with instruction and interface timing of TM S320C25.Digital signal processors (DSP) is a fit for real-time digital signal processing for high-speed dedicated processors, the main variety used for real-time digital signal processing to achieve rapid algorithms. In today's digital age background, the DSP has become the communications, computer, and consumer electronics products, and other fields based device.Digital signal processors and digital signal processing is inseparably, we usually say "DSP" can also mean the digital signal processing (Digital Signal Processing), is that in this digital signal processors Lane. Digital signal processing is a cover many disciplines applied to many areas and disciplines, refers to the use of computers or specialized processing equipment, the signals in digital form for the collection, conversion, recovery, valuation, enhancement, compression, identification, processing, the signals are compliant form. Digital signal processors for digital signal processing devices, it is accompanied by a digital signal processing to produce. DSP development process is broadly divided into three phases : the 20th century to the 1970s theory that the 1980s and 1990s for the development of products. Before the emergence of the digital signal processing in the DSP can only rely on microprocessors (MPU) to complete. However, the advantage of lower high-speed real-time processing can not meet the requirements. Therefore, until the 1970s, a talent made based DSP theory and algorithms. With LSI technology development in 1982 was the first recipient of the world gave birth to the DSP chip. Years later, the second generation based on CMOS工艺DSP chips have emerged. The late 1980s, the advent of the third generation of DSP chips. DSP is the fastest-growing 1990s, there have been four successive five-generation and the generation DSP devices. After 20 years of development, the application of DSP products has been extended to people's learning, work and all aspects of life and gradually become electronics products determinants.中文翻译数字滤波器的仿真与实现随着信息时代和数字世界的到来，数字信号处理已成为当今一门极其重要的学科和技术领域。
IIR数字滤波器中英文对照外文翻译文献
(文档含英文原文和中文翻译)中英文资料对照外文翻译IIR Digital Filter DesignAn important step in the development of a digital filter is the determination of a realizable transfer function G(z) approximating the given frequency response specifications. If an IIR filter is desired,it is also necessary to ensure that G(z) is stable. The process of deriving the transfer function G(z) is called digital filter design. After G(z) has been obtained, the next step is to realize it in the form of a suitable filter structure. In chapter 8,we outlined a variety of basic structures for the realization of FIR and IIRtransfer functions. In this chapter,we consider the IIR digital filter design problem. The design of FIR digital filters is treated in chapter 10.First we review some of the issues associated with the filter design problem. A widely used approach to IIR filter design based on the conversion of a prototype analog transfer function to a digital transfer function is discussed next. Typical design examples are included to illustrate this approach. We then consider the transformation of one type of IIR filter transfer function into another type, which is achieved by replacing the complex variable z by a function of z. Four commonly used transformations are summarized. Finally we consider the computer-aided design of IIR digital filter. To this end, we restrict our discussion to the use of matlab in determining the transfer functions.9.1 preliminary considerationsThere are two major issues that need to be answered before one can develop the digital transfer function G(z). The first and foremost issue is the development of a reasonable filter frequency response specification from the requirements of the overall system in which the digital filter is to be employed. The second issue is to determine whether an FIR or IIR digital filter is to be designed. In the section ,we examine these two issues first . Next we review the basic analytical approach to the design of IIR digital filters and then consider the determination of the filter order that meets the prescribed specifications. We also discuss appropriate scaling of the transfer function.9.1.1 Digital Filter SpecificationsAs in the case of the analog filter,either the magnitude and/or the phase(delay) response is specified for the design of a digital filter for most applications. In some situations, the unit sample response or step response may be specified. In most practical applications, the problem of interest is the development of a realizable approximation to a given magnitude response specification. As indicated in section 4.6.3, the phase response of the designed filter can be corrected by cascading it with an allpass section. The designof allpass phase equalizers has received a fair amount of attention in the last few years. We restrict our attention in this chapter to the magnitude approximation problem only. We pointed out in section 4.4.1 that there are four basic types of filters,whose magnitude responses are shown in Figure 4.10. Since the impulse response corresponding to each of these is noncausal and of infinite length, these ideal filters are not realizable. One way of developing a realizable approximation to these filter would be to truncate the impulse response as indicated in Eq.(4.72) for a lowpass filter. The magnitude response of the FIR lowpass filter obtained by truncating the impulse response of the ideal lowpass filter does not have a sharp transition from passband to stopband but, rather, exhibits a gradual "roll-off."Thus, as in the case of the analog filter design problem outlined in section 5.4.1, the magnitude response specifications of a digital filter in the passband and in the stopband are given with some acceptable tolerances. In addition, a transition band is specified between the passband and the stopband to permit the magnitude to drop off smoothly. For example, the magnitude )(ωj e G of a lowpass filter may be given as shown in Figure7.1. As indicated in the figure, in the passband defined by 0p ωω≤≤, we require that the magnitude approximates unity with an error of p δ±,i.e.,p p j p for e G ωωδδω≤+≤≤-,1)(1.In the stopband, defined byπωω≤≤s ,we require that the magnitude approximateszero with an error of i s ,δ.e., ,)(s j e G δω≤ for πωω≤≤s .The frequencies p ω and s ω are , respectively, called the passband edge frequency and the stopband edge frequency. The limits of the tolerances in the passband and stopband,p δ and s δ, are usually called the peak ripple values. Note that the frequency response )(ωj e G of a digital filter is a periodic function of ω,and the magnitude response of a real-coefficient digital filter is an even function ofω. As a result, the digital filter specifications are given only for the range πω≤≤0.Digital filter specifications are often given in terms of the loss function,)(log 20)(10ωωζj e G -=, in dB. Here the peak passband ripple p α and theminimum stopband attenuation s α are given in dB,i.e., the loss specifications of a digital filter are given bydB p p )1(log 2010δα--=,dB s s )(log 2010δα-=. 9.1 Preliminary ConsiderationsAs in the case of an analog lowpass filter, the specifications for a digital lowpass filter may alternatively be given in terms of its magnitude response, as in Figure 7.2. Here the maximum value of the magnitude in the passband is assumed to be unity, and the maximum passband deviation, denoted as 1/21ε+,is given by the minimum value of the magnitude in the passband. The maximum stopband magnitude is denoted by 1/A.For the normalized specification, the maximum value of the gain function or the minimum value of the loss function is therefore 0 dB. The quantitymax α given bydB )1(log 20210max εα+= Is called the maximum passband attenuation. Forp δ<<1, as is typically the case, it can be shown thatp p αδα2)21(log 2010max ≅--≅The passband and stopband edge frequencies, in most applications, are specified in Hz, along with the sampling rate of the digital filter. Since all filter design techniques are developed in terms of normalized angular frequencies p ω and s ω,the sepcified critical frequencies need to be normalized before a specific filter design algorithm can be applied. Let T F denote the sampling frequency in Hz, and F P and F s denote, respectively,the passband and stopband edge frequencies in Hz. Then the normalized angular edge frequencies in radians are given byT F F F F p Tp T p p ππω22==Ω=T F F F F s Ts T s s ππω22==Ω= 9.1.2 Selection of the Filter Type The second issue of interest is the selection of the digital filter type,i.e.,whether an IIR or an FIR digital filter is to be employed. The objective of digital filter design is to develop a causal transfer function H(z) meeting the frequency response specifications. ForIIR digital filter design, the IIR transfer function is a real rational function of 1-z .H(z)=NMdNz z d z d d pMz z p z p p ------++++++++......2211022110 Moreover, H(z) must be a stable transfer function, and for reduced computational complexity, it must be of lowest order N. On the other hand, for FIR filter design, the FIRtransfer function is a polynomial in 1-z :∑=-=N n n zn h z H 0][)(For reduced computational complexity, the degree N of H(z) must be as small as possible. In addition, if a linear phase is desired, then the FIR filter coefficients must satisfy the constraint:][][N n h n h -±=T here are several advantages in using an FIR filter, since it can be designed withexact linear phase and the filter structure is always stable with quantized filter coefficients. However, in most cases, the order N FIR of an FIR filter is considerably higher than the order N IIR of an equivalent IIR filter meeting the same magnitude specifications. In general, the implementation of the FIR filter requires approximately N FIR multiplications per output sample, whereas the IIR filter requires 2N IIR+1 multiplications per output sample. In the former case, if the FIR filter is designed with a linear phase, then the number of multiplications per output sample reduces to approximately (N FIR+1)/2. Likewise, most IIR filter designs result in transfer functions with zeros on the unit circle,N with all of the zeros on the unit and the cascade realization of an IIR filter of orderIIRN+3)/2] multiplications per output sample. It has been shown that circle requires [(3IIRfor most practical filter specifications, the ratio N FIR/N IIR is typically of the order of tens or more and, as a result, the IIR filter usually is computationally more efficient[Rab75]. However ,if the group delay of the IIR filter is equalized by cascading it with an allpass equalizer, then the savings in computation may no longer be that significant [Rab75]. In many applications, the linearity of the phase response of the digital filter is not an issue,making the IIR filter preferable because of the lower computational requirements.9.1.3 Basic Approaches to Digital Filter DesignIn the case of IIR filter design, the most common practice is to convert the digital filter specifications into analog lowpass prototype filter specifications, and then to transform it into the desired digital filter transfer function G(z). This approach has been widely used for many reasons:(a) Analog approximation techniques are highly advanced.(b) They usually yield closed-form solutions.(c) Extensive tables are available for analog filter design.(d) Many applications require the digital simulation of analog filters.In the sequel, we denote an analog transfer function as)()()(s D s P s H a a a =, Where the subscript "a" specifically indicates the analog domain. The digital transfer function derived form H a (s) is denoted by)()()(z D z P z G = The basic idea behind the conversion of an analog prototype transfer function H a (s) into a digital IIR transfer function G(z) is to apply a mapping from the s-domain to the z-domain so that the essential properties of the analog frequency response are preserved. The implies that the mapping function should be such that(a) The imaginary(j Ω) axis in the s-plane be mapped onto the circle of the z-plane.(b) A stable analog transfer function be transformed into a stable digital transfer function.To this end,the most widely used transformation is the bilinear transformation described in Section 9.2.Unlike IIR digital filter design,the FIR filter design does not have any connection with the design of analog filters. The design of FIR filter design does not have any connection with the design of analog filters. The design of FIR filters is therefore based on a direct approximation of the specified magnitude response,with the often added requirement that the phase response be linear. As pointed out in Eq.(7.10), a causal FIR transfer function H(z) of length N+1 is a polynomial in z -1 of degree N. The corresponding frequency response is given by∑=-=N n n j j en h e H 0][)(ωω.It has been shown in Section 3.2.1 that any finite duration sequence x[n] of length N+1 is completely characterized by N+1 samples of its discrete-time Fourier transfer X(ωj e ). As a result, the design of an FIR filter of length N+1 may be accomplished by finding either the impulse response sequence {h[n]} or N+1 samples of its frequency response )H(e j ω. Also,to ensure a linear-phase design, the condition of Eq.(7.11) must be satisfied. Two direct approaches to the design of FIR filters are the windowed Fourier series approach and the frequency sampling approach. We describe the former approach in Section 7.6. The second approach is treated in Problem 7.6. In Section 7.7 we outline computer-based digital filter design methods.作者：Sanjit K.Mitra国籍：USA出处：Digital Signal Processing -A Computer-Based Approach 3eIIR数字滤波器的设计在一个数字滤波器发展的重要步骤是可实现的传递函数G（z）的接近给定的频率响应规格。
本科毕设滤波器方面的中英文翻译
Abstract:A modification of the filter design described in Arcetri Technical Report N5/2002 is presented. The overall structure is similar, but the the digital local oscillator is moved after the rst lter and after the frequency decimation. With this modification the design proposed here presents some advantage in terms of gate usage and spectral dynamic range.1. IntroductionIn the hybrid correlator proposed for ALMA, a large fraction of the total logic and correlator cost is represented by the digital filter bank. Since the circuit is replicated in a large number of copies, even a modest reduction in complexity may have a relatively large impact on overall system cost. In report [8] a two stage tunable filter has been presented. The design, shown in fig. 2, is composed by a complex oscillator and mixer, a first decimating broad filter, a second sharp filter, and a complex to real conversion stage. The first filter has a road transition region, and thus a short FIR response time (128 taps).The second filter operates at the decimated frequency, allowing for a long response, and a sharp transition region, with only 64 taps. Both filters have complex samples and real coefficients.Figure 1: Structure of the original digital BBCThe signal is down converted by a digital LO/mixer, filtered by a first broad filter,re-quantized to 10 bit, filtered by a second sharp filter,converted to real representation, rescaled and re-quantized to a final resolution of 3 or 4 bits. Total power meters are used tomonitor signal level.A modified architecture (fig. 2), with almost identical performance and response, may be obtained moving the LO/mixer after the first filter. The first filter has a band pass corresponding to the desired portion of the input spectrum (without restrictions due to decimation), and is obtained from a the low pass prototype used in the previous approach, translated by a frequency equal to the LO setting.Figure 2: Structure of the modified digital BBCThe signal is first filtered by the broad filter, decimated, and then frequency converted by a full complex mixer. The second filter and output section is identical to the previous case. The filter is thus depending on the sub band position, and its coefficients must be reloaded every time the tuning change. To avoid aliasing, it must discriminate between positive and negative frequencies, It has therefore real input, complex (hermitian) tap coefficients, and complex output. The mixer/LO is fully complex, with 4 multipliers and 2 adders. The second filter and complex-to-real conversion stage is identical to the previous design.The main advantage of this design is that the mixer operates at the decimated frequency. Since a time multiplexed mixer is composed of 32 identical multipliers, even considering for the increased complexity in the multi-bit complex multiplier this results in a drastic simplification. It is possible to use a much better multiplier,thus increasing the global quantization efficiency (although by a small value, about 0.5%) and spurious free dynamic range.Another advantage is that the first filter operates on the 3-bit input data representation, instead of the 6-bit mixer output. This reduces the total filter size by a considerable amount (30-40%).A further advantage is that the mixer does not see any DC component that can beproduced by an offset in the sampler thresholds, as this is effectively filtered by the first filter. This DC component is equivalent to a strong monochromatic line, and may produce undesired spurs as it beats with the LO harmonics.2 Theory of operationFigure 3: Spectral processing exampleFor readability, a x8 multiplexing factor has been assumed, instead of x32. From top: (a) Input real signal, divided into 10 sub bands; (b) Undecimated and (c) decimated broad filter output; (d) Mixer output; (e) Sharp filter output.Signal processing for an hypothetical 1:8 decimated signal is shown in fig. 3 The real input, divided in 10 overlapped sub-bands, is shown in (a). The broad filter selects sub-band 6, with guard bands from sub-bands 5 and 7 (b). After decimation, (c) the band of interest occupies half the complex decimated bandwidth, with sub-bands 5 and 7 aliased in the remaining half. In the particular case, the band of interest folds from positive back to negative frequencies. After complex mixing the band of interest is centered on frequency zero (d), and the unwanted sub-bands are rejected by the sharp filter (e).The processing of a real simulated signal, with the desired 1:32 decimation factor, is shown in fig. 4 and 5.The signal is the same used in the previous report. The complex spectrum of the (real) input signal is shown in fig. 4a. The signal is composed of white noise, a strong out-of-band tone (-20dB), and a weaker (-30dB) in-band tone. The simulated signal is 2.5 ms long.After filtering, the signal is shown in fig. 4b. Only one side of the complex spectrum is preserved, thus avoiding undesired aliasing in the decimation operation.After decimation, the signal has the spectrum shown in fig. 4c. Even if the spectrum folds from positive to negative frequencies, no undesired alias of the strong input line can be seen.Figure 4: Spectral processing of a simulated signalFrom top: (a) Input real signal; (b) Undecimated and (c) decimated broad filter output Graphs have a logarithmic (dB) scale.The complex mixer rotates the filtered spectrum in order to present the desired passband to the sharp filter centered on frequency zero (fig. 5a). The low pass sharp filter then selects the desired passband and removes the undesired passbands (5b). This signal is then converted to real (5c), and re-quantized for correlation. The filter real output is exactly equal to that of the filter described in the previous report (apart from quantization effects).2.1 Broad band filterThe filter is a complex passband (real samples, complex coefficients) derived by the low pass prototype used in the previous design. The prototype has a bandpass equal to 1/64 the input bandwidth, and a guard region twice as large. After decimation, both the complexresponse and the two guard bands have a total width of 1/32 the initial band, or 1/2 the decimated complex band. The two guard bands fold in the same region of thedecimated band.The prototype is shifted by the desired center frequency. For 34 sub bands, the rotation for channel i(i =0,33) is (i-05)34*2 GHz, but arbitrary shift is possible. Thus, filter tuning is accomplished by calculation of a new set of coe?cients (no filter optimization is necessary) and reloading of the coe?cient memory.The real part of the filter is symmetric, while the complex one is antisymmetric. In both cases, filter structure may exploit this symmetry to reduce the number of multiplications. Filter conceptual schematic for the real (symmetric) branch is shown in fig 6. The demultiplexed inputs are fied to 32 identical groups of four taps each. Direct and inverse taps are summed together before multiplication. Folding and summing corresponding samples may present problems in a few-bit representation. The input samples are not actual values, but arbitrary codes. Summing the codes obviously does not work. The code is neither monotonic, nor equispaced. The signal must therefore be converted to a monotonic, equispaced code before the filter. This imposes a limitation on the possible quantization codes, resulting in a slightly reduction in quantization efficiency. A equispaced code (values 1, 3, 5, 7) has an quantization loss of 3.??%, against a loss.Figure 5: Spectral processing of a simulated signalFrom top: (a) mixer output; (b) Sharp filter output; (c)Real signal sent to the correlator.All plots are on a logarithmic vertical scale.The result of the sum of two codes (1, 3, 5, 7) can be any even number from -14 to 14, representable with a 4 bit, signed quantity. For 8 bit signed coe?cients, product size is 11 bit. Filter multipliers are therefore implemented with 16x11 bit RAM blocks.The filter has been designed using the filter from the previous design as a low-pass template, and multiplying each coefficient by the appropriate exponential.The same considerations about coefficient precision truncation apply for here. The actual filter shape,however, depends very much on the local oscillator setting. Truncation is an intrinsically nonlinear procedure, and only statistical properties of the filter shape can be anticipated. An alternative approach would be to use a nonlinear minimization program to adjust filter coefficients on the desired shape after filter rotation, instead of blindly truncate them. This approach would probably give a better stop band rejection (by 2-3 dB), at the expense of a much higher computational effort during filter reprogramming.2.2 Complex Local OscillatorThe local oscillator is greatly simpli?ed with respect to the previous approach. It is composed by a DDS.register, similar to the previous one, that generates a 10 bit phase value. No phase offset is needed, apart from the 90/180 degree phase switching. The 10 bit value is fed to asine/cosine lookup table, that produces a high resolution sine and cosine value. A complex multiplier, implemented with four hardwired multipliers and two adders, compute the expression y(t) = x(t)exp(2j t).The mixer does not select the bandwidth, it must only compensate for the unwanted rotation of the filtered band, and for its possible folding from positive to negative frequencies (as in the example shown in fig. 4). The complex mixing rotates the decimated band in order to have the frequency scale monotonically ordered from-625 MHz to +625 MHz. After conversion, the desired band is centered around frequency zero, and therefore.Figure 6: Coarse FIR schematicSignals from I and Q mixers are multiplied by coefficient taps in LUT tables. Input is from 32 time multiplexed streams, output is to 2 (I and Q) streams.can be filtered by alow-pass filter.The local oscillator value is programmed to the desired LO frequency modulus 125 MHz. The remaining part of the LO frequency affects only first filter coefficients, as bandwidth selection is done in this filter.The phase quantizationstep affects LO harmonicscontent. With 1024phase bins, the first harmonic appears Atharmonic number 1024,with an amplitude of approximately-60dB. Amplitude quantization in the sine/cosine table also generates harmonics, but with 8 bitsine/cosine representation the spur free dynamic range is around -70 dB.To reduce harmonic content, a small (few phase bins) pseudo-random noise can be added to the DDS phase.The resulting phase jitter is of the order of 1 degree, but is multiplied by the harmonic number, completely washing out the harmonics due to phase quantization.The lookup table can be simplified if only first quadrant values are stored, and the sign is treated separately. In this way, lookup table size is reduced to 1/4, and one more bit is available for the result.2.3 Sharp lter and output sectionThis section is identical to the design described in [8]Figure7: Complex localoscillator. A DDS register generatesa phasevalueSine andcosine values aregenerated in a lookup table. The complex multiplication is implemented in 4 hardwired multipliers and two adders.3 Considerations on FPGA resource usageImplementation of this filter require considerably less resources than the previous design. The broad filter has 3 bit input, instead of 6. This requires about half the resources in terms of configurable blocks, lookup tables. The saving in the adder chain is not so high, since most of the adder tree size is dictated by the coefficients size, not by the samples size. The lookup tables must be writable. This increases its complexity,especially in terms of routing resources. The mixer multiplier must be implemented using hard multipliers, not lookup tables. A single large look up table to hold sine/cosine values is still needed. Especially for Altera FPGAs, this is a large advantage, as these chips have smaller RAM blocks, but also one or two large RAMs.Re-tuning the band is relatively slower, the filter has no capability for frequency hopping. This is not a requirement, and tap reloading is in any case faster than for a full 1024 tap filter. Some intelligence is needed in the control processor to recalculate filter taps from thelow-pass prototype, but this is within the capabilities of any current microprocessor.摘要:它是一种Arcetri技术报告提出修改方案并设计的滤波器。
外文文献翻译--- 用于近似处理的低能耗数字滤波器
毕业设计科技文献翻译《Low-Power Digital Filtering Using Approximate Processing》《用于近似处理的低功耗数字滤波器》姓名专业学号班级指导教师2010年 4月Ⅰ. INTRODUCTIONTECHNIQUES for reducing power consumption have bemultimedia devices. Since digital signal processing is pervasive in such applications , it is useful to consider how algorithmic approaches may be exploited in construction low-power solution.A significant number of DSP function involve frequency-selective digital filtering in which the goal is to reject one or more frequency bands while keeping the remaining portions of the input spectrum largely unaltered. Examples include lowpass filtering for signal upsampling and downsampling , bandpass filtering for subband coding, and lowpass filtering for frequency-division multiplexing and demultiplexing. The exploration of low-power solutions in these areas is therefore of significant interest.To first order, the average power consumption, P, of a digital system may be expressed as∑=isddiifVCNP2(1)Where Ci is the average capacitance switched per operation of type i (corresponding to addition, multiplication, storage, or bus accesses), Ni is the number of operation of type i performed per sample, Vdd is the operating supply voltage, and fs is the sample frequency.Real-time digital filtering is an example of a class of applications in which there is no advantage in exceeding a bounded computation rate. For such applications, an architecture-driven voltage scaling approach has previously been developed in which parallel and pipelined architectures can be used to compensate for increased delays at reduced voltages . This strategy can result in supply voltages in the 1 to 1.5 V ra-nge by using conventional CMOS technology. Power supply voltages can be further scaled using reduced threshold devices. Circuits operating at power supply voltages as low as 70 mV (at 300 K) and 27 mV (at 77 K) have been demonstrated .Once the power supply voltage is scaled to the lowest possible level, the goal is to minimize the switched capacitance at all levels of the design abstraction. At the logic level, for example, modules can be shut down at a very low level basedon signal values. Arithmetic structures (e.g., ripple carry versus carry select) can also be optimized to reduce transi-tion activity. Architectural techniques include optimizing the sequencing of operations to mini mize transition activity, avoiding time-multiplexed architectures which destroy sig-nal correlations, using balanced paths to minimize glitching transitions, etc. At the algorithmic level, the computational complexity or the data representation can be optimized for low power .Another approach to reduce the switched capacitance is to lower N,. Efforts have been made to minimize N, by intelli-gent choice of algorithm, given a particular signal processing task. In the case of conventional filter design, the filter order is fixed based on worst case signal statistics,which is inefficient if the worst case seldom occurs. More flexibility may be incorporated by using adaptive filtering algorithms, which are characterized by their ability to dynamically adjust the processing to thedata by employing feedback mechanisms. In this paper, we illustrate how adaptive filtering concepts may be exploited to develop low-power implementations for digital filtering.Adaptive filtering algorithms have generally been used to dynamically change the values of the filter coefficients, while maintaining a fixed filter order. In contrast, our approach nvolves the dynamic adjustment of the filter order. This approach leads to filtering solutions in which the stopband energy in the filter output may be kept below a specified hreshold while using as small a filter order as possible. Since power consumption is proportional to filter order, our approach achieves power reduction with respect to a fixed-order filter whose output is similarly guaranteed to have stopband energy below the specified threshold. Power reduction is achieved by dynamically minimizing the order of the digital filter.The idea of dynamically reducing cost (in our case, power consumption) While maintaining a desired level of output quality (in our case, stopband energy in the filter output) emanates from the concept of approximate processing in computer science. While approximate processing concepts may be used to describe a variety of existing techniques in digital signal processing processing (DSP), communications, and other areas, there has recently been progress in formally using these concepts to develop new DSP technique . Since our adaptive filtering technique falls into this category, we refer to our approach as adaptive approximate filtering, or simply approximate filtering.Ⅱ. DIGITAL FILTERING TRADE-OFFSA frequency-selective digital filter may have either a finite impulse response (FIR) or an infinite impulse response (IIR). It is well known that IIR filters use fewer taps than FIR filters in order to provide the same amount of attenuation in the stopband region. However, IIR filters introduce nonlinear frequency dispersion in the output signals which is unacceptable in some application. For such cases, it is desirable to use symmetric FIR filters because of there linear phase characteristic.An important family of symmetric FIR filters corresponds to the symmetric windowing of the impulse responses of corresponding ideal filters. For example, a lowpass filter of this type has an impulse response given by[][]n nn n h c πωωsin = (2)Where []n ω is a symmetric N-point window. This filter has cutoff frequency c ω and may be implemented using a tapped delay line with N taps. For the purposes of this paper, we refer to such a filter as having order N. In Fig. 1, we display the frequency response magnitudes for three different values of N when []n ω is a rectangular window and c ω=2π. It should be observed that the mean attenuationbeyond the cutoff frequencyc ω increase with filter order. Furthermore, with respect to a tapped delay-line implementation (see Fig. 2), the taps of the shorter Type I filter are subsets of the taps of the longer Type I filters. This ensures that if the filter order is to be decreased without changing the cutoff frequency, we can simply power down portions of the tapped delay line for the higher order filter. The price paid for such powering down is that the stopband attenuation of the filter decreases.Butterworth IIR filter are commonly used for performing frequency-selective filtering in applications where frequency dispersion is tolerable. The frequency response magnitudes of such filters do not suffer from the ripples which can be seen in the frequency response magnitudes for FIR filters. These IIR filters are commonly implemented as cascade interconnections of second-order sections, each of which consist of five multiplies and four delays, as shown in Fig.3. Also in Fig.3 is an illustration of a cascade structure for an eighth-order IIR filter as the cascade of four second-order section For the purposes of this paper, we consider the order of a Butterworth IIR filter to be equal to twice the number of second-orderFrequency,π normalizedFig. 1 Frequency response magnitudes for FIR filters of orders N=20,80,and 140Fig. 2 Tapped delay line of an FIR filter structure, and the powering down concept To preserve phase linearity, powering down must be applied at both ends of the structure.Fig. 3 Cascade implementation of an IIR filter structure. The detail of one of the second-order section is shown.sections in its cascade implementation., An interesting property of IIR Butterworth filters is that if the second-order sections are appropriately ordered, one may sequentially power down the later second-order sections and effectively decrease the net stopban attenuation of the filter.Ⅲ. ADAPTIVE APPROXIMATE FILTERINGI n this section we present the details of our approximate processing approach to low-power frequency-selective filter-ing. As discussed earlier, frequency-selective filters are used in applications where the goal is to extract certain frequency components from a signal while rejecting others. Suppose a signal, x[n], consists of apassband component, xp[n], and a stopband component,[]nxs. That is,[][][]n x n x n x s p += (3)If it were possible to cost-effectively measure the strength of the stopbandcomponent, []n x s , from observation of []n x , we could determine how muchstopband attenuation is needed at any particular time. When the energy in []n x sincreases, it is desirable to increase the stopband attenuation of the filter. This can be accomplished by using a higher-order filter. Conversely, the filter order may belowered when the energy in []n x s decreases. We have developed a practicaltechnique, based upon adaptive filtering principles, for dynamically estimating the energy fluctuations in the stopband component, []n x s , and using them to adjust the order of a frequency-selective FIR or IIR filter. As described in the previous section, the decreasein filter order enables the powering down of various segments of the filter structure. Powering down of the higher order taps has the effect of reducing the switched capacitance at the cost of decreasing the attenuation in the stopband. Assuming that the FIR delay line is implemented using SRAM, even the data shifting operation of the higher order taps can be eliminated through appropriate addressing schemes.Our overall technique is depicted in Fig. 4. The quantity d[n], which represents the energy differential between the input and the output, is obtained as[][][]n E n E n d y x -= (4)where[][]∑-=-=1021L k x k n x L n E (5)and[][]∑-=-=1021L k y k n y L n E (6)The filter order for sample period n, Order [n], is updated at each sample period. One approach for the update process is to choose Order [n] to be the smallest positiveinteger which guarantees that the stopband energy, Q[n], of the output signal will be maintained below a specified threshold y. Assuming that the stopband portion of the input spectrum is essentially flat,' the stopband energy in the output can be estimated as[][][][]n Order E n d n Q SB α= (7)where a is a proportionality constant, and Es~[lc] represents the stopband energy in the frequency response, Hk(w), of the lcth order filter. That is,[]()⎰=SB k SB d H k E ωωπ221(8)Fig. 4 Overview of approximate filtering strategywhere SB denotes the stopband region. Since for every sample period this approach requires an expensive search over the stored values of []k E SB , we have designed a more efficient strategy which incrementally updates the most recent filter order. In this case, we estimate the stopband energy in the output as[][][][]1-=n Order E n d n Q SB α (9)The decision rule for choosing Order [n] is then given by[][][][][][][]⎪⎩⎪⎨⎧-<--≤≤-->+-=δγγδγγn Q N n Order n Q n Order n Q N n Order n Order 00111 (10)where α, β,δ, and 0N are application-specific parameters. It should be notedthat the filter order is changed at most by 0N during each sample period..The parameters δ and 0N in (10) control the sensitivity of the time evolution of the filter order. The choice of the parameter L in (5) and (6) involves a trade-off between suppression of sensitivity to local fluctuations and preservation of the possible time-varying nature of the signal energy. For the case of FIR filters, we also observe that when the value of L is less than the maximum filter order, there is no extra storage required to compute[]n E x beyond that required for the filter implementation. On the other hand, excess storage is always required to update[]n E y .The arithmetic cost of the update process can be easily shown to involve five multiplications, five additions, one table lookup from a small memory module, and simple control. This cost is roughly equivalent to that of increasing the FIR filter order by five or the IIR filter order by two. This, for example, means that net power savings can be expected in the FIR case if for significant periods of time the dynamic FIR filter order decreases by more than five with respect to the maximum filter order. The overhead of multiplication is reduced to one multiplication instead of five per update if absolute value operations are used to compute[]n E x instead ofmagnitude-squared operations. Ⅳ. RESULTSIn the context of FIR filters, we have used simulations of our approximate filtering technique to show that reduction inFig. 5 FIR filter stopband energy, []k E SB versus filter order, k, for the rectangularwindow family of FIR filters.power consumption by an order of magnitude is achieved over fixed-order filter implementations when the stopband energy of the output signal is stipulated to remain below a given threshold γ. The context for most of these simulations is frequency-division demultiplexing of pairs of speech wave- forms.1) The Speech Signals: Each of the speech signals used in our simulations was sampled at 8 KHz and normalized to have maximum amplitude of unity. Each signal corresponds to a complete sentence with negligible silence at its beginning and end.2) Frequency-Division Multiplexing: Each digitized speech waveform was pre-filtered to have a maximum frequency of 1.5 KHz. A guard band of 1 KHz was used in multiplexing a reference speech signal (corresponding to the sentence, "That shirt seems much too long,") with each of the other speech signals. The reference signal always occupied the 0 to 1.5 KHz band, while the other signals always occupied the 2.5 KHz to 4 KHz band.3) The Demultiplexing: Demultiplexing involves lowpass filtering (cutoff frequency 2 KHz) to isolate the reference speech signal. The approximate filtering technique was used to perform this lowpass filtering for each of the 10 frequency- division multiplexed (FDM) signals. The parameter values in (10) were chosen to be10log γ=-40dB, δ=10γ, 20=N , L=100. (11)The family of FIR filters used in these simulations corresponds to (2) with w[n] rectangular. The values of []k E SB for this case are plotted in Fig. 5.4) Peqormance: In Table I we have listed various mea-sures obtained for the performance of the approximate filter as it was applied to each FDM signal. The first column contains the sentence number for the stopband component of the input signal. The second and third columns, respectively, list the minimum and maximum filter orders used by the approximate filter in each case. The final column shows the relative power consumption of the approximate filter withFig. 6 Evolution of filter order for an FDM example. Two plots are shown in thefigure. One shows the filter order as a function of time, While the other shows the stopband energy of the input signal as a function of time.respect to a fixed- order filter which is guaranteed to keep the stopband energy in the output below for all times. We observe that our adaptive technique reduces the average power consumption by a factor of 5.9.To gain further insight into the source for this power reduction, in Fig. 6 we illustrate the nature of the adaptation pedorrned by our technique in the case of one of the FDM signals. One of the curves shows the evolution of the filter order while the other curve showsthe energy profile of the stopband signal. Clearly, the variations in filter order roughly follow the energy variations of the stopband signal. In particular, the most power savings is achieved during the silence regions of the stopband signal.5) Speech Communication Implications: Longer periods of speech communication generally include significantly larger fractions of silence periods than an individual sentence. To factor this into our analysis, we repeated our simulations while inserting additional silence at the end of each speech signal. The average (over all 10 cases) of the relative power consumption is displayed in Fig. 7 as a function of the silence duration relative to the duration of the entire signal. As expected, the power reduction improves as the relative amount of silence is increased.Fig. 7 Filter performance versus percentage silence in stopband signal.Fig. 8 Filter order evolution for the approximate filtering subband decomposition example. The top plot shows the filter order as a function of time, Which tracks the input’s stopband component []nxs, which is shown in the bottom plot.6) Subband Coding: Data compression techniques for voice signals often use a binary tree-structured filterbank of highpass and lowpass filters, as depicted at the top of Fig.8. Each of these filters may be implemented using the proposed approximate filtering technique. To illustrate the potential for power savings in the first stage of the subband decomposition, an approximate FIR lowpass filter was applied to a speech signal, x[n], corresponding to the sentence, “That shirt seems much too long.” The time-varying FIR filter order used by our technique is shown in the top plot of Fig. 8.The bottom plot in Fig. 8 shows the input’s stopband component,[]nxs, todemonstrate that the filter order roughly tracks the stopband energy of the input signal.CONCLUSIONAn algorithm-based approach has been presented for ob-taining low-power implementations of important classes of IIR and FIR digital filters. In this approach, adaptive filtering and approximate processing concepts are combined to design digital filters which have the important property that the filter order can be dynamically varied in accordance with the stopband energy of the input signal. Simulations of the proposed technique using a variety of speech signals have英文翻译用于近似处理的低能耗数字滤波器英文作者：Jeffrey T. Ludwig, S. Hamid Nawab, and Anantha P. Chandrakasan翻译：李璐2010年4月摘要：我们提出一个算法来设计数字滤波器的低功率频率选择基于自适应滤波的概念和近似处理。
测试信号分析与处理专业英语词汇
第一章系统：system 信号：signal模拟信号：analog signal 数字信号：digital signal模/数转换：analog-to-digital conversion 频谱：spectrum数字滤波：digital filtering 滤波器：filter采样：sample 保持：hold数字代码：digital code 量化电平：quantization level 时域：time domain 频域：frequency domain低频：low frequency 高频：high frequency低通滤波器：low pass filter 高通滤波器：high pass filter带通滤波器：band pass filter 带阻滤波器：band stop filter零阶保持信号:zero order hold signal 平滑：smooth采样周期：sampling period 频率分量:frequency elements图像处理：image processing 传感器：sensor电压：voltage 电流：current第二章anti-imaging filter 抗镜像滤波器sampling interval 采样间隔=sampling period 采样周期sampling frequency 采样频率=sampling rate 采样速率sampling theorem 采样定理Nyquist sampling rate 奈奎斯特采样率Nyquist frequency 奈奎斯特频率Nyquist range 奈奎斯特范围oversampling 过采样undersampling 欠采样quantization step 量化步长quantization noise量化噪声bit rate 比特率anti-aliasing filter 抗混叠滤波器第三章数字函数：digital function 合成函数：composite function 二维数字信号：two-dimensional digital signal语音信号：speech signal 量化方案：quantization scheme 脉冲函数：impulse function 单位脉冲函数：unit impulse function 阶跃函数：step function 幂函数:power function指数函数: exponential function 正弦函数：sine function余弦函数：cosine function 复平面：complex plain欧拉恒等式：Euler’s identity 模拟频率：analog frequency数字频率:digital frequency 采样间隔：sampling interval相移：phase shift 像素：pixel灰度级：gray scale第四章roll-off 滚降gain 增益pass band 通带stop band 阻带bandwidth 带宽linear system 线性系统superposition 叠加原理time-invariant 时不变causal system因果系统difference equation差分方程filter coefficient滤波器系数recursive filter 递归滤波器nonrecursive filter 非递归滤波器finite word length effect有限字长效应impulse response 脉冲响应infinite impulse response （IIR)无限脉冲响应finite impulse response (FIR)有限脉冲响应moving average filter 滑动平均滤波器step response 阶跃响应第六章z transform z变换region of convergence 收敛域inverse z transform 逆z变换transfer function 传输函数partial fraction expansion 部分分式展开cover-up method 覆盖法zero 零点pole 极点marginally stable 临界稳定unstable 不稳定第七章傅立叶变换：Fourier Transform 滤波器形状：filter shape频率响应:frequency response 频率特性：frequency characteristics 离散时间傅立叶变换：Discrete Time Fourier Transform幅度响应：magnitude response 相位响应：phase response传输函数：transfer function 相位差：phase difference采样频率：sampling frequency第八章white noise 白噪声magnitude spectrum 幅度频谱phase spectrum 相位频谱discrete Fourier series（DFS)离散傅里叶级数第九章有限脉冲响应滤波器：finite impulse response filter无限脉冲响应滤波器：infinite impulse response filter相位失真：phase distortion 理想低通滤波器：idle low pass filter 窗函数：window function 稳定性：stability通带波纹：pass band ripple 阻带波纹：stop band ripple通带边缘频率:pass band edge frequency过渡带宽度：transition width 矩形窗：Rectangular Window汉宁窗：Hanning Window 哈明窗:Hamming Window布莱克曼窗:Blackman Window 凯塞窗:Kaiser Window项数:number of terms 衰减:attenuation增益:gain 采样频率:sampling frequency第十章infinite impulse response filter(IIR)无限脉冲响应滤波器bilinear transformation 双线性变换prewarping equation 预扭曲方程Butterworth filter 巴特沃斯滤波器Chebyshev Type I filter 切比雪夫I 型滤波器Chebyshev Type II filter 切比雪夫II 型滤波器elliptic filter 椭圆滤波器Impulse invariance method 脉冲响应不变法。
Filter-Solutions10教程
Filter+Solutions10.0英汉翻译及操作说明Lowpass notch filters :低通陷波滤波器Order: 阶filter circuits:滤波电路frequency response:幅频响应Passband :通频带、传输带宽repeatedly cycle：重复周期maximum signal to noise ratio：最大信噪比gain constants：增益系数，放大常数circuit topologies：电路拓扑结构gain shortfall：增益不足maximum output：最大输出功率last stage：末级preceding stage:前级stage filter：分级过滤器Gain Stage：增益级voltage amplitude：电压振幅Component values: 元件值maximum valued: 最大值minimum valued: 最小值standard value:标准值resistors: 电阻器capacitors:电容器operational amplifiers:运算放大器(OA) circuit board:(实验用)电路板active filters:有源滤波器supply currents:源电流power supplies:电源bypassing capacitors:旁路电容optimal:最佳的;最理想的Gain Bandwidth:带宽增益passive component:无源元件active component: 有源元件overall spread:全局;总范围Component characteristics:组件特性Modification:修改;更改data book:数据手册typical values:标准值;典型值default values:省略补充program execution:程序执行Reset button:复原按钮positive temperature coefficient:正温度系数variable resistors:可变电阻器cermet resistor:金属陶瓷电阻器output resistance:输出电阻distortion:失真single amplifier:单级放大器voltage follower:电压输出跟随器troubleshooting:发现并修理故障control panel,:控制面板１、打开crack的软件后，根据滤波器的设计要求，在filter type中选择滤波器的类型（Gaussian：高斯滤波器、Bessel：贝塞尔滤波器、butterworth：巴特沃斯；Chebyshev1切比雪夫1；Chebyshev2切比雪夫2；Hourglass：对三角滤波器、Elliptic：椭圆滤波器、Custom：自定义滤波器、Raised Cos：升余弦滤波器、Matche：匹配滤波器、Delay：延迟滤波器）；２、在filter class中选择滤波器的种类（低通、高通、带通、带阻）；３、在filter Attributes中设置滤波器的阶数（Order）、通频带频率（Passband frequency）；４、在Implementation中选择有源滤波器（active ）、无源滤波器（passive）和数字滤波器（Digital）；５、在Freq Scale中选择Hertz和Log，如果选择了Rad/Sec，则要注意Rad/Sec ＝6.28＊Hertz；６、在Graph Limits中设置好图像的最大频率和最小频率，最大频率要大于通频带的截止频率；在Passive Design/Ideal Filter Response中观察传输函数(Transfer Function)、时域响应(Time Response)、零极点图(Pole Zero Plots)、频域响应(Frequency Response)的图像；７、在Circuit Parmaters中设置源电阻(Source Res)和负载电阻(Load Res);最后点击Circuits观察滤波器电路图；８、在设计有缘滤波器的时候还要注意在Active Implementation 中选择滤波器的电路布局形式一般有源滤波器选择Pos SAB型的，在Circuit Parmaters中设置增益大小（gain）。
数字信号处理词汇英文翻译
DFT (discrete Fourier transform)离散傅立叶变换
196
N-point DFT of a length L signal对L长信号做N点DFT
197
zero padding补零
198
biasing error偏移误差
199
rounding error舍入误差
200
matrix form矩阵形式
integrator积分器
88
DCgain直流增益
89
overlap-add-block convolution method重叠相加器
90
temporary临时的
91
adder加法器
92
multiplier相乘器
93
delay延迟器
94
tapped delay line抽头延迟器
95
differentiator微分器
78
difference equation差分卷积
79
recursive递归
80
even偶数
81
odd奇数
82
filter coefficient滤波器系数
83
diverge发散
84
antidiagonal反对角线
85
flip-and-slide翻转平移
86
input-off-state输出暂态
87
218
window method窗口法
219
linear phase线性相位
220
guaranteesability保证稳定性
221
lowpass低通
222
highpass高通
数字滤波器外文翻译
中文5590字毕业设计（外文翻译材料）2009年6月学 院： 专 业： 学生姓名： 指导教师： 电气与电子工程学院 电子信息工程0503DIGITAL FILTERSDigital filtering is one of the most powerful tools of DSP. Apart from the obvious advantages of virtually eliminating errors in the filter associated with passive component fluctuations over time and temperature, op amp drift (active filters), etc., digital filters are capable of performance specifications that would, at best, be extremely difficult, if not impossible, to achieve with an analog implementation. In addition, the characteristics of a digital filter can be easily changed under software control. Therefore, they are widely used in adaptive filtering applications in communications such as echo cancellation in modems, noise cancellation, and speech recognition.The actual procedure for designing digital filters has the same fundamental elements as that for analog filters. First, the desired filter responses are characterized, and the filter parameters are then calculated. Characteristics such as amplitude and phase response are derived in the same way. The key difference between analog and digital filters is that instead of calculating resistor, capacitor, and inductor values for an analog filter, coefficient values are calculated for a digital filter. So for the digital filter, numbers replace the physical resistor and capacitor components of the analog filter. These numbers reside in a memory as filter coefficients and are used with the sampled data values from the ADC to perform the filter calculations.The real-time digital filter, because it is a discrete time function, works with digitized data as opposed to a continuous waveform, and a new data point is acquired each sampling period. Because of this discrete nature, data samples are referenced as numbers such as sample 1, sample 2, sample 3, etc. Figure 1 shows a low frequency signal containing higher frequency noise which must be filtered out. This waveform must be digitized with an ADC to produce samples x(n). These data values are fed to the digital filter, which in this case is a lowpass filter. The output data samples, y(n), are used to reconstruct an analog waveform using a low glitch DAC.Digital filters, however, are not the answer to all signal processing filtering requirements. In order to maintain real-time operation, the DSP processor must be able to execute all the steps in the filter routine within one sampling clock period1/f s.A fast general purpose fixed-point DSP such as the ADSP-2189M at 75MIPS can 。
基于单片机的数字滤波器设计外文文献翻译
毕业设计（论文）外文文献翻译外文文献：digital filter designAbstract：With the information age and the advent of the digital world, digital signal processing has become one of today's most important disciplines and door technology. Digital signal processing in communications, voice, images, automatic control, radar, military, aerospace, medical and household appliances, and many other fields widely applied. In the digital signal processing applications, the digital filter is important and has been widely applied.Keyword：SCM; Proteus, C language; Digital filter1、figures Unit on :Analog and digital filtersIn signal processing, the function of a filter is to remove unwanted parts of the signal, such as random noise, or to extract useful parts of the signal, such as the components lying within a certain frequency range.The following block diagram illustrates the basic idea.There are two main kinds of filter, analog and digital. They are quite different in their physical makeup and in how they work. An analog filter uses analog electronic circuits made up from components such as resistors, capacitors and op amps to produce the required filtering effect. Such filter circuits are widely used in such applications as noise reduction, video signal enhancement, graphic equalisers in hi-fi systems, and many other areas. There are well-established standard techniques for designing an analog filter circuit for a given requirement. At all stages, the signal being filtered is an electrical voltage or current which is the direct analogue of the physical quantity (e.g. a sound or video signal or transducer output) involved. A digital filter uses a digital processor to perform numerical calculations on sampledvalues of the signal. The processor may be a general-purpose computer such as a PC, or a specialised DSP (Digital Signal Processor) chip. The analog input signal must first be sampled and digitised using an ADC (analog to digital converter). The resulting binary numbers, representing successive sampled values of the input signal, are transferred to the processor, which carries out numerical calculations on them. These calculations typically involve multiplying the input values by constants and adding the products together. If necessary, the results of these calculations, which now represent sampled values of the filtered signal, are output through a DAC (digital to analog converter) to convert the signal back to analog form.Note that in a digital filter, the signal is represented by a sequence of numbers, rather than a voltage or current.The following diagram shows the basic setup of such a system.Unit refers to the input signals used to filter hardware or software. If the filter input, output signals are separated, they are bound to respond to the impact of the Unit is separated, such as digital filters filter definition. Digital filter function, which was to import sequences X transformation into export operations through a series Y.According to figures filter function 24-hour live response characteristics, digital filters can be divided into two, namely, unlimited long live long live the corresponding IIR filter and the limited response to FIR filters. IIR filters have the advantage of the digital filter design can use simulation results, and simulation filter design of a large number of tables may facilitate simple. It is the shortcomings of the nonlinear phase; Linear phase if required, will use the entire network phase-correction. Image processing and transmission of data collection is required with linear phase filters identity. And FIR linear phase digital filter to achieve, but an arbitrary margin characteristics. Impact from the digital filter response of the units can be divided into two broad categories : the impact of the limited response (FIR) filters, and unlimited number of shocks to (IIR) digital filters.FIR filters can be strictly linear phase, but because the system FIR filter function extremity fixed at the original point, it can only use the higher number of bands to achieve their high selectivity for the same filter design indicators FIR filter called band than a few high-IIR 5-10 times, the cost is higher, Signal delay is also larger. But if the same linear phase, IIR filters must be network-wide calibration phase, the same section also increase the number of filters and network complexity. FIR filters can beused to achieve non-Digui way, not in a limited precision of a shock, and into the homes and quantitative factors of uncertainty arising from the impact of errors than IIR filter small number, and FIR filter can be used FFT algorithms, the computational speed. But unlike IIR filter can filter through the simulation results, there is no ready-made formula FIR filter must use computer-aided design software (such as MATLAB) to calculate. So, a broader application of FIR filters, and IIR filters are not very strict requirements on occasions.Unit from sub-functions can be divided into the following four categories :(1)Low-filter (LPF);(2)high-filter (HPF);(3)belt-filter (BPF);(4)to prevent filter (BSF).The following chart dotted line for the ideals of the filter frequency characteristics :2、MATLAB introducedMATLAB is a matrix laboratory (Matrix Laboratory) is intended. In addition to an excellent value calculation capability, it also provides professional symbols terms, word processing, visualization modeling, simulation and real-time control functions. MATLAB as the world's top mathematical software applications, with a strongengineering computing, algorithms research, engineering drawings, applications development, data analysis and dynamic simulation, and other functions, in aerospace, mechanical manufacturing and construction fields playing an increasingly important role. And the C language function rich, the use of flexibility, high-efficiency goals procedures. High language both advantages as well as low level language features. Therefore, C language is the most widely used programming language. Although MATLAB is a complete, fully functional programming environment, but in some cases, data and procedures with the external environment of the world is very necessary and useful. Filter design using Matlab, could be adjusted with the design requirements and filter characteristics of the parameters, visual simple, greatly reducing the workload for the filter design optimization.In the electricity system protection and secondary computer control, many signal processing and analysis are based on are certain types Yeroskipou and the second harmonics of the system voltage and current signals (especially at D process), are mixed with a variety of complex components, the filter has been installed power system during the critical components. Current computer protection and the introduction of two digital signal processing software main filter. Digital filter design using traditional cumbersome formula, the need to change the parameters after recalculation, especially in high filters, filter design workload. Uses MATLAB signal processing boxes can achieve rapid and effective digital filter design and simulatio MATLAB is the basic unit of data matrix, with its directives Biaodashi mathematics, engineering, commonly used form is very similar, it is used to solve a problem than in MATLAB C, Fortran and other languages End precision much the same thing. The popular MATLAB 5.3/Simulink3.0 including hundreds of internal function with the main pack and 30 types of tool kits (Toolbox). kits can be divided into functional tool kits and disciplines toolkit. MATLAB tool kit used to expand the functional symbols terms, visualization simulation modelling, word processing and real-time control functions. professional disciplines toolkit is a stronger tool kits, tool kits control, signal processing tool kit, tool kits, etc. belonging to such communicationsMATLAB users to open widely welcomed. In addition to the internal function, all the packages MATLAB tool kits are readable document and the document could be amended, modified or users through Yuanchengxu the construction of new procedures to prepare themselves for kits.3、Digital filter designDigital filter design of the basic requirementsDigital filter design must go through three steps :(1) Identification of indicators : In the design of a filter, there must be some indicators. These indicators should be determined on the basis of the application. In many practical applications, digital filters are often used to achieve the frequency operation. Therefore, indicators in the form of general jurisdiction given frequency range and phase response. Margins key indicators given in two ways. The first is absolute indicators. It provides a function to respond to the demands of the general applicationof FIR filter design. The second indicator is the relative indicators. Its value in the form of answers to decibels. In engineering practice, the most popular of such indicators. For phase response indicators forms, usually in the hope that the system with a linear phase frequency bands human. Using linear phase filter design with the following response to the indicators strengths：①it only contains a few algorithms, no plural operations；②there is delay distortion, only a fixed amount of delay; ③the filter length N (number of bands for N-1), the volume calculation for N/2 magnitude.(2) Model approach : Once identified indicators can use a previous study of the basic principles and relationships, a filter model to be closer to the target system.(3) Achieved : the results of the above two filters, usually by differential equations, system function or pulse response to describe. According to this description of hardware or software used to achieve it.4、Introduced FPGAProgrammable logic device is a generic logic can use a variety of chips, which is to achieve ASIC ASIC (Application Specific Integrated Circuit) semi-customized device, Its emergence and development of electronic systems designers use CAD tools to design their own laboratory in the ASIC device. Especially FPGA (Field Programmable Gate Array) generated and development, as a microprocessor, memory, the figures for electronic system design and set a new industry standard (that is based on standard product sales catalogue in the market to buy). Is a digital system for microprocessors, memories, FPGA or three standard building blocks constitute their integration direction.Digital circuit design using FPGA devices, can not only simplify the design process and can reduce the size and cost of the entire system, increasing system reliability. They do not need to spend the traditional sense a lot of time and effort required to create integrated circuits, to avoid the investment risk and become the fastest-growing industries of electronic devices group. Digital circuit design system FPGA devices using the following main advantages(1) Design flexibleUse FPGA devices may not in the standard series device logic functional limitations. And changes in system design and the use of logic in any one stage of the process, and only through the use of re-programming the FPGA device can be completed, the system design provides for great flexibility.(2)Increased functional densityFunctional density in a given space refers to the number of functional integration logic. Programmable logic chip components doors several high, a FPGA can replace several films, film scores or even hundreds of small-scale digital IC chip illustrated in the film. FPGA devices using the chip to use digital systems in small numbers, thus reducing the number of chips used to reduce the number of printed size and printed, and will ultimately lead to a reduction in the overall size of the system.(3)Improve reliabilityPrinting plates and reduce the number of chips, not only can reduce system size, but it greatly enhanced system reliability. A higher degree of integration than systemsin many low-standard integration components for the design of the same system, with much higher reliability. FPGA device used to reduce the number of chips required to achieve the system in the number printed on the cord and joints are reduced, the reliability of the system can be mproved.(4)Shortening the design cycleAs FPGA devices and the programmable flexibility, use it to design a system for longer than traditional methods greatly shortened. FPGA device master degrees high, use printed circuit layout wiring simple. At the same time, success in the prototype design, the development of advanced tools, a high degree of automation, their logic is very simple changes quickly. Therefore, the use of FPGA devices can significantly shorten the design cycle system, and speed up the pace of product into the market, improving product competitiveness.(5)Work fastFPGA/CPLD devices work fast, generally can reach several original Hertz, far larger than the DSP device. At the same time, the use of FPGA devices, the system needed to achieve circuit classes and small, and thus the pace of work of the entire system will be improved.(6)Increased system performance confidentialityMany FPGA devices have encryption functions in the system widely used FPGA devices can effectively prevent illegal copying products were others(7)To reduce costsFPGA device used to achieve digital system design, if only device itself into the price, sometimes you would not know it advantages, but there are many factors affecting the cost of the system, taken together, the cost advantages of using FPGA is obvious. First, the use of FPGA devices designed to facilitate change, shorten design cycles, reduce development costs for system development; Secondly, the size and FPGA devices allow automation needs plug-ins, reducing the manufacturing system to lower costs; Again, the use of FPGA devices can enhance system reliability, reduced maintenance workload, thereby lowering the cost of maintenance services for the system. In short, the use of FPGA devices for system design to save costs.FPGA design principles :FPGA design an important guiding principles : the balance and size and speed of exchange, the principles behind the design of the filter expression of a large number of certification.Here, "area" means a design exertion FPGA/CPLD logic resources of the FPGA can be used to the typical consumption (FF) and the search table (IUT) to measure more general measure can be used to design logic equivalence occupied by the door is measured. "pace" means stability operations in the chip design can achieve the highest frequency, the frequency of the time series design situation, and design to meet the clock cycle -- PADto pad, Clock Setup Time, Clock Hold Beijing, Clock-to-Output Delay, and other characteristics of many time series closely related. Area (area) and speed (speed) runs through the two targets FPGA design always is the ultimate design quality evaluation criteria. On the size and speed of the two basic concepts : balance of size and speed and size and speed of swap.One pair of size and speed is the unity of opposites contradictions body. Requirements for the design of a design while the smallest, highest frequency of operation is unrealistic. More scientific goal should be to meet the design requirements of the design time series (includes requirements for the design frequency) premise, the smallest chip area occupied. Or in the specified area, the design time series cushion greater frequency run higher. This fully embodies the goals of both size and speed balanced thinking. On the size and speed requirements should not be simply interpreted as raising the level and design engineers perfect sexual pursuit, and should recognize that they are products and the quality and cost of direct relevance. If time series cushion larger design, running relatively high frequency, that the design Jianzhuangxing stronger, more quality assurance system as a whole; On the other hand, the smaller size of consumption design is meant to achieve in chip unit more functional modules, the chip needs fewer, the entire system has been significantly reduced cost. As a contradiction of the two components, the size and speed is not the same status. In contrast, meet the timetables and work is more important for some frequency when both conflicts, the use of priority guidelines.Area and the exchange rate is an important FPGA design ideas. Theoretically, if a design time series cushion larger, can run much higher than the frequency design requirements, then we can through the use of functional modules to reduce the consumption of the entire chip design area, which is used for space savings advantages of speed; Conversely, if the design of a time series demanding, less than ordinary methods of design frequency then generally flow through the string and data conversion, parallel reproduction of operational module, designed to take on the whole "string and conversion" and operate in the export module to chip in the data "and string conversion" from the macro point of view the whole chip meets the requirements of processing speed, which is equivalent to the area of reproduction - rate increase.For example. Assuming that the digital signal processing system is 350Mb/s input data flow rate, and in FPGA design, data processing modules for maximum processing speed of150Mb/s, because the data throughput processing module failed to meet requirements, it is impossible to achieve directly in the FPGA. Such circumstances, they should use "area-velocity" thinking, at least three processing modules from the first data sets will be imported and converted, and then use these three modules parallel processing of data distribution, then the results "and string conversion," we have complete data rate requirements. We look at both ends of the processing modules, data rate is 350Mb/s, and in view of the internal FPGA, each sub-module handles the data rate is 150Mb/s, in fact, all the data throughput is dependent on three security modules parallel processing subsidiary completed, that is used by more chip area achieve high-speed processing through "the area of reproduction for processing speed enhancement" and achieved design.FPGA is the English abbreviation Field of Programmable Gate Array for the site programmable gate array, which is in Pal, Gal, Epld, programmable device basis to further develop the product. It is as ASIC (ASIC) in the field of a semi-customized circuit and the emergence of both a customized solution to the shortage circuit, butovercome the original programmable devices doors circuit few limited shortcomings.FPGA logic module array adopted home (Logic Cell Array), a new concept of internal logic modules may include CLB (Configurable Logic Block), export import module IOB (Input Output Block) and internal links (Interconnect) 3. FPGA basic features are :(1)Using FPGA ASIC design ASIC using FPGA circuits, the chip can be used,while users do not need to vote films production.(2)FPGA do other customized or semi-customized ASIC circuits throughout the Chinese specimen films.(3)FPGA internal capability and rich I/O Yinjue.(4)FPGA is the ASIC design cycle, the shortest circuit, the lowest development costs, risks among the smallest device(5)FPGA using high-speed Chmos crafts, low consumption, with CMOS, TTL low-power compatibleIt can be said that the FPGA chip is for small-scale systems to improve system integration, reliability one of the bestCurrently FPGA many varieties, the Revenue software series, TI companies TPC series, the fiex ALTERA company seriesFPGA is stored in films from the internal RAM procedures for the establishment of the state of its work, therefore, need to programmed the internal Ram. Depending on the different configuration, users can use a different programming methods Plus electricity, FPGA, EPROM chips will be read into the film, programming RAM中data, configuration is completed, FPGA into working order. Diaodian, FPGA resume into white films, the internal logic of relations disappear, FPGA to repeated use. FPGA's programming is dedicated FPGA programming tool, using generic EPROM, prom programming device can. When the need to modify functional FPGA, EPROM can only change is. Thus, with a FPGA, different programming data to produce different circuit functions. Therefore, the use of FPGA very flexible.There are a variety of FPGA model : the main model for a parallel FPGA plus a EPROM manner; From the model can support a number of films FPGA; serial prom programming model could be used serial prom FPGA programming FPGA; The external model can be engineered as microprocessors from its programming microprocessors.Verilog HDL is a hardware description language for the algorithm level, doors at the level of abstract level to switch-level digital system design modelling. Modelling of the target figure by the complexity of the system can be something simple doors and integrity of electronic digital systems. Digital system to the levels described, and in the same manner described in Hin-time series modelling.Verilog HDL language with the following description of capacity : design behaviour characteristics, design data flow characteristics, composition and structure designed to control and contain the transmission and waveform design a certification mechanism. All this with the use of a modelling language. In addition, Verilog HDL language programming language interface provided by the interface in simulation, design certification from the external design of the visit, including specific simulationcontrol and operation.Verilog HDL language grammar is not only a definition, but the definition of each grammar structure are clear simulation, simulation exercises. Therefore, the use of such language to use Verilog simulation models prepared by a certification. From the C programming language, the language inherited multiple operating sites and structures. Verilog HDL provides modelling capacity expansion, many of the initial expansion would be difficult to understand. However, the core subsets of Verilog HDL language very easy to learn and use, which is sufficient for most modelling applications. Of course, the integrity of the hardware description language is the most complex chips from the integrity of the electronic systems described.HistoryVerilog HDL language initially in 1983 by Gateway Design Automation companies for product development simulator hardware modelling language. Then it is only a dedicated language. Since their simulation, simulation devices widely used products, Verilog HDL as a user-friendly and practical language for many designers gradually accepted. In an effort to increase the popularity of the language activities, Verilog HDL language in 1990 was a public area. Open Verilog International (OVI) is to promote the development of Verilog international organizations. 1992, decided to promote OVI OVI standards as IEEE Verilog standards. The effort will ultimately succeed, a IEEE1995 Verilog language standard, known as IEEE Std 1364-1995. Integrity standards in Verilog hardware description language reference manual contains a detailed description.Main capacityListed below are the main Verilog hardware description language ability*Basic logic gate, and, for example, or have embedded in the language and nand* Users of the original definition of the term (UDP), the flexibility. Users can be defined in the original language combinations logic original language, the original language of logic could also be time series* Switches class infrastructure models, such as the nmos and pmos also be embedded in the language* Hin-language structure designated for the cost of printing the design and trails Shi Shi and design time series checks.* Available three different ways to design or mixed mode modelling. These methods include : acts described ways - use process of structural modelling; Data flow approach - use of a modelling approach Fuzhi expression; Structured way - using examples of words to describe modular doors and modelling.* Verilog HDL has two types of data : data types and sequence data line network types. Line network types that the physical links between components and sequence types that abstract data storage components.* To describe the level design, the structure can be used to describe any level module example* Design size can be arbitrary; Language is design size (size) impose any restrictions * And the machine can read Verilog language, it may as EDA tools and languages ofthe world between the designers* Verilog HDL language to describe capacity through the use of programming language interface (PLI) mechanism further expansion. PLI is to allow external functions of the visit Verilog module information, allowing designers and simulator world Licheng assembly* Design to be described at a number of levels, from the switch level, doors level, register transfer level (RTL) to the algorithm level, including the level of process and content* To use embedded switching level of the original language in class switch design integrity modelling * Same language can be used to generate simulated incentive and certification by the designated testing conditions, such as the value of imports of the designated*Verilog HDL simulation to monitor the implementation of certification, the certification process of implementing the simulation can be designed to monitor and demonstrate value. These values can be used to compare with the expectations that are not matched in the case of print news reports.* Acts described in the class, not only in the RTL level Verilog HDL design description, and to describe their level architecture design algorithm level behavioural description* Examples can use doors and modular structure of language in a class structure described* Verilog HDL mixed mode modelling capabilities in the design of a different design in each module can level modelling* Verilog HDL has built-in logic function, such as*Structure of high-level programming languages, such as conditions of expression, and the cycle of expression language, language can be used* To it and can display regular modelling * Provide a powerful document literacy* Language in the specific circumstances of non-certainty that in the simulator, different models can produce different results; For example, describing events in the standard sequence of events is not defined.5、In troduction of DSPToday, DSP is w idely used in the modern techno logy and it has been the key part of many p roducts and p layed more and mo re impo rtant ro le in our daily life.Recent ly, Northw estern Po lytechnica lUniversity Aviation Microelect ronic Center has comp leted the design of digital signal signal p rocesso r co re NDSP25, w h ich is aim ing at TM S320C25 digital signal p rocesso r of Texas Inst rument TM S320 series. By using top 2dow n design flow , NDSP25 is compat ible w ith inst ruct ion and interface t im ing of TM S320C25.Digital signal processors (DSP) is a fit for real-time digital signal processing for high-speed dedicated processors, the main variety used for real-time digital signal processing to achieve rapid algorithms. In today's digital age background, the DSP has become the communications, computer, and consumer electronics products, and other fields based device.Digital signal processors and digital signal processing is inseparably, we usually say "DSP" can also mean the digital signal processing (Digital Signal Processing), is that in this digital signal processors Lane. Digital signal processing is a cover many disciplines applied to many areas and disciplines, refers to the use of computers or specialized processing equipment, the signals in digital form for the collection, conversion, recovery, valuation, enhancement, compression, identification, processing, the signals are compliant form. Digital signal processors for digital signal processing devices, it is accompanied by a digital signal processing to produce. DSP development process is broadly divided into three phases : the 20th century to the 1970s theory that the 1980s and 1990s for the development of products. Before the emergence of the digital signal processing in the DSP can only rely on microprocessors (MPU) to complete. However, the advantage of lower high-speed real-time processing can not meet the requirements. Therefore, until the 1970s, a talent made based DSP theory and algorithms. With LSI technology development in 1982 was the first recipient of the world gave birth to the DSP chip. Years later, the second generation based on CMOS工艺DSP chips have emerged. The late 1980s, the advent of the third generation of DSP chips. DSP is the fastest-growing 1990s, there have been four successive five-generation and the generation DSP devices. After 20 years of development, the application of DSP products has been extended to people's learning, work and all aspects of life and gradually become electronics products determinants.REFERENCES1.Chan, D.S.K., Rabiner L.R.: Analysis of Quantization Errors in the Direct Form for Finite Impulse Response Digital Filters. IEEE Trans. Audio and Electroacoustics. 21(4) (1973) 354-3662.Avenhaus, E.: On the Design of Digital Filters with Coefficients of Limited Word Length. IEEE Trans. Acoustics, Speech, Signal Processing. 20 (1972) 206-2123.Kodek, D.M.: Design of Optimal Finite Wordlength FIR Digital Filters using Integer Programming Techniques. IEEE Trans. Acoustics, Speech and Signal Processing. 28(3) (1980) 304-3084.Kodek, D.M., Steiglitz, K.: Comparison of Optimal and Local Search Methods for Designing Finite Wordlength FIR digital filters. IEEE Trans. Circuits and Systems. 28(1) (1981) 28-325.Mitchell, M.: An Introduction to Genetic Algorithms. Bradford Books, MA Cambridge。
滤波器术语英汉翻译
滤波器软件英汉翻译Lowpass notch filters :低通陷波滤波器Order: 阶filter circuits:滤波电路frequency response:幅频响应Passband :通频带、传输带宽repeatedly cycle：重复周期maximum signal to noise ratio：最大信噪比gain constants：增益系数，放大常数circuit topologies：电路拓扑结构gain shortfall：增益不足maximum output：最大输出功率last stage：末级preceding stage:前级stage filter：分级过滤器Gain Stage：增益级voltage amplitude：电压振幅Component values: 元件值maximum valued: 最大值minimum valued: 最小值standard value:标准值resistors: 电阻器capacitors:电容器operational amplifiers:运算放大器(OA) circuit board:(实验用)电路板active filters:有源滤波器supply currents:源电流power supplies:电源bypassing capacitors:旁路电容optimal:最佳的;最理想的Gain Bandwidth:带宽增益passive component:无源元件active component: 有源元件overall spread:全局;总范围Component characteristics:组件特性Modification:修改;更改data book:数据手册typical values:标准值;典型值default values:省略补充program execution:程序执行Reset button:复原按钮positive temperature coefficient:正温度系数variable resistors:可变电阻器cermet resistor:金属陶瓷电阻器output resistance:输出电阻distortion:失真single amplifier:单级放大器voltage follower:电压输出跟随器troubleshooting:发现并修理故障control panel,:控制面板。
外文翻译---FIR滤波器设计技术
外文原文及翻译FIR滤波器设计技术摘要这份报告列举了一些设计FIR滤波器所使用的技术。
首先讨论了窗函数法和频率取样法的优点和缺点。
FIR数字滤波器也包含了许多优化设计的方法，这些优化技术减少了在频率采样时非采样频率点的误差频率。
对于用于设计数字滤波器的技术，例如matlab，进行了简明扼要的探讨。
介绍FIR滤波器的系统函数是一个1z 的多项式，因FIR滤波器的频率响应是频率的实函数，也称其为零相位滤波器。
N阶FIR滤波器的系统函数表示为（1）FIR滤波器是十分重要的，可应用于精确线性相位相应。
FIR滤波器的实现方式保证了它是一个稳定的滤波器。
FIR滤波器的设计可分为两部分：（i）近似问题（ii）实现问题解决近似问题，要通过四个步骤找出传递函数：（i）在频域内找出期望的或最理想的反应（ii）选择滤波器的阶数（FIR滤波器的长度N）（iii）选择近似结果中较好的（iv）选择一种算法寻找最优的滤波器传递函数选择部分结构处理实现传递函数的形式可能是线路图或程序。
本质上来说，有三种著名的FIR滤波器设计方法：（1）窗函数法（2）频率取样法（3）滤波器的优化设计窗函数法在该方法中，[Park87],[Rab75], [Proakis00]从理想的频率响应Hd（w）出发，一般来说，单位脉冲相应hd（n）的持续时间是无限的，所以在某种程度上说，它必须截断。
n=M-1约束着FIR滤波器的长度M。
以M-1截断的hd（n）乘以窗函数就得到了滤波器的单位脉冲响应。
矩形窗口的定义为w(n) = 1 0≦n≦M-1 (2)= 0 其它FIR滤波器的单位脉冲相应为h(n) = hd(n) w(n) (3)= hd(n) 0≦n≦M-1= 0 其它现在,多元化的窗函数w(n)与hd(n)相当于hd(w)与w（w）的卷积，其中，w （w）是窗函数的频域表示。
因此Hd(w)与w(w)的卷积为FIR数字滤波器的截断后的频率响应(4)频率响应也可以利用以下的关系式(5)由于非均匀收敛的傅里叶级数的不连续性，其自身的波纹前后有一种近似于不连续的频率响应，因此直接截断的hd(n)来获得h(n)将导致吉布斯现象。
最常用数字滤波方法及源代码
最常用数字滤波方法及源代码在数字信号处理中，常用的数字滤波方法有以下几种：1) 移动平均滤波（Moving Average Filter）：将输入信号的过去N 个样本的平均值作为输出样本的值。
这种滤波器可以有效地平滑信号，但对于快速变化的信号可能引入较大的延迟。
2) 中值滤波（Median Filter）：将输入信号的过去N个样本的中间值作为输出样本的值。
中值滤波器可以有效地去除噪声，但对于快速变化的信号可能引入较大的失真。
3) 低通滤波（Lowpass Filter）：通过去除高频成分来平滑信号。
常用的低通滤波器有巴特沃斯滤波器、切比雪夫滤波器等。
以下是Python中实现这些滤波方法的简单源代码示例：移动平均滤波方法：```pythondef moving_average_filter(input_signal, window_size):filtered_signal = []for i in range(len(input_signal) - window_size + 1):window = input_signal[i:i+window_size]filtered_signal.append(sum(window) / window_size)return filtered_signal```中值滤波方法：```pythondef median_filter(input_signal, window_size):filtered_signal = []for i in range(len(input_signal) - window_size + 1):window = input_signal[i:i+window_size]filtered_signal.append(sorted(window)[window_size//2])return filtered_signal```低通滤波方法：```pythonimport scipy.signal as signaldef lowpass_filter(input_signal, cutoff_freq, fs):nyquist_freq = 0.5 * fsnormalized_cutoff_freq = cutoff_freq / nyquist_freqb, a = signal.butter(4, normalized_cutoff_freq, btype='low') filtered_signal = signal.lfilter(b, a, input_signal)return filtered_signal```注意：以上代码示例仅为简单实现，并未考虑边界情况和参数校验等细节。
滤波器术语英汉翻译
滤波器软件英汉翻译Lowpass notch filters :低通陷波滤波器Order: 阶filter circuits:滤波电路frequency response:幅频响应Passband :通频带、传输带宽repeatedly cycle：重复周期maximum signal to noise ratio：最大信噪比gain constants：增益系数，放大常数circuit topologies：电路拓扑结构gain shortfall：增益不足maximum output：最大输出功率last stage：末级preceding stage:前级stage filter：分级过滤器Gain Stage：增益级voltage amplitude：电压振幅Component values: 元件值maximum valued: 最大值minimum valued: 最小值standard value:标准值resistors: 电阻器capacitors:电容器operational amplifiers:运算放大器(OA) circuit board:(实验用)电路板active filters:有源滤波器supply currents:源电流power supplies:电源bypassing capacitors:旁路电容optimal:最佳的;最理想的Gain Bandwidth:带宽增益passive component:无源元件active component: 有源元件overall spread:全局;总范围Component characteristics:组件特性Modification:修改;更改data book:数据手册typical values:标准值;典型值default values:省略补充program execution:程序执行Reset button:复原按钮positive temperature coefficient:正温度系数variable resistors:可变电阻器cermet resistor:金属陶瓷电阻器output resistance:输出电阻distortion:失真single amplifier:单级放大器voltage follower:电压输出跟随器control panel,:控制面板troubleshooting:发现并修理故障。
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
FIR 数字滤波器的有限字长系数优化的比较研究
拜彻尔，泰勒，罗兰
威尔士大学纽波特学院运算工程学校
摘要：实时数字滤波器频率响应的精度受实现时系数约束条件即有限字长(FWL)的影响。
该文仅考虑FIR 数字滤波器有关的FWL 问题。
准确和近似响应之间的最大误差限的约束条件所对应的理论问题和统计误差值都进行了详细的研究。
利用实数值遗传算法作为优化工具，并由若干设计案例的FWL 效应获得其最大误差限和误差值。
由此，完成了简单凑整逼近、遗传算法优化、整数规划法，以及简单希尔登山者方法之间的比较。
关键词：实时数字滤波器； 有限字长；遗传算法；整数规划
1. 前言
FIR 数字滤波器广泛用于图像处理、移动通信、医疗电子，以及很多其他的信号处理应用。
为降低能耗和提高运算量，截断系数到最短长度是有优势的。
然而，该截断会引起滤波嚣设计参数的变化，在某些情况下这是不可接收的。
此即优化问题，即尽可能地选择近似系数值的微小变化量，以便最好的服从设计规范标准。
针对有限脉冲响应(FIR)滤波器形式结构的线性相位已被证明是鲁棒的，因而FWL 系数的自我实现的研究是极具有吸引力的[1]。
FWL FIR 对称数字滤波器的研究涉及到一组系数的选择，从而这个新频率响应可以作为无限准确系数截断的一个结果，可以最大的接近所给定的规范频率响应。
已知的为解决该问题所使用的算法均基于两种方法：局部搜索法[2]和整数规划分支界限法[3,4]。
局部搜索法需要选择一组可行的FWL 系数(称为四舍五入值)，用以给出一个频率响应并用以检验H 的领域。
同时要选定滤波器的传递函数，以便得到更好的滤波器H'，即具有低误差函数的滤波器。
如果找到了这样的一个滤波器H'，那么便可用H'来代替H ，而算法即可进入下一步或者终止。
分支界限算法涉及对一组可能解所构成的树的系统性修正，这些解依赖于由枚举总数所确定的下界值。
这两种算法本质上计算密集，且不能保证全局优化。
其问题即是在于进一步复合，使其更加灵敏以便增加滤波器长度。
2. FWL 系数及误差目标函数
用以导出FWL 系数的最常用定点算法是直接量化法。
使用标准滤波器设计技术导出的高精度系数在该方法中首次被利用，以得出FWL 的量化系数。
如下量化系数的起始解给出。
h ri =round[h ei 2B-1] i=0,1,2,...,N-1 (1)
这里，h ri 为四舍五入系数，hei 为高精度系数，B 为用以描述系数的位数，N 为滤波器长度。
优化过程的主要目的在于极小化目标函数，其明确目标为获得一个与期望的响应尽可能接近的滤波器频率响应。
目标函数被用于500个等距频率的格点。
目标函数通过以下式来评价：
}H max ,H 110max{max }H H 1{ObjV s p s s p p i i L
s
i 2
i P
i 2
i -++-=∑∑== (2)
H ip =遗传算法优化滤波器在通带中对应频率的幅值响应
H is =遗传算法优化滤波器在阻带中对应频率的幅值响应 L=频率格点的数目（500）
P=通带的截止频率数 S=阻带的截止频率数
(2)式所表述的平方偏差和加权最大偏差和的综合即可获得优良的整体频率响应。
当优化目标函数仅使用最大化偏差时，这些响应不受初期试验中观察到的相位差的影响，。
3. FIR 滤波器的频带选择的遗传算法的优化
在这一部分我们认为波带选择的问题是为了使理想响应被指定在被选到的通带或阻带以上。
理想函数D(ω)包含大量的脱节带频，而K=1,……，对于于每一个K ，D(ω)是用于结晶所有的ωk Ω∈。
如果有着无限精度小数的滤波器是H(ω)同时使用FWL 系数近似滤波器是H'(ω)，那最大误差界是由
为了进行比较研究，托代克和史代比所使用的10个滤波器例子用于系数优化，基于整数规划的方法也用于此处。
这10个滤波器被分成四组，如表1所示：
滤波器规范组
表2表明对于所有 理想响应的最大化误差的结果，表2所使用的界值是通过使用等式3而得来的。
整数规划方法的比较清楚地表明了关于遗传算法优化滤波器的一个明显提高，它也表明等式3的界值是与使用遗传算法优化滤波器而得到的最大化误差相一致。
遗传算法优化滤波器已生成了略低的最大化误差值，同20%滤波器的界值比较，即A25/5和C15/5滤波器。
另一方面，相比较于20%的滤波器的界值整数规划滤波器有更好的表现。
B25/7滤波器的一个响应例子由图1表示。
它表明如期望所示尽管圆润的响应伴随着准确的响应，遗传算法优化响应伴随着理想响应的要求即是滤波器B25/7通带里的1,。
图1展示了一个有关滤波器B25的最大化误差大小与字节数的比较。
表1.(a)简单圆的响应大小，对于滤波器B25/7遗传算法优化和整数规化优化系数，(b)对于B25滤波器误差大小和字节数的比较。
4.简单的登山科技和详细搜索
为了检验遗传算法优化结果的强健性和准确度，简单攀山算法的计算方法，例如最陡爬坡和最近爬坡被用于选择如表1所示的滤波器，为了遗传算法优化所用的搜索空间进行了随机样本测试。
另外，对于以少部分低阶滤波器，进行了一个超越相匹配的搜索空间的详细的搜索。
这个搜索所用攀山算法是基于用于二进制字符串的并且根据FIR 滤波器的整值的号码进行了改编。
开头的一个整值的号码系数集是由随机扰动的四舍五入系数通过加1或减1， 如图2
简单的攀山算法的流程图
SAHC：最陡爬坡
NAHC：最近爬坡
表示四舍五入系数值的搜索空间加1或减1
最陡爬坡和最近爬坡，也为了选择滤波器而进行的随机样本和详细搜索的结果如表3所示。
结果表明有星号的代表那些比加1或减1偏离更厉害的四舍五入的系数值。
数据同时也表明了详细搜索仅限于对四舍五入系数进行加1或减1。
证据表明遗传算法优化可以连续产生好的结果（见表2）。
尽管最陡爬坡的攀山技术对于选定数量的滤波器也表现出非凡的好结果。
5.结论
在这篇文章中，我们探索了FIR数字滤波器有限字长的遗传算法优化的问题。
大量的频段选择滤波器的遗传算法优化是考虑在内的。
对于这样的滤波器，
基于整数规划方法的优化结果和简单攀山技术的结果进行了比较。
对大部分所选的滤波器，遗传算法优化在此表现出了连续的改善。
简单攀山技术（特别是最陡爬坡）所用的优化方法通过产生好的结果已经变现出很好的潜力，通常这在所考虑范围内的滤波器是不符合要求的，然而遗传算法技术已经显示了一个强健的，实用的，和高效率的优化工具。
另外，它就像是遗传算法代码以600兆赫兹的速度奔腾与电脑上伴随第二部分所给的参数，超过了完整的优化方法，每个滤波器接近以30秒的速度在优化。
参考文献
1. Chan, D.S.K., Rabiner L.R.: Analysis of Quantization Errors in the Direct
Form for Finite Impulse Response Digital Filters. IEEE Trans. Audio and Electroacoustics. 21(4) (1973) 354-366
2. Avenhaus, E.: On the Design of Digital Filters with Coefficients of Limited
Word Length. IEEE Trans. Acoustics, Speech, Signal Processing. 20 (1972) 206-212
3. Kodek, D.M.: Design of Optimal Finite Wordlength FIR Digital Filters
using Integer Programming Techniques. IEEE Trans. Acoustics, Speech and Signal Processing. 28(3) (1980) 304-308
4. Kodek, D.M., Steiglitz, K.: Comparison of Optimal and Local Search
Methods for Designing Finite Wordlength FIR digital filters. IEEE Trans. Circuits and Systems. 28(1) (1981) 28-32
5. Mitchell, M.: An Introduction to Genetic Algorithms. Bradford Books, MA Cambridge。