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JTAG Configuration

JTAG has developed a specification for boundary-scan testing. This boundary-scan test (BST) architecture offers the capability to efficiently test components on PCBs with tight lead spacing. The BST architecture can test pin connections without using physical test probes and capture functional data while a device is operating normally. You can also use the JTAG circuitry to shift configuration data into the device. The QuartusII software automatically generates.sofs that are used for JTAG configuration with a download cable in the Quartus II software programmer.

For more information about JTAG boundary-scan testing, refer to the IEEE 1149.1(JTAG) Boundary-Scan Testing for Cyclone III Devices chapter.

JTAG instructions have precedence over any other device configuration modes. Therefore, JTAG configuration can take place without waiting for other configuration modes to complete. For example, if you attempt JTAG configuration of Cyclone III device family during PS configuration, PS configuration terminates and JTAG configuration begins. If the Cyclone III device family MSEL pins are set to AS mode, the Cyclone III device family does not output a DCLK signal when JTAG configuration takes place. The four required pins for a device operating in JTAG mode are TDI, TDO, TMS, and TCK. The TCK pin has an internal weak pull-down resistor while the TDI and TMS pins have weak internal pull-up resistors (typically 25 kΩ). The TDO output pin is powered by VCCIO in I/O bank 1. All the JTAG input pins are powered by the VCCIO pin. All the JTAG pins support only LVTTL I/O standard. All user I/O pins are tri-stated during JTAG configuration. Table 9–15 lists the function of each JTAG pin. 1 The TDO output is powered by the VCCIO power supply of I/O bank 1.

For more information about how to connect a JTAG chain with multiple voltages across the devices in the chain, refer to the IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone III Devices chapter.

Table 9–15. Dedicated JTAG Pins

You can download data to the device on the PCB through the USB-Blaster, MasterBlaster, ByteBlaster II, ByteBlasterMV download cable, and Ethernet-Blaster communications cable during JTAG configuration. Configuring devices using a cable is similar to programming devices in-system. Figure 9–24 and Figure 9–25 show the JTAG configuration of a single Cyclone III device family.

For device VCCIO of 2.5, 3.0, and 3.3 V, refer to Figure 9–24. All I/O inputs must maintain a maximum AC voltage of 4.1 V. Because JTAG pins do not have the internal PCI clamping diodes to prevent voltage overshoot when using VCCIO of 2.5, 3.0, and 3.3V, you must power up the VCC of the download cable with a 2.5-V supply from VCCA.

For device VCCIO of 1.2, 1.5, and 1.8 V, refer to Figure 9–25. You can power up the VCC of the download cabled with the supply from VCCIO.