西安交通大学 专用集成电路ASIC 课件 chap07_phyDesign

Detail Routing
微电子学系
Chap07 P.13
Placement－Prediction
What is prediction ?



Allows quick space exploration, localizes the search For example:

every system has some critical cost functions: Area, wirelength, congestion, timing etc. Prediction aims at estimating values of these cost functions without having to go through the time-consuming process of full construction.
Back End
Detail Routing
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Chap07 P.6
物理设计流程

Floorplan

估算ASIC的面积，确定block的划分、I/O的位置、宏单元的 位置方向，IP块的放置，确定放置单元平面的大小、形状， 预留布线通道，电源、地线位置等。 将所有的宏单元和单元放置到适当的位置；手动加自动。 根据约束条件产生所需的时钟buffer，并将这些buffer放置到 合适的位置。 连接所有的连线，包括电源、地，时钟线，全局连线和局部 连线。
微电子学系
Chap07 P.15
Placement Problem
Input:
•A set of cells and their complete information (a cell library). •Connectivity information between cells (netlist information).
•Cell: a circuit component to be placed on the chip area. In placement, the functionality of the component is ignored. •Net: specifying a subset of terminals, to connect several cells. •Netlist: a set of nets which contains the connectivity information of the circuit.
statistical wire-load models Wirelength in placement
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Chap07 P.14
Constraint of Placement




Area Would like to pack all the modules very tightly Wire length (half-perimeter of the net bbox) Minimize the average wire length Would result in tight packing of the modules with high connectivity Overlap Could be prohibited by the moves, or used as penalty Keep the cells from overlapping (moves cells apart) Timing Not a 1-1 correspondent with wire length minimization, but consistent on the average Congestion Measure of routability Would like to move the cells apart
第7章 后端物理设计
西安交通大学电信学院 微电子研究所 程 军 2012/10/12
微电子学系
Chap07 P.2
CMOS工艺中的互连线
Tiny devices buried under a multilevel structure of wires and vias.
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Chap07 P.3

Chip Area Total Wire length Critical path delay Routability Others, noise, heat dissipation etc.
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Chap07 P.12
Placement
IO Pad Placement
Definitions:

Placement


Clock Tree Generation


Routing

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Chap07 P.7
物理设计流程(2)
Floorplan
Placement
Routing
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Chap07 P.8
Floorplan
A
G H I
Design Hierarchy TOP B
J K
C
(a)
(b)
总体布局结果
详细布局结果
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Chap07 P.21
标准单元详细布局结果
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Chap07 P.22
Routing
Mixed Cell and Block
Cell-based Block-based
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Chap07 P.23
Routing Algorithms

Global routing
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Chap07 P.5
Front End Flow
Behavioral Level Design Logic Design and Simulation Logic Synthesis
Back End Flow
Front End
IO Pad Placement Power/Ground Stripes, Rings Routing

P&R iteration：at least 1 time； Memory usage：large Computing time：long Die size：relative small； Partition into 5 soft blocks，each contains 2000 cells； P&R iteration: at least 6 times； Memory & computing time: relative small & short; Die size: relative large Design reuse potential
Chap07 P.4
At-Risk Nets (millions)
Estimated Number of Nets At-Risk
16
0.5
连线延迟和门延迟的变化趋势
在0.25m，Al连线延时超过门延时，在0.13m，Cu连线延 时超过了门延时。在设计方法学上，由关注晶体管转变成 关注互连线。”Interconnect is everything: Timing, power, noise, design functionality and reliability”
Power/Ground Stripes, Rings Routing
Global Placement Detail Placement
Clock Tree Synthesis and Routing Extraction and Delay Calc. Timing Verification
Global Routing
Chap07 P.9
{C,F}
Floorplan(2)—Contents

Soft macros, Hard macros, IP and floorplan groups Block placement Interactive adjustment and edit

Move，mirror，rotate，align Change size，aspect ratio Reserve routing layers Add/delete/modify/move/align pins/bus pins

Pin assignment Early analysis: timing, congrestion, …
微电子学系
Chap07 P.10
Floorplan(3)－Flatten or Hierarchical

假设一个设计包含10000个单元，以下是两种方法的 区别； Flatten design
L
D
M N
E
O P Q
F
Floorplanning 第一种方法
{L,M,N} {O,P,Q} {F} {I, J, K} {G,H} {Q} {C}
第二种方法
{L,M,N} {P} {C}
第三种方法
{O,P,Q}
{G,H}
{O}
{F}
{I, J, K}
{G,H}
{I, J, K}
{L,M,N}
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Output:
A set of locations on the chip: one location for each cell.
Goal:
The cells are placed to produce a routable chip that meets timing (lowpower, …)
A good placement
微电子学系
Chap07 P.17
Global and Detailed Placement
In global placement, we decide the approximate locations for cells by placing cells in global bins. In detailed placement, we make some local adjustment to get the final non-overlapping placement.
深亚微米互连线复杂性
18
Risk Factors: Interconnect Delay Signal Integrity Electromigration Process Variations
14 12 10 8 6 4 2 0.13 0.18 0.25 0.35
0
Technology ()
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Hierarchical design

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Chap07 P.11
Summary of Floorplan

floorplanning problem is to plan the positions and shapes of the modules at the beginning of the design cycle to optimize the circuit performance:
Logic Partitioning Die Planning
Global Placement
Detail Placement Simulation Floorplanning Clock Tree Synthesis and Routing Design Verification Timing Verification Global Routing Test Generation LVS DRC ERC Extraction and Delay Calc. Timing Verification
Challenge:
•The number of cells in a design is very large (> 1 million). •The timing constraints are very tight.
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Chap07 P.16
Placement Problem
A bad placement
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Global Placement Detailed Placement
Chap07 P.18
Bi-Partitioning/Quadrisection
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Chap07ห้องสมุดไป่ตู้P.19
Placement(quadratic + partitioning)
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Chap07 P.20
标准单元详细布局