毕设外文翻译--单片机基础

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单片机方面毕业设计外文文献翻译

单片机方面毕业设计外文文献翻译

中文译文单片机单片机也被称为微控制器(Microcontroller Unit),常用英文字母的缩写MCU表示单片机,它最早是被用在工业控制领域。

单片机由芯片内仅有CPU的专用处理器发展而来。

最早的设计理念是通过将大量外围设备和CPU集成在一个芯片中,使计算机系统更小,更容易集成进复杂的而对体积要求严格的控制设备当中。

INTEL的Z80是最早按照这种思想设计出的处理器,从此以后,单片机和专用处理器的发展便分道扬镳。

早期的单片机都是8位或4位的。

其中最成功的是INTEL的8031,因为简单可靠而性能不错获得了很大的好评。

此后在8031上发展出了MCS51系列单片机系统。

基于这一系统的单片机系统直到现在还在广泛使用。

随着工业控制领域要求的提高,开始出现了16位单片机,但因为性价比不理想并未得到很广泛的应用。

90年代后随着消费电子产品大发展,单片机技术得到了巨大提高。

随着INTEL i960系列特别是后来的ARM系列的广泛应用,32位单片机迅速取代16位单片机的高端地位,并且进入主流市场。

而传统的8位单片机的性能也得到了飞速提高,处理能力比起80年代提高了数百倍。

目前,高端的32位单片机主频已经超过300MHz,性能直追90年代中期的专用处理器,而普通的型号出厂价格跌落至1美元,最高端[1]的型号也只有10美元。

当代单片机系统已经不再只在裸机环境下开发和使用,大量专用的嵌入式操作系统被广泛应用在全系列的单片机上。

而在作为掌上电脑和手机核心处理的高端单片机甚至可以直接使用专用的Windows和Linux操作系统。

单片机比专用处理器更适合应用于嵌入式系统,因此它得到了最多的应用。

事实上单片机是世界上数量最多的计算机。

现代人类生活中所用的几乎每件电子和机械产品中都会集成有单片机。

手机、电话、计算器、家用电器、电子玩具、掌上电脑以及鼠标等电脑配件中都配有1-2部单片机。

而个人电脑中也会有为数不少的单片机在工作。

单片机毕业设计--英文翻译

单片机毕业设计--英文翻译

附录一:中文翻译单片机的组成单片机要自动完成计算,它应该具有哪些最重要的部分呢?我们以打算盘为例计算一道算术题。

例:36+163×156-166÷34。

现在要进行运算,首先需要一把算盘,其次是纸和笔。

我们把要计算的问题记录下来,然后第一步先算163×156,把它与36相加的结果记在纸上,然后计算166÷34,再把它从上一次结果中减去,就得到最后的结果。

现在,我们用单片机来完成上述过程,显然,它首先要有代替算盘进行运算的部件,这就是“运算器”;其次,要有能起到纸和笔作用的器件,即能记忆原始题目、原始数据和中间结果,还要记住使单片机能自动进行运算而编制的各种命令。

这类器件就称为“存贮器”。

此外,还需要有能代替人作用的控制器,它能根据事先给定的命令发出各种控制信号,使整个计算过程能一步步地进行。

但是光有这三部分还不够,原始的数据与命令要输入,计算的结果要输出,都需要按先后顺序进行,有时还需等待。

如上例中,当在计算163×156时,数字36就不能同时进入运算器。

因此就需要在单片机上设置按控制器的命令进行动作的“门”,当运算器需要时,就让新数据进入。

或者,当运算器得到最后结果时,再将此结果输出,而中间结果不能随便“溜出”单片机。

这种对输入、输出数据进行一定管理的“门”电路在单片机中称为“口”(Port)。

在单片机中,基本上有三类信息在流动,一类是数据,即各种原始数据(如上例中的36、163等)、中间结果(如166÷34所得的商4、余数30等)、程序(命令的集合)等。

这样要由外部设备通过“口”进入单片机,再存放在存贮器中,在运算处理过程中,数据从存贮器读入运算器进行运算,运算的中间结果要存入存贮器中,或最后由运算器经“出入口”输出。

用户要单片机执行的各种命令(程序)也以数据的形式由存贮器送入控制器,由控制器解读(译码)后变为各种控制信号,以便执行如加、减、乘、除等功能的各种命令。

毕业设计(论文)外文原文及译文

毕业设计(论文)外文原文及译文

毕业设计(论文)外文原文及译文一、外文原文MCUA microcontroller (or MCU) is a computer-on-a-chip. It is a type of microcontroller emphasizing self-sufficiency and cost-effectiveness, in contrast to a general-purpose microprocessor (the kind used in a PC).With the development of technology and control systems in a wide range of applications, as well as equipment to small and intelligent development, as one of the single-chip high-tech for its small size, powerful, low cost, and other advantages of the use of flexible, show a strong vitality. It is generally better compared to the integrated circuit of anti-interference ability, the environmental temperature and humidity have better adaptability, can be stable under the conditions in the industrial. And single-chip widely used in a variety of instruments and meters, so that intelligent instrumentation and improves their measurement speed and measurement accuracy, to strengthen control functions. In short,with the advent of the information age, traditional single- chip inherent structural weaknesses, so that it show a lot of drawbacks. The speed, scale, performance indicators, such as users increasingly difficult to meet the needs of the development of single-chip chipset, upgrades are faced with new challenges.The Description of AT89S52The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel's high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following standard features: 8K bytes ofFlash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.Features• Compatible with MCS-51® Products• 8K Bytes of In-System Programmable (ISP) Flash Memory– Endurance: 1000 Write/Erase Cycles• 4.0V to 5.5V Operating Range• Fully Static Operation: 0 Hz to 33 MHz• Three-level Program Memory Lock• 256 x 8-bit Internal RAM• 32 Programmable I/O Lines• Three 16-bit Timer/Counters• Eight Interrupt Sources• Full Duplex UART Serial Channel• Low-power Idle and Power-down Modes• Interrupt Recovery from Power-down Mode• Watchdog Timer• Dual Data Pointer• Power-off FlagPin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89S52, as shown in the following table.Port 3 also receives some control signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.ALE/PROGAddress Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSENis activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Special Function RegistersNote that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers:Control and status bits are contained in registers T2CON and T2MOD for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.Interrupt Registers:The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers areprovided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.Power Off Flag:The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.Memory OrganizationMCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access of the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).MOV 0A0H, #dataInstructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #dataNote that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52.Timer 2Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON.Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.In the Counter function, the register is incremented in response to a1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.InterruptsThe AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10.Each of these interrupt sources can be individually enabled or disabledby setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.Note that Table 5 shows that bit position IE.6 is unimplemented. In the AT89S52, bit position IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software.The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.二、译文单片机单片机即微型计算机,是把中央处理器、存储器、定时/计数器、输入输出接口都集成在一块集成电路芯片上的微型计算机。

单片机书英译汉

单片机书英译汉

本科生毕业设计(翻译)Chapter2 Overview About MicrocontrollersA microcontroller is a single-chip device that contains memory for program information and data. It can perform the operation logic of programming a control process, reading inputs, manipulating and sending output; namely, it has build-in interfaces for input/output (I/O) as well as a central processing unit (CPU). Thus the microcontroller id often know as microcontroller unit (MCU) and the built-in interface capability is designed for connection with sensors, actuators and communications with other devices, and so on. In practice, a microcontroller chip has other chips in addition to itself. They are called support chips will be embedded into the microcontroller chip in the future, namely, become part of the microcontroller chip.Microcontrollers are one kind of microprocessors involved in the special direction-they are highly integrated and they remit the increased computing power. They are developed CPU chips with built-in memory and interface circuits. This results in the situation that more microcontrollers are sold than powerful microcomputers, because they are used in many machines, instruments, and consumer products.In this chapter an overview of microcontroller from many viewpoints, including internal organization, normal types, basic design structure, material-structure styles, operation process, working cycles, working conditions, memory types and software, is shortly described. Finally, as an example, a typical microcontroller single-chip of type 80C51 is sketched.2.1 Normal Configurations Of MicrocontrollersA single chip of microcontroller basically consists of the following internal function blocks.1. CPU playing a role as a brain and heart, under the control of whichsome necessary blocks are working.2. Energy management system receiving the externally provided energy from power supply and allocating them to the internal function blocks for their usages.3. Clock and timing system providing a clock signal with constant frequency, under the help of external oscillation system, for the operation process to hold the entire process in a synchronous state.4. Reset control system leading the operation logic back to the initial state or holding the operation logic at the initial state.5. Control logic memory storing the internal data programs or instructions which indicate the CPU how to guide the operation process.6. Variable area storing the internal data produced during the operation process.The most basic principle of internal configurations and connections are shown as Figure 2.1.The group of microcontrollers, normally called “single chips”,has various kinds. They have differences in volumes, forms, leg numbers, functions, characteristics, etc., and can be principally divided into three large classes called “embedded microcontrollers”, having their common essentiality, as well as their own special points in characters, structures, functions and application ranges. Some of them can replace each other by only adding a little development, but some of them have their own special advantages and disadvantages which can’t be found in othersEach class of microcontrollers mentioned above will be described shortly later.2.1.1 Embedded MicrocontrollerEmbedded microcontrollers cover a very wide range. Their common character is that a single chip contains almost all necessary functions such asdata storage, input and output interfaces designed for its independent work, thus, to drive an embedded microcontroller to start to work, a user only needs to supply an electrical power and a clock system to it.An embedded microcontroller can be a single chip based on a microprocessor criterion already set up, also can be a system set up by using a microcontroller criterion. So it can implement a lot of functions, for example, a single task in a single chip.An elementary role played by the embedded microcontrollers is supplying inexpensive programmable logical controllers and interfaces. Thus, they needn’t to have high degree completed functio ns, but they can implement very complex control combinations according to different requests.Generally the embedded microcontrollers have the following common characteristics:1. Holding a CPU (as mentioned above).2. Possess the reset (as mentioned above) capability.3. Possess the ability of internal clock timing (timing the operation logic by using internal clock).4. Having control memories and program input terminals.5. Having variable areas.6. Having I/O (input/output) pins.7. Having instruction cycle timer.The expended set based on the primary chip mentioned above can satisfy the basic requirements of a computer system, and all added functions listed below are realized through their I/O pins:Internally installed monitor/debug programs.1. The ability to program the internal control memories-this is implemented by using a directing control of a mainframe.2. The abilities of interrupt stimulated by different interrupt sources.3. I/O interface for analog and digital signals.4. Serial I/O (synchronous and asynchronous) interfaces.5. Parallel I/O interfaces.6. Interfaces for external memories.The characteristics listed above make the microcontrollers more flexible, easier to be used and able to realize many developing tasks which seems unable to realize.2.1.2 External Storage MicrocontrollerThe basic structure of external storage microcontrollers can be shown as Figure 2.2.A typical application of external storage microcontrollers is being used as a service device to fetch and temporarily store the data for the main memory. They rationally distribute and temporarily store a lot of data, and can work at a quite high speed than the embedded microcontrollers.Most external storage microcontrollers possess 16-bit or 32-bit channels. They have external memories for storing the operation programs. Their operations fully depend upon their external memories which include control memories and all variable memories required for the microcontrollers.The typical type of external storage microcontrollers is type 80188, made by Intel. The basic body of type 80188 is the type 8088 used in IBM PC and their compatible types. Based on 8088, some circuits are added to the chip to supply some typical functions implemented in application of microcontrollers.The purpose of developing the 80188 is to provide a set of integrated soft-shells for the users. The 80188 includes all required circuit functions provided for application technology development engineer.2.1.3 Digital Signal Processor (DSP)This is a kind of relatively new processors playing a role in sampling data from analog signals, and calculating out the corresponding values.DSP S and their arithmetic and logic units (ALU) operate at very high speed, so that real-time control can be realized, and they involve a variety of mathematic algorithm systems so that they are very welcome in high-level science and technology fields.DSP S are often used to eliminate noises for the equipments, such as the microphone in airplanes, or the signal processors in TV Centers, owing to their high speed and mathematic functions.The DSP algorithm development is a special science field, especially is an important branch of control theory requiring quite high-level mathematics, for example, the Fuzzy Logics, a non-classical mathematics, supporting computer system control.DSP S include multiplex kinds. All of them have the common features which can be found in embedded microcontrollers and external storage microcontrollers. DSP S share typically not used alone, but combined in a system organized by a center control devices such as microcontroller, or with the help of a interface connection element.DSP S are generally used to control the external digital hardware, or process input signal and structure output signal in the description form which consist of equations.2.2 Basic Design Structures Of MicrocontrollersThe microcontrollers belong to the large family of single chip digital processors, so the hardware and software structure class of the former equivalent to the later. Their software structures include RISC structure and CISC structure, and hardware structures include Princeton structure andHarvard structure.2.2.1 Basic Instruction Structures Of CISC And RISCCISC structure refers to a kind of structure of Complex Instruction Set Computer. RISC structure refers to a kind of Reduced Instruction Set Computer. The main difference between them consists in the instruction structures. In the following differentiations and comparisons between them are discussed.1. Operation speedUsually, the operation speed of RISC is higher than CISC, though some processors of CISC type are regarded as one of RISC-like type. Many processors of CISC type implement the operation code with higher speed than the processors of RISC type, or implement some higher level technologies, which the RISC type can not realize.2. Instruction storage and implementationIn CISC, usually a lot of instructions are stored in the processors, and implement different steps of a single operation, such as direct data fetching out or filling in, and symbol register test. Each operation to be implemented requires an instruction-combination arranged by the designer.In RISC, usually each instruction stored in the processor exists as a least unit basing on which the user himself designs the required operations; this isn’t done by the designer.For example ,a STACK process includes two operation sets, PUSH and POP. The PUSH operation set is implemented at the start of a interrupt process and consists of putting all related data, addresses and state symbols, orderly, to the stack registers where they will stay, POP operation is implemented after the interrupt process and consists of putting all related data, addresses and state symbols, in opposite order, from the stack register, where they stays. Implementing all operations in RISC processors mentioned aboverequire only two instructions: “take out data from register” and “put data into register”, but a lot of programming tasks done by the user, meanwhile, in CISC processors, two instructions are required for implementing all the same operation, POP and PUSH, which are designed and programmed by the designer and then supplied to the users as a product.Basic Hardware Structures: Harvard Structure and Princeton StructureThe Harvard and Princeton structure are two computer hardware structures established by the expert of Harvard University and Princeton University in 1970 to satisfy the public requirement, in order to suit the high operation speed and variations of environment conditions.The principle of Princeton structure is shown as in Figure2.3. In this structure a common memory is arrayed, in order to store the control program and the data structure, such as variables and stack. In this structure a memory interface is used to construct an arbitrary channel, directing to the memory space, for supporting the data transmission between the processor and the internal registers.The problem of Princeton structure is “bottle neck” effect which appears when data of many channels are taken out or put in within a short time, so that the data flow is resisted.In the Harvard structure, shown in Figure 2.4, there are flexible connections and interfaces among the processor, control memory, register space and stack, as a result, the “bottle neck” effect and the data resistance can be avoided, the advantage of Princeton structure often can be shown when a set of complex operation system is to be implement.2.3 Chip Technology Of PMOS、NMOS、BMOS And CMOSAlong with the development of manufacture, like all other electronic products, the microcomputers have been growing smaller and smaller, running faster an faster, consuming less and less power, and becomingcheaper and cheaper, primarily due to improvements in the manufacturing processes and technologies, especially in the material processing technologies. The “CMOS” logic technology, a currently widely used material processing technique for microcontrollers, has made a large contribution to provide the computer functions and electrical interfaces. This is primarily a “push-pull”technology combining a “PMOS” and“NMOS” transistor together shown in Figure 2.5. It consists in a CMOS inverter working as a “NOT” gate, where the PMOS transistor is conducted(or“on”) and the NMOS transistor is blocked(or “off”), when the input signal is a low voltage level. Namely, the transistor, playing the role as a “switch” at V CC will be “on”, supplying V CC to the signal output responding to an input signal held on low voltage level. Contrarily, when receiving a signa l “high”, the NMOS transistor will be turn on, pulling the output line to GROUND (marked as GND) to provide an output signal “low”. The full names of the three terms mentioned are given below.1. PMOS or NMOS-P- channel Metal Oxide Semiconductor. This material technology was earlier used in the microprocessor manufacture history for microcomputers of types PMOS and NMOS.2. BMOS-Bipolar Metal Oxide Semiconductor. This technology includes BINMOS (Bipolar NMOS) and BIPMOS.3. CMOS-Complementary Metal Oxide Semiconductor. In this logic technique advantages of two silicon crystal structure types are optimally developed in combination, as shown in Figure 2.5, so the microcomputers have the advantages such as low power consumption, micro value, high operation speed and large capacity.Getting into the chip technologies deeper and deeper, some important terms and problems, mentioned below, can be explained more and more clearly.1. Power consumption and working frequencyDuring a state transition mentioned above, the amount of current flowing through the transistor is very small. As the working frequency increase, the current flows more often in a given time period, so that the average current, namely power consumption of device, must go up.2. Sleep modeIn this working mode no input signal is received, or no operation reacts to any input signal, namely no gates are switching so that no current flows through the device, thus the power consumption falls nearly to zero.3. Signal switching pointBefore using any devices, it is important to check if the input signal switching point matches the input threshold level of the device. For CMOS devices this is, typically, 1.4 V to one-half of V CC, but it can be different from types.4. High-and low-voltage levelCMOS can interface directly with most positive logic technologies, where logic value“1”is represented by high-voltage level, and logic value“0”-by low. Thus, it is important to make sure that a high-voltage level can be differentiated from a low in all circumstances, i. e., a “high” input is always above the voltage-switching threshold level,2.4 Basic Operation Process Of MicrocontrollersThe most basic operation process of a microcontroller consists of the following steps shown as in Figure 2.6.1. Instruction fetching-The CPU takes out an instruction from one of the rooms of internal or external control memory, ROM, according to the address calculated in the last step and recognizes the contents of the instruction.2. Instruction number calculating-The instruction number calculator of the CPU calculates the instruction number, namely, adds 1 to the number calculated in the last step.3. Instruction implementing-The operation system controlled by CPU implements the operation under the guiding of the content of the instruction.4. Address calculating-The address calculator calculates the next address, namely, plus an address increment to the last calculated address.5. Repeating-Going back to step 1 and starting the next cycle.All steps of a process are controlled by the operating logical control system and synchronized by the timing system with the help of an internally or externally supported clock system.2.5 Cycles Running In MicrocontrollersUsually there are 5 concepts of cycles defined for describing the implementation process of a microcontroller: clock cycle, machine cycle, instruction cycle, taps cycle (P cycle) and state cycle (S cycle). A short description will be given for each one as fellows.Clock cycle is the least basic cycle, called cycle of clock pulse as well. This cycle is produced internally or externally by an oscillation circuit such as crystal oscillator system, driven by an internal electronic energy source circuit, and equals to a natural cycle of the oscillation element.Machine cycle means a time interval for implementing a basic operation step.Instruction cycle refers to needed time interval for implementing an instruction.Tap cycle, marked as “P”, refers to a time interval, which equals to N *(clock cycle), where N is an integer.State Cycle, marked as “S”, is defined as 1 clock cycle and equals to 2 Ps.C51. If a crystal element of working frequency, 1 MHz, is selected to be used in the clock system, then 1 clock cycle equals to 1 us, 1 machine cycle is defined as 12 clock cycles and equals to 12 us; 1 instruction cycle Equals to 1 or 2 machine cycle(s) depending on the instruction lengthand mode, and equals to 12 or 24 clock cycles, i.e. 12 or 24 us.2.6 Basic Working Conditions And Center Function BlocksThe basic hardware-conditions for normally running an essential microcontroller system, or called least microcontroller system, configured according the basic conditions, are shown in Figure 2.7 based on an example of 80C51 microcontroller chip. In the essential system each peripheral element and related circuit plays a role in insuring and protesting normal operation of the microcontroller.2.6.1 PowerVirtually all microcontrollers today are built by using CMOS technology. They require significantly less power than the older, but usually use batteries and relies on “super-capacitors” for safe operation during power outages, thus minimizing power consumption becomes important. There are three conditions to be considered.1. Intrinsic power-the power required only for running the microcontroller.2. I/O Drive Power-the power taken into account for the power consumption when the microcontroller is sinking the current from or raising the current to external I/O devices.3. Sleep/Standby power-the power used when the microcontroller stays in “sleep”/“standby” state and is waiting for a specific external event.Many chips have robust power handling circuitries to fit the wide variety of different applications and power sources, ranging from 1 V to 6V.Different terms can be used to describe powers of different devices (Figure 2.7 shown above), such as V CC or V DD:high level, usually ranging from +2 V TO +5 V, V SS or GND (Ground).When applying a microcontroller, an important problem to consider isprotesting the power supply input from the complex power environment disturbance. A practical and reliable resolution is to use a tantalum capacitor of about 0.1 uF installed between the V CC (V DD) and GND (like C2 and C3) to filter the high frequency part of the input voltage, so that the device can handle great I/O current transients without causing inadvertent resets or data corruption. C3is designed for avoiding inductance effect which often happens because of the disturbance of high frequency radio wave.2.6.2 ResetIn order to ensure a microcontroller to run at a valid power conditions, a reset system such as the one consists of C1,R1, and S1 shown in Figure 2.7, are usually set up at the chip connected with its RESET-leg. This enables the chip to have two functions: restart function and power on stay function, detailed as fellows.1. Restart functionThis function performs the following process:If the switch, S1, is turned on when the chip is running, the connection between V CC and RESET pin leads the current flowing from V CC to the pin, so that the pin holds on a higher level and the operation logic of the chip turns back to initial state, or say, the address pointer of operation logic turns to initial address. Through the manual turning on of S1, the operation logic can get out from the tangle, such as unlimited cycle caused by external disturbance.2. Power on delay functionThis function performs the following process:At the moment when the power supply is turned on, the charging of C1 through R1leads a current flowing from RESET leg to V CC, and set the RESET pin on the high level, so that a RESET process like the one mentioned above happens, and the initial state is held until the charging isfinished and the current disappears. This process can hold the operation logic delaying at initial state, until the power condition get into stable state.2.6.3 System Clock/OscillatorsWhen running, each operation step of a microcontroller must follow an accurate time order system based on an externally or internally provided stable pulse series with constant frequency like a clock. The system, providing such pulse series, called clock signal system, or simply-“clock”, consists in an oscillator circuit driven (shown in Figure 2.7, where C L is a crystal oscillator, C4 and C5 are load for holding the oscillator system stable) by an energy source which vibrates sympathetically with the circuit and provides energy for it.Most microcontrollers are designed to be able to run within wide frequency band: from 0 to 100 GHz, the practical value of which is determined by the selected frequency value of the crystal oscillator.Another methods used for providing clocks are “RC oscillator” and an arbitrary external circuit or element, which provides a stable clock signal series. The first one uses the characteristic rise/fall time of a RC network, thus, it is the cheapest one, but not accurate enough.Some microcontrollers have internal RC or “ring”oscillators without any external parts, usually enabled by a configuration register programmed with the control store.2.6.4 Level-And-Phase Converting ElementIn order to connect the microcontrollers(using CMOS communication protocol with the logical“0”:low level normally) with personal computer or other equipment(using RS-232 communication protocol with the logical“1”:-8~ -12 V,a nd logical“0”:+8~ +12V, normally), a potential-and-phase converting element is used to convert the serial signals of CMOS protocolsystem, coming from or going tip microcontrollers, into one of RS-232 protocol system, going to or coming from personal computer or other 232-type equipments(Figure 2.7,C V).2.6.5 Latch ElementWhen being used in parallel communication bus, the latch element (Figure 2.7, K C) functions as a relay station serving for address lines to hold the address data temporarily when the address lines work as data lines temporarily. This will be detailed in the following lessons.2.6.6 Timing Monitor Equipment (Watchdog)An external equipment or internal function block called Timing Monitor (Watchdog) is used for microcontroller. This element or function block can lead the operation process back to its initial state by implementing their counter and overflow signal if the operation system runs into unlimited repetition state or wrong path state accidentally, and disable this function by “clear up” signal sent by microcontroller, if it runs normally.The external and internal Watchdogs play the same role for causing a reset operation of the microcontroller. This is performed when the Watchdog is not updated within a predetermined time interval (usually from milliseconds to several seconds).Effective applications of a microcontroller are determined by its rational operation, and the later is based on the intelligent constitution of operations of all functional blocks built in the microcontroller. In the following the basic functional blocks of microcontrollers will be typically introduced.第二章微控制器的概述微控制器是一个用于存储程序信息和数据的单芯片器件。

单片机基础毕业设计外文翻译

单片机基础毕业设计外文翻译

本科生毕业设计(论文)外文翻译毕业设计题目:外文题目:Fundamentals of Single-chip Microcomputer 译文题目:单片机基础学院:信息科学与工程学院专业班级:电子信息工程0802班学生姓名:指导教师:外文原文Fundamentals of Single-chip MicrocomputerDr. Dobbs MacintoshJournalAbstractT h e s i n gl e-chi p m i c r o com pu t er i s t h e cul m i na t i on of bo t h t h e d e v el opm e nt o f t h e di gi t al c om p ut e r a nd t h e i nt e gra t e d c i r c ui t a rgu a b l y t h e t ow m o st s i gn i fi c ant i nv en t i on s of t h e 20t h ce n t u r y .T h es e t o w t yp e s o f a rc hi t e c t u r e a r e fo un d i n s i n gl e-c hi p m i c r o com pu t e r.S om e e m p l o y t h e s pl i t p ro gr a m/d at a m em o r y o f t h e H a r v a rd a r ch i t e ct u r e, s ho wn i n F i g.3-5A-1, ot h er s f o l l o w t he p hi l o so ph y,w i d e l y a d a p t ed f o r ge n e r al-pu rp os e com p ut e rs and m i c r op r oc e s s o rs,of m ak i n g n o l o gi c al di s t i nc t i on be t w ee n p ro gr a m a n d d at a m em o r y a s i n t h e P r i n c et on ar c hi t e ct u r e.In ge n e r a l t er m s a si n gl e-c hi p m i cro c om put e r i s c ha r ac t e ri z ed b y t h e i n co r po r at i o n o f al l t h e u ni t s o f a c om put e r i n t o a s i n gl e d e vi c e.Keyword: Single-chip Microcomputer ROM RAM Programming Algorithm Features• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory– Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-level Program Memory Lock• 128 x 8-bit Internal RAM• 32 Programmable I/O Lines• Two 16-bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low-power Idle and Power-down ModesDescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard MCS-51 instruction set and pinout. Theon-chipFlash allows the program memory to be reprogrammed in-system or by a conventionalnonvolatile memory programmer. By combining a versatile 8-bit CPU with Flashon a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which providesa highly-flexible and cost-effective solution to many embedded control applications.The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vector two-level interrupt architecture,a full duplex serial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logicfor operation down to zero frequency and supports twosoftware selectable power saving modes. The Idle Modestops the CPU while allowing the RAM, timer/counters,serial port and interrupt system to continue functioning. ThePower-down Mode saves the RAM contents but freezesthe oscillator disabling all other chip functions until the nexthardware reset.Pin ConfigurationsBlock DiagramPin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as highimpedanceinputs.Port 0 may also be configured to be the multiplexed loworderaddress/data bus during accesses to external programand data memory. In this mode P0 has internalpullups.Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-orderaddress bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some control signals for Flash programmingand verification.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory.When theAT89C51 is executing code from external programmemory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes programexecution,from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Figure 1. Oscillator ConnectionsFigure 2. External Clock Drive ConfigurationPower-down ModeIn the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.Programming the FlashThe AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program theAT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms.Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by theRDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erasedby using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.外文资料翻译译文单片机基础摘要:单片机是电脑和集成电路发展的巅峰,有据可查的是它们也是20世纪最意义的两大发明。

单片机毕业设计外文翻译--单片机和keil

单片机毕业设计外文翻译--单片机和keil

附录A 外文文献The SCM and µVision2一、Principle of MCUSingle-chip is an integrated on a single chip a complete computer system. Even though most of his features in a small chip, but it has a need to complete the majority of computer components: CPU, memory, internal and external bus system, most will have the Core. At the same time, such as integrated communication interfaces, timers, real-time clock and other peripheral equipment. And now the most powerful single-chip microcomputer system can even voice, image, networking, input and output complex system integration on a single chip.Also known as single-chip MCU (Microcontroller), because it was first used in the field of industrial control. Only by the single-chip CPU chip developed from the dedicated processor. The design concept is the first by a large number of peripherals and CPU in a single chip, the computer system so that smaller, more easily integrated into the complex and demanding on the volume control devices. INTEL the Z80 is one of the first design in accordance with the idea of the processor, From then on, the MCU and the development of a dedicated processor parted ways.Early single-chip 8-bit or all of the four. One of the most successful is INTEL's 8031, because the performance of a simple and reliable access to a lot of good praise. Since then in 8031 to develop a single-chip microcomputer system MCS51 series. Based on single-chip microcomputer system of the system is still widely used until now. As the field of industrial control requirements increase in the beginning of a 16-bit single-chip, but not ideal because the price has not been very widely used. After the 90's with the big consumer electronics product development, single-chip technology is a huge improvement. INTEL i960 Series with subsequent ARM in particular, a broad range of applications, quickly replaced by 32-bit single-chip 16-bit single-chip high-end status, and enter the mainstream market. Traditional 8-bit single-chip performance has been the rapid increase in processing power compared to the 80's to raise a few hundred times. At present, the high-end 32-bit single-chip frequency over 300MHz, the performance of the mid-90's close on the heels of a special processor, while the ordinary price of the model dropped to one U.S. dollars, the most high-end models, only 10 U.S. dollars. Contemporary single-chip microcomputer system is no longer only the bare-metal environment in the development and use of a large number of dedicated embedded operating system is widely used in the full range of single-chip microcomputer. In PDAs and cell phones as the core processing of high-end single-chip or even a dedicated direct access to Windows and Linux operating systems.More than a dedicated single-chip processor suitable for embedded systems, so it was up to the application. In fact the number of single-chip is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will have a single-chip integration. Phone, telephone, calculator, home appliances, electronic toys, handheld computers and computer accessories such as a mouse in the Department are equipped with 1-2 single chip. And personal computers also have a large number of single-chip microcomputer in the workplace. Vehicles equipped with more than 40 Department of the general single-chip, complex industrial control systems and even single-chip may have hundreds of work at the same time! SCM is not only far exceeds the number of PC and other integrated computing, evenmore than the number of human beings.Hardwave introductionThe 8051 family of micro controllers is based on an architecture which is highly optimized for embedded control systems. It is used in a wide variety of applications from military equipment to automobiles to the keyboard on your PC. Second only to the Motorola 68HC11 in eight bit processors sales, the 8051 family of microcontrollers is available in a wide array of variations from manufacturers such as Intel, Philips, and Siemens. These manufacturers have added numerous features and peripherals to the 8051 such as I2C interfaces, analog to digital converters, watchdog timers, and pulse width modulated outputs. Variations of the 8051 with clock speeds up to 40MHz and voltage requirements down to 1.5 volts are available. This wide range of parts based on one core makes the 8051 family an excellent choice as the base architecture for a company's entire line of products since it can perform many functions and developers will only have to learn this one platform.The basic architecture consists of the following features:·an eight bit ALU·32 descrete I/O pins (4 groups of 8) which can be individually accessed·two 16 bit timer/counters·full duplex UART·6 interrupt sources with 2 priority levels·128 bytes of on board RAM·separate 64K byte address spaces for DATA and CODE memoryOne 8051 processor cycle consists of twelve oscillator periods. Each of the twelve oscillator periods is used for a special function by the 8051 core such as op code fetches and samples of the interrupt daisy chain for pending interrupts. The time required for any 8051 instruction can be computed by dividing the clock frequency by 12, inverting that result and multiplying it by the number of processor cycles required by the instruction in question. Therefore, if you have a system which is using an 11.059MHz clock, you can compute the number of instructions per second by dividing this value by 12. This gives an instruction frequency of 921583 instructions per second. Inverting this will provide the amount of time taken by each instruction cycle (1.085 microseconds).二、etting Started with µVision2The Keil Software 8051 development tools listed below are programs you use to compile your C code, assemble your assembly source files, link and locate object modules and libraries, create HEX files, and debug your target program.µVision2 for Windows™ is an In tegrated Development Environment that combines project management, source code editing, and program debugging in one single, powerful environment.The C51 ANSI Optimizing C Cross Compiler creates relocatable object modules from your C source code.The A51 Macro Assembler creates relocatable object modules from your 8051 assembly source code.The BL51 Linker/Locator combines relocatable object modules created by the C51 Compiler and the A51 Assembler into absolute object modules.The LIB51 Library Manager combines object modules into libraries that may be used by the linker.The OH51 Object-HEX Converter creates Intel HEX files from absolute object modules.The RTX-51 Real-time Operating System simplifies the design of complex, time-critical software projects.Software Development CycleWhen you use the Keil Software tools, the project development cycle is roughly the same as it is for any other software development project.1. Create a project, select the target chip from the device database, and configure the tool settings.2. Create source files in C or assembly.3. Build your application with the project manager.4. Correct errors in source files.5. Test the linked application.µVision2 IDEThe µVision2 IDE combines project management, a rich-featured editor with interactive error correction, option setup, make facility, and on-line help. Use µVision2 to create your source files and organize them into a project that defines your target application. µVision2 automatically compiles, assembles, and links your embedded application and provides a single focal point for your development efforts.LIB51 Library ManagerThe LIB51 library manager allows you to create object library from the object files created by the compiler and assembler. Libraries are specially formatted, ordered program collections of object modules that may be used by the linker at a later time. When the linker processes a library, only those object modules in the library that are necessary to create the program are used.BL51 Linker/LocatorThe BL51 linker creates an absolute object module using the object modules extracted from libraries and those created by the compiler and assembler. An absolute object file or module contains no relocatable code or data. All code and data reside at fixed memory locations. The absolute object file may be used:To program an EPROM or other memory devices,With the µVision2 Debugger for simulation and target debugging,With an in-circuit emulator for the program testing.µVision2 DebuggerThe µVision2 symbolic, source-level debugger is ideally suited for fast, reliable program debugging. The debugger includes a high-speed simulator that let you simulate an entire 8051 system including on-chip peripherals and external hardware. The attributes of the chip you use are automatically configured when you select the device from the Device Database.The µVision2 Debugger provides several ways for you to test your programs on real target hardware:Install the MON51 Target Monitor on your target system and download your program using the Monitor-51 interface built-in to the µVision2 Debugger.Use the Advanced GDI interface to attach use the µVision2 Debugger front end with your target system.Monitor-51The µVision2 Debugger supports target debugging using Monitor-51. The monitor program resides in the memory of your target hardware and communicates with the µVision2 Debugger using the serial port of the 8051 and a COM port of your PC. With Monitor-51, µVision2 lets you perform source-level, symbolic debugging on your target hardware.RTX51 Real-Time Operating SystemThe RTX51 real-time operating system is a multitasking kernel for the 8051 microcontroller family. The RTX51 real-time kernel simplifies the system design, programming, and debugging of complex applications where fast reaction to time critical events is essential. The kernel is fully integrated into the C51 Compiler and is easy to use. Task description tables and operating system consistency are automatically controlled by the BL51 linker/locator.C51 Optimizing C Cross CompilerThe Keil C51 Cross Compiler is an ANSI C Compiler that was writtenspecifically to generate fast, compact code for the 8051 microcontroller family.The C51 Compiler generates object code that matches the efficiency and speed of assembly programming.Using a high-level language like C has many advantages over assembly language programming:Knowledge of the processor instruction set is not required. Rudimentary knowledge of the memory structure of the 8051 CPU is desirable (but not necessary).Details like register allocation and addressing of the various memory types and data types is managed by the compiler.Programs get a formal structure (which is imposed by the C programming language) and can be divided into separate functions. This contributes to source code reusability as well as better overall application structure.The ability to combine variable selection with specific operations improves program readability.Keywords and operational functions that more nearly resemble the human thought process may be used.Programming and program test time is drastically reduced.The C run-time library contains many standard routines such as: formatted output, numeric conversions, and floating-point arithmetic.Existing program parts can be more easily included into new programs because of modular program construction techniques.The language C is a very portable language (based on the ANSI standard) that enjoys wide popular support and is easily obtained for most systems.Existing program investments can be quickly adapted to other processors as needed.Code OptimizationsThe C51 Compiler is an aggressive optimizing compiler that takes numerous steps to ensure that the code generated and output to the object file is the most efficient (smallest and/or fastest) code possible. The compiler analyzes the generated code to produce the most efficient instruction sequences. This ensures that your C program runs as quickly and effectively as possible in the least amount of code space.The C51 Compiler provides nine different levels of optimizing. Each increasing level includes the optimizations of levels below it. The following is a list of all optimizations currently performed by the C51 Compiler.General OptimizationsConstant Folding: Constant values occurring in an expression or address calculation are combined as a single constant.Jump Optimizing: Jumps are inverted or extended to the final target address when the program efficiency is thereby increased.Dead Code Elimination: Code that cannot be reached (dead code) is removed from the program.Register Variables: Automatic variables and function arguments are located in registers whenever possible. No data memory space is reserved for these variables.⌝Parameter Passing Via Registers: A maximum of three function arguments⌝may be passed in registers.Global Common Subexpression Elimination: Identical subexpressions or address calculations that occur multiple times in a function are recognized and calculated only once whenever possible.Common Tail Merging: Common instruction blocks are merged together using jump instructions.Re-use Common Entry Code: Common instruction sequences are moved in front of a function to reduce code size.二、Principle of MCUSingle-chip is an integrated on a single chip a complete computer system. Even though most of his features in a small chip, but it has a need to complete the majority of computer components: CPU, memory, internal and external bus system, most will have the Core. At the same time, such as integrated communication interfaces, timers, real-time clock and other peripheral equipment. And now the most powerful single-chip microcomputer system can even voice, image, networking, input and output complex system integration on a single chip.Also known as single-chip MCU (Microcontroller), because it was first used in the field of industrial control. Only by the single-chip CPU chip developed from the dedicated processor. The design concept is the first by a large number of peripherals and CPU in a single chip, the computer system so that smaller, more easily integrated into the complex and demanding on the volume control devices. INTEL the Z80 is one of the first design in accordance with the idea of the processor, From then on, the MCU and the development of a dedicated processor parted ways.Early single-chip 8-bit or all of the four. One of the most successful is INTEL's 8031, because the performance of a simple and reliable access to a lot of good praise. Since then in 8031 to develop a single-chip microcomputer system MCS51 series. Based on single-chip microcomputer system of the system is still widely used until now. As the field of industrial control requirements increase in the beginning of a 16-bit single-chip, but not ideal because the price has not been very widely used. After the 90's with the big consumer electronics product development, single-chip technology is a huge improvement. INTEL i960 Series with subsequent ARM in particular, a broad range of applications, quickly replaced by 32-bit single-chip 16-bit single-chip high-end status, and enter the mainstream market. Traditional 8-bit single-chip performance has been the rapid increase in processing power compared to the 80's to raise a few hundred times. At present, the high-end 32-bit single-chip frequency over 300MHz, the performance of the mid-90's close on the heels of a special processor, while the ordinary price of the model dropped to one U.S. dollars, the most high-end models, only 10 U.S. dollars. Contemporary single-chip microcomputer system is no longer only the bare-metal environment in the development and use of a large number of dedicated embedded operating system is widely used in the full range of single-chip microcomputer. In PDAs and cell phones as the core processing of high-end single-chip or even a dedicated direct access to Windows and Linux operating systems.More than a dedicated single-chip processor suitable for embedded systems, so it was up to the application. In fact the number of single-chip is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will have a single-chip integration. Phone, telephone, calculator, homeappliances, electronic toys, handheld computers and computer accessories such as a mouse in the Department are equipped with 1-2 single chip. And personal computers also have a large number of single-chip microcomputer in the workplace. Vehicles equipped with more than 40 Department of the general single-chip, complex industrial control systems and even single-chip may have hundreds of work at the same time! SCM is not only far exceeds the number of PC and other integrated computing, even more than the number of human beings.Hardwave introductionThe 8051 family of micro controllers is based on an architecture which is highly optimized for embedded control systems. It is used in a wide variety of applications from military equipment to automobiles to the keyboard on your PC. Second only to the Motorola 68HC11 in eight bit processors sales, the 8051 family of microcontrollers is available in a wide array of variations from manufacturers such as Intel, Philips, and Siemens. These manufacturers have added numerous features and peripherals to the 8051 such as I2C interfaces, analog to digital converters, watchdog timers, and pulse width modulated outputs. Variations of the 8051 with clock speeds up to 40MHz and voltage requirements down to 1.5 volts are available. This wide range of parts based on one core makes the 8051 family an excellent choice as the base architecture for a company's entire line of products since it can perform many functions and developers will only have to learn this one platform.The basic architecture consists of the following features:·an eight bit ALU·32 descrete I/O pins (4 groups of 8) which can be individually accessed·two 16 bit timer/counters·full duplex UART·6 interrupt sources with 2 priority levels·128 bytes of on board RAM·separate 64K byte address spaces for DATA and CODE memoryOne 8051 processor cycle consists of twelve oscillator periods. Each of the twelve oscillator periods is used for a special function by the 8051 core such as op code fetches and samples of the interrupt daisy chain for pending interrupts. The time required for any 8051 instruction can be computed by dividing the clock frequency by 12, inverting that result and multiplying it by the number of processor cycles required by the instruction in question. Therefore, if you have a system which is using an 11.059MHz clock, you can compute the number of instructions per second by dividing this value by 12. This gives an instruction frequency of 921583 instructions per second. Inverting this will provide the amount of time taken by each instruction cycle (1.085 microseconds).附录B 中文译文单片机和keil一、单片机原理单片机是指一个集成在一块芯片上的完整计算机系统。

单片机毕业设计外文翻译10

单片机毕业设计外文翻译10

一、外文原文:The single slice machine is also called tiny controller, is because it was used in the industry to control realm at the earliest stage. Single slice machine from inside chip have CPU appropriation processor to develop only since then. At the earliest stage of design the principle is to pass to integrate a great deal of peripherals and CPU in a chip, making calculator system smaller, integrating more easily into complicated of but to mention to request a strict control equipments in the middle. The INTEL Z80 is the processor which designed according to this kind of thought at the earliest stage, from now on, single slice the development of the machine and appropriation processor went by different roads then.The single slice of the earlier period all of machines are 8 or 4.Among them, the INTEL is most successful of 8031, because of in brief dependable but the function was quite good to acquire very big good opinion.Henceforth at 8031 up developed MCS51 serieses a single slice machine system.According to the single slice of this system machine system is still in the extensive usage till now.Because the industry controls the exaltation of[with] realm request, starting appearing 16 single slice machine, but because sex price wanted to don't get a very extensive application than the disregard.Develop greatly along with the consumption electronics product after 90's, the single slice machine technique got a huge exaltation. Along with the extensive application of INTEL i960 serieses especially later ARM series, the 32 single slice machines replaces 16 single slice the high level position of the machine quickly, and gets into an essential market. And traditional of 8 single slice the function of the machine also got to fly to raise soon, handling an ability to compare with to raise few a hundred folds in 80's.Currently, 32 single slice of the high level with main machine already over 300 MHz, the function keeps appropriation processor of making track for the mid 90's, and the common model number factory price drop into to USD 1, tallest carry of model number also only USD 10.The contemporary and single slice machine system has already no longer developed and used just under the naked machine environment, the in great quantities appropriative built-in operate system is applied extensively in the whole seriousness of the single slice is on board. But Be using the high level of handheld PC and cellular phone core processing single slice the machine even can use appropriative Windows and the Linux operate system directly.Single slice the machine ratio appropriation processor is the most suitable to match to apply in the built-in system, so it got the most applications. In fact the single slice machine is an amount the most calculators are in the world. The modern mankind are living medium use of assemble in almost each electronics and machine product have a single slice machine. All have 1-2 single slice machine in the computer accessoriness such as cellular phone, telephone, calculator, home appliances, electronics toy, handheld PC and mouse etc.. And personal computer in would also capable number not a few single slice the machine be working. Provide with morethan 40 departments a single slice machine generally on the car; complicated industry's controlling the top of the system even may has single several hundred pedestals slices machine to work in the meantime! Single slice the amount of the machine not only far above the PC machine and other calculations of comprehensive, even than the mankind's amount still want have another二、翻译内容单片机也被称为微控制器(Microcontroller),是因为它最早被用在工业控制领域。

单片机毕业设计外文文献翻译

单片机毕业设计外文文献翻译

英文原文:80C518051 single-chip micro-computer, referred to as microcontrollers, there are known as micro-controller, a micro-computer re -To branch. SCM is developed in the mid 70s a large-scale integrated circuit chip, a CPU, RAM, ROM, I / O interfaces and interrupt system on the same silicon device. Since the 80s, Microcontroller rapid development, all kinds of new products are constantly emerging, there have been many high-performance of new models now become the field of factory automation and control of the pillar industries.Pin Function:MCS-51 is a standard 40-pin DIP IC chip, pin distribution ---- microcontroller pin diagram please refer to:P0.0 ~ P0.7 P0 port 8-bit bidirectional port lines (in the pin 39 to No. 32 terminal). P1.0 ~ P1.7 P1 port 8-bit bidirectional port line (pin 1 in the No. 8 terminal).P2.0 ~ P2.7 P2 port 8-bit bidirectional port lines (in the pin terminal 21 ~ 28).P3.0 ~ P3.7 P3 port 8-bit bidirectional port lines (in the pin terminal 10 ~ 17).This four I / O port has not exactly the same function, we can get to learn, and other books though, but written in too deep, difficult to understand for beginners, here are according to my own expression to write the I believe that you can understand.P0 port has three functions:1, external expansion memory, as the data bus (Figure 1 in D0 ~ D7 of data bus interface)2, external expansion memory, as the address bus (Figure 1 in A0 ~ A7 to address bus interface)3, is not extended, it can do a general I / O to use, but within the supreme pull-up resistor, as an input or output should be connected to an external pull-up resistor.P1 port Zhizuo I / O port to use: its internal pull-up resistor.P2 port has two functions:1,An extended external memory when used as an address bus2, doing a general I / O port used, and their internal pull-up resistor;P3 port has two functions:As well as I / O using the external (the internal pull-up resistor), there are some special features, from a special register to set the specific features please refer to our explanation behind the pin.Internal EPROM of the microcontroller chip (for example, 8751), for the writing process required to provide specialized programming and programming pulse power, these signals are also provided in the form from the signal pin, and Namely: programming pulse: 30 feet (ALE / PROG)Programming voltage (25V): 31 feet (EA / Vpp)In introducing the four I / O port referred to a "pull-up resistor" Then, pull-up resistor is what Dongdong do? What role does he play? Said the resistance that is of course, is a resistor, when as an input, the pull-up resistor pulled its potential, if the input is low you can provide a current source; Therefore, if the P0 port as long as the input, in the high impedance state, only an external pull-up resistor to be effective. ALE / PROG address latch control signal: in a system is extended, ALE is used to control the P0 port output low 8-bit address latch latch get together in order to achieve low address and data segregation. (In the back on the expansion of the curriculum, we will see the 8051 expansion of EEPROM circuit, the ALE and the 74LS373 in Figure G-latches connected to the external CPU to access when the time to lock the address low address, the P0 port output. ALE may be high may also be low, when the ALE is high, allowing address latch signal when accessing external memory, ALE signals a negative transition (from positive to negative) P0 port on the lower eight address signals into the latch. when ALE is low, when, P0 port on the content and the output latch line. on the latch, and we will be introduced later.In the absence of access to external memory during the period, ALE 1 / 6 oscillator frequency output cycle (ie, frequency of 6 points), when access to external memory to 1 / 12 oscillator cycle, the output (12 min frequency). From here we can see that when the system does not extend when the ALE will be 1 / 6 cycle, fixed frequency oscillator output, so can be used as an external clock, or the use of an external timing pulse.PORG pulse input for the program: In the fifth lesson MCU's internal structure and composition, we know that in 8051 within the a 4KB or 8KB of program memory (ROM), ROM's role is to be used to store user needs implementation of the program, then we are into how to write good programs into this ROM in it? Is actually programmed into the pulse input can be written, this pulse input port is PROG. PSEN external program memory read strobe: In reading an external ROM, PSEN low effective, in order to achieve an external ROM module read.1, the internal ROM reading, PSEN is not action;2, external ROM reading at each machine cycle will move twice;3, external RAM read, the two PSEN pulse is skipped will not be output;4, external ROM, and ROM-foot-phase OE.See Figure 2 - (8051 extension 2KB EEPROM circuit in Figure PSEN and expansion ROM in the OE pin-phase)EA / VPP access and sequence memory control signals1, then high time:CPU reads the internal program memory (ROM)Expansion of the external ROM: When reading the internal program memory than0FFFH (8051) 1FFFH (8052) automatically reads the external ROM.2, then low when: CPU to read external program memory (ROM). In the previous study, we are aware, there is no internal ROM MCU 8031, then 8031 microcontroller in the application, this pin is a low level of direct.3,8751 Shaoxie internal EPROM, to make use of this pin input voltage of 21V forShao Xie.RST Reset signal: when the input signal continuously high for more than two machine cycles when it is effective to complete the MCU reset initialization, when the reset program counter PC = 0000H, ie, after reset from the program memory of the 0000H unit to read the first script.External crystal oscillator pins XTAL1 and XTAL2. When using the chip internal clock, this two-pin for external quartz crystal and fine-tuning capacitor; when using an external clock, used to access an external clock pulse signal.VCC: Power Supply +5 V inputVSS: GND Ground.A VR and the pic are 8051 different structures with 8-bit microcontrollers, because structure is different, so assembly instructions are different, but distinct from the useof CISC instruction set of the 8051, they are RISC instruction set, and only a few dozen instructions, most instructions are single instruction cycle instruction, so in the same crystal frequency, faster than the 8051. Another PIC 8-bit microcontroller in previous years, is the world's largest MCU shipments, followed by Freescale microcontroller.ARM is actually 32-bit microcontroller, its internal resources (registers and peripheral functions) than in 8051 and PIC, A VR should be a lot more, with the computer's CPU chip is very close. Commonly used in mobile phones, routers and so on.DSP is actually a special kind of microcontroller, which from 8-32 are available here. It is specifically used to calculate the digital signals. Operation in some formulas, it's fastest computers than the current home of the CPU even faster. For example, the general 32-bit DSP instruction cycle in an op-End a 32-digit x 32-digit product coupled with a 32-digit. Applied to certain pairs of real-time processing requirements of the higher places中文译文:8051单片微型计算机简称为单片机,又称为微型控制器,是微型计算机的一个重要分支。

单片机【经典外文翻译】--单片机简介(译文+英文)—-毕业论文设计

单片机【经典外文翻译】--单片机简介(译文+英文)—-毕业论文设计

Singlechip brief introductionThe monolithic integrated circuit said that the monolithic micro controller, it is not completes some logical function the chip, but integrates a computer system to a chip on. Summary speaking: A chip has become a computer. Its volume is small, the quality is light, the price cheap, for the study, the application and the development has provided the convenient condition. At the same time, the study use monolithic integrated circuit is understands the computer principle and the structure best choice.The monolithic integrated circuit interior also uses with the computer function similar module, for instance CPU, memory, parallel main line, but also has with the hard disk behave identically the memory component, what is different is its these part performance is opposite our home-use computer weak many, but the price is also low, generally does not surpass 10 Yuan then ......Made some control electric appliance one kind with it is not the very complex work foot. We use now the completely automatic drum washer, the platoon petti-coat pipe, VCD and so on inside the electrical appliances may see its form! ......It is mainly takes the control section the core part.It is one kind of online -like real-time control computer, online -like is the scene control, needs to have the strong antijamming ability, the low cost, this is also and the off-line type computer (for instance home use PC) main difference.The monolithic integrated circuit is depending on the procedure, and may revise. Realizes the different function through the different procedure, particularly special unique some functions, this is other component needs to take the very big effort to be able to achieve, some are the flowered big strength is also very difficult to achieve. One is not the very complex function, if develops in the 50s with the US 74 series, or the 60s's CD4000 series these pure hardware do decides, the electric circuit certainly are a big PCB board! But if, if succeeded in the 70s with the US puts in the market the series monolithic integrated circuit, the result will have the huge difference! Because only the monolithic integrated circuit compiles through you the procedure may realize the high intelligence, high efficiency, as well as redundant reliability!Because the monolithic integrated circuit to the cost is sensitive, therefore present occupies the dominant status the software is the most preliminary assembly language, it was except the binary machine code above the most preliminary language, since why were such preliminary must use?Why high-level did the language already achieve the visualization programming level not to use? The reason is very simple, is the monolithic integrated circuit does not have home computer such CPU, also has not looked like the hard disk such mass memory equipment. Inside even if a visualization higher order language compilation script only then a button, also will achieve several dozens K the sizes! Does not speak anything regarding the home use PC hard disk, but says regarding the monolithic integrated circuit cannot accept. The monolithic integrated circuit in the hardware source aspect's use factor must very Gao Caixing, therefore assembly, although primitive actually massively is using. Same truth, if attains supercomputer's on operating system and the application software home use PC to come up the movement, home use PC could also not withstand.It can be said that the 20th century surmounted three “the electricity” the time, namely the electrical time, the Electronic Age and already entered computer time. However, this kind of computer, usually refers to the personal computer, is called PC machine. It by the main engine, the keyboard, the monitor and so on is composed. Also has a kind of computer, most people actually not how familiar. This kind of computer is entrusts with the intelligence each kind of mechanical monolithic integrated circuit (also to call micro controller). , This kind of computer's smallest system only has used as the name suggests a piece of integrated circuit, then carries on the simple operation and the control. Because its volume is small, usually hides in is accused the machinery “the belly”. It in the entire installment, plays is having like the human brains role, it went wrong, the entire installment paralyzed. Now, this kind of monolithic integrated circuit's use domain already very widespread, like the intelligent measuring appliance, the solid work paid by time control, the communication equipment, the guidance system, the domestic electric appliances and so on. Once each product used the monolithic integrated circuit, could get up causes the effect which the product turned to a new generation, often before product range crown by adjective - - “intelligence”, like intelligence washer and so on. Now some factory's technical personnel or other extra-curricular electronic exploiter do certain products, are not the electric circuit are too complex, is the function is too simple, and is imitated extremely easily. Investigates its reason, possibly on card, in the product has not used on the monolithic integrated circuit or other programmable logical component.中文文献译文单片机简介单片机又称单片微控制器,它不是完成某一个逻辑功能的芯片,而是把一个计算机系统集成到一个芯片上。

毕业设计外文翻译--89C51单片机

毕业设计外文翻译--89C51单片机

毕业设计外文翻译--89C51单片机The Description of AT89S511 General DescriptionThe AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.2 PortsPort 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory.In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I IL) because of the internal pull-ups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signalsduring Flash programming and verification.Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I IL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table.3 Memory OrganizationMCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.3.1 Program MemoryIf the EA pin is connected to GND, all program fetches are directed to externalmemory. On the AT89S51, if EA is connected to V CC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.3.2 Data MemoryThe AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.4 Watchdog Timer (One-time Enabled with Reset-out)The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.4.1 Using the WDTTo enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read orwritten. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.4.2 WDT DURING Power-down and IdleIn Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt, which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode.With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.5.InterruptsThe AT89S51 has a total of five interrupt vectors: two external interrupts(INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in Figure 6-1. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.6 Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 7-1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 7-2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.7 Idle ModeIn idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special function registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.8 Power-down ModeIn the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.AT89S51概述1 一般概述该AT89S51是一个低功耗,高性能CMOS 8位微控制器,可在4K字节的系统内编程的闪存存储器。

毕业设计-单片机相关外文文献翻译-人工修订精确版

毕业设计-单片机相关外文文献翻译-人工修订精确版

Structure and function of the MCS—51seriesStructure and function of the MCS—51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces。

This company introduced 8 top—grade one-chip computers of MCS-51 series in 1980 after introducing 8 one—chip computers of MCS—48 series in 1976。

It belong to a lot of kinds this line of one-chip computer the chips have,such as 8051,8031,8751,80C51BH,80C31BH,etc。

,their basic composition,basic performance and instruction system are all the same. 8051 daily representatives— 51 serial one-chip computers .An one—chip computer system is made up of several following parts: (1)One microprocessor of 8 (CPU). (2) At slice data memory RAM (128B/256B),it use not depositting not can reading /data that write,such as result not middle of operation,final result and data wanted to show,etc. ( 3)Procedure memory ROM/EPROM (4KB/8KB ),is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 ,8032,80C ,etc.。

毕业设计(论文)单片机英文中文翻译论文

毕业设计(论文)单片机英文中文翻译论文

毕业设计(论文)单片机英文中文翻译论文AT89S52FeaturesCompatible with MCS-51 Products8K Bytes of In-System Programmable ISP Flash Memory –Endurance 10000 WriteErase Cycles40V to 55V Operating RangeFully Static Operation 0 Hz to 33 MHzThree-level Program Memory Lock256 x 8-bit Internal RAM32 Programmable IO LinesThree 16-bit TimerCountersEight Interrupt SourcesFull Duplex UART Serial ChannelLow-power Idle and Power-down ModesInterrupt Recovery from Power-down ModeWatchdog Timer Dual Data PointerPower-off Flag Fast Programming TimeFlexible ISP Programming Byte and Page ModeGreen PbHalide-free Packaging OptionDescriptionThe AT89S52 is a low-power high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applicationsThe AT89S52 provides the following standard features 8K bytes of Flash 256 bytes of RAM 32 IO lines Watchdog timer two data pointers three 16-bit timercounters a six-vector two-level interrupt architecture a full duplex serial port on-chip oscillator and clock circuitry In addition the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes The Idle Mode stops the CPU while allowing the RAM timercounters serial port and interrupt system to continue functioning The Power-down mode saves the RAM con-tents but freezes the oscillator disabling all other chip functions until the next interrupt or hardware resetPin Description21 VCC Supply voltage22 GND Ground23 Port 0Port 0 is an 8-bit open drain bidirectional IO port As an output port each pin can sink eight TTL inputs When 1s are written to port 0 pins the pins can be used as high-impedance inputs Port 0 can also be configured to be the multiplexed low-order addressdata bus during accesses to external program and data memory In this mode P0 has internal pull-ups Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification External pull-ups are required during program verification24 Port 1Port 1 is an 8-bit bidirectional IO port with internal pull-ups The Port 1 output buffers can sinksource four TTL inputs When 1s are written to Port 1 pins they are pulled high by the inter-nal pull-ups and can be used as inputs As inputs Port 1 pins that are externally being pulled low will source current IIL because of the internal pull-ups In addition P10 and P11 can be configured to be the timercounter 2 external count input P10T2 and the timercounter 2 trigger input P11T2EX respectively as shown in the follow-ing tablePort 1 also receives the low-order address bytes during Flash programming and verificationPort Pin Alternate Functions P10 T2 external count input to TimerCounter 2 clock-out P11 T2EX TimerCounter 2 capturereloadtrigger and direction control P15 MOSI used for In-System Programming P16 MISO used for In-System Programming P17 SCK used for In-System Programming 25 Port 2Port 2 is an 8-bit bidirectional IO port with internal pull-ups The Port 2 output buffers can sinksource four TTL inputs When 1s are written to Port 2 pins they are pulled high by the inter-nal pull-ups and can be used as inputs As inputs Port 2 pins that are externally being pulled low will source current IIL because of the internal pull-ups Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses MOVX DPTR In this application Port 2 uses strong internal pull-ups when emitting 1s During accesses to external data memory that use 8-bit addresses MOVX RI Port 2 emits the contents of the P2 Special Function Register Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification26 Port 3Port 3 is an 8-bit bidirectional IO port with internal pull-ups The Port 3 output buffers can sinksource four TTL inputs When 1s are written to Port 3 pins they are pulled high by the inter-nal pull-ups and can be used as inputs As inputs Port 3 pins that are externally being pulled low will source current IIL because of the pull-ups Port 3 receives some control signals for Flash programming and verification Port 3 also serves the functions of various special features of the AT89S52as shown in the fol-lowing tablePort Pin Alternate Functions P30 RXD serial input portP31 TXD serial output port P32 external interrupt 0P33 external interrupt 1 P34 T0 timer 0 external inputP35 T1 timer 1 external input P36 external data memory write strobe P37 external data memory read strobe 27 RSTReset input A high on this pin for two machine cycles while the oscillator is running resets the device This pin drives high for 98 oscillator periods after the Watchdog times out The DISRTO bit in SFR AUXR address 8EH can be used to disable this feature In the default state of bit DISRTO the RESET HIGH out feature is enabled28 ALEAddress Latch Enable ALE is an output pulse for latching the low byte of the address during accesses to external memory This pin is also the program pulse input during Flash programming In normal operation ALE is emitted at a constant rate of 16 the oscillator frequency and may be used for external timing or clocking purposes Note however that one ALE pulse is skipped dur-ing each access to external data memory If desired ALE operation can be disabled by setting bit 0 of SFR location 8EH With the bit set ALE is active only during a MOVX or MOVC instruction Otherwise the pin is weakly pulled high Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode29 Program Store Enable is the read strobe to external programmemory When the AT89S52 is executing code from external program memory is activated twice each machine cycle except that two activations are skipped during each access to exter-nal data memory210 VPPExternal Access Enable must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH Note however that if lock bit 1 is programmed will be internally latched on reset should be strapped to VCC for internal program executions This pin also receives the 12-volt programming enable voltage VPP during Flash programming 211 XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit212 XTAL2Output from the inverting oscillator amplifierMemory OrganizationMCS-51 devices have a separate address space for Program and Data Memory Up to 64K bytes each of external Program and Data Memory can be addressed31 Program MemoryIf the pin is connected to GND all program fetches are directed to external memory On the AT89S52 if is connected to VCC program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory32 Data MemoryThe AT89S52 implements 256 bytes of on-chip RAM The upper 128 bytes occupy a parallel address space to the Special Function Registers This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space When an instruction accesses an internal location above address 7FH the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space Instructions which use direct addressing access the SFR space For example the following direct addressing instruction accesses the SFR at location 0A0H which is P2MOV 0A0H dataInstructions that use indirect addressing access the upper 128 bytes of RAM For example the following indirect addressing instruction where R0 contains 0A0H accesses the data byte at address 0A0H rather than P2 whose address is 0A0HMOV R0 dataNote that stack operations are examples of indirect addressing so the upper 128 bytes of data RAM are available as stack spaceWatchdog Timer One-time Enabled with Reset-outThe WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets The WDT consists of a 14-bit counter and the Watchdog Timer Reset WDTRST SFR The WDT is defaulted to disable from exiting reset To enable the WDT a user must write 01EH and 0E1H insequence to the WDTRST register SFR location 0A6H When the WDT is enabled it will increment every machine cycle while the oscillator is running The WDT timeout period is dependent on the external clock frequency There is no way to disable the WDT except through reset either hardware reset or WDT overflow reset When WDT over-flows it will drive an output RESET HIGH pulse at the RST pin41 Using the WDTTo enable the WDT a user must write 01EH and 0E1H in sequence to the WDTRST register SFR location 0A6H When the WDT is enabled the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow The 14-bit counter overflows when it reaches 16383 3FFFH and this will reset the device When the WDT is enabled it will increment every machine cycle while the oscillator is running This means the user must reset the WDT at least every 16383 machine cycles To reset the WDT the user must write 01EH and 0E1H to WDTRST WDTRST is a write-only register The WDT counter cannot be read or written When WDT overflows it will generate an output RESET pulse at the RST pin The RESET pulse dura-tion is 98xTOSC where TOSC 1FOSC To make the best use of the WDT it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset42 WDT During Power-down and IdleIn Power-down mode the oscillator stops which means the WDT also stopsWhile in Power-down mode the user does not need to service the WDT There are two methods of exiting Power-down mode by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode When Power-down is exited with hardware reset servicing the WDT should occur as it normally does whenever the AT89S52 is reset Exiting Power-down with an interrupt is significantly different The interrupt is held low long enough for the oscillator to stabilize When the interrupt is brought high the interrupt is serviced To prevent the WDT from resetting the device while the interrupt pin is held low the WDT is not started until the interrupt is pulled high It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode To ensure that the WDT does not overflow within a few states of exiting Power-down it is best to reset the WDT just before entering Power-down mode Before going into the IDLE mode the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled The WDT keeps counting during IDLE WDIDLE bit 0 as the default state To prevent the WDT from resetting the AT89S52 while in IDLE mode the user should always set up a timer that will periodically exit IDLE service the WDT and reenter IDLE mode With WDIDLE bit enabled the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE5 UARTThe UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C526 Timer 0 and 1Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C527 Timer 2Timer 2 is a 16-bit TimerCounter that can operate as either a timer or an event counter The type of operation is selected by bit C in the SFR T2CON Timer 2 has three operating modes capture auto-reload up or down counting and baud rate generator The modes are selected by bits in T2CON as shown in Table 6-1 Timer 2 consists of two 8-bit registers TH2 and TL2 In the Timer function the TL2 register is incremented every machine cycle Since a machine cycle consists of 12 oscillator periods the count rate is 112 of the oscil-lator frequencyTable 6-1 Timer 2 Operating ModesRCLK TCLK CP TR2 MODE 0 0 1 16-bit Auto-reload 01 1 16-bit Capture 1 X 1 Baud Rate Generator XX 0 Off In the Counter function the register is incremented in response to a 1-to-0 transition at its corre-sponding external input pin T2 In this function the external input is sampled during S5P2 of every machine cycle When the samples show a high in one cycle and a low in the next cycle the count is incremented The new count value appears in theregister during S3P1 of the cycle following the one in which the transition was detected Since two machine cycles 24 oscillator periods are required to recognize a 1-to-0 transition the imum count rate is 124 of the oscillator frequency To ensure that a given level is sampled at least once before it changes the level should be held for at least one full machine cycle71 Capture ModeIn the capture mode two options are selected by bit EXEN2 in T2CON If EXEN2 0 Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON This bit can then be used to generate an interrupt If EXEN2 1 Timer 2 performs the same operation but a 1-to-0 transi-tion at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L respectively In addition the transition at T2EX causes bit EXF2 in T2CON to be set The EXF2 bit like TF2 can generate an interrupt72 Auto-reload Up or Down CounterTimer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode This feature is invoked by the DCEN Down Counter Enable bit located in the SFR T2MOD Upon reset the DCEN bit is set to 0 so that timer 2 will default to count up When DCEN is set Timer 2 can count up or down depending on the value of the T2EX pin Timer 2 automatically counting up when DCEN 0 In this mode two options areselected by bit EXEN2 in T2CON If EXEN2 0 Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software If EXEN2 1 a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX This transition also sets the EXF2 bit Both the TF2 and EXF2 bits can generate an interrupt if enabled Setting the DCEN bit enables Timer 2 to count up or down as shown in Figure 10-2 In this mode the T2EX pin controls the direction of the count A logic 1 at T2EX makes Timer 2 count up The timer will overflow at 0FFFFH and set the TF2 bit This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers TH2 and TL2 respectively A logic 0 at T2EX makes Timer 2 count down The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution In this operating mode EXF2 does not flag an interrupt8 Baud Rate GeneratorTimer 2 is selected as the baud rate generator by setting TCLK andor RCLK in T2CON Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer1 is used for the other function Setting RCLK andor TCLK puts Timer2 into its baud rate generator mode The baud rate generator mode is similar to the auto-reload mode in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L which are preset by software The baud rates in Modes 1 and3 are determined by Timer 2s overflow rate according to the fol-lowing equation The Timer can be configured for either timer or counter operation In most applications it is con-figured for timer operation CP 0 The timer operation is different for Timer 2 when it is used as a baud rate generator Normally as a timer it increments every machine cycle at 112 the oscillator frequency As a baud rate generator however it increments every state time at 12 the oscillator frequency9 Programmable Clock OutA 50 duty cycle clock can be programmed to come out on P10 This pin besides being a regular IO pin has two alternate functions It can be programmed to input the external clock for TimerCounter 2 or to output a 50 duty cycle clock ranging from 61 Hz to 4 MHz for a 16-MHz operating frequency To configure the TimerCounter 2 as a clock generator bit C T2CON1 must be cleared and bit T2OE T2MOD1 must be set Bit TR2 T2CON2 starts and stops the timer The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers RCAP2H RCAP2L as shown in the following equationIn the clock-out mode Timer 2 roll-overs will not generate an interrupt This behavior is similar to when Timer 2 is used as a baud-rate generator It is possible to use Timer 2 as a baud-rate gen-erator and a clock generator simultaneously Note however that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L10 InterruptsThe AT89S52 has a total of six interrupt vectors two external interrupts and three timer interrupts Timers 0 1 and 2 and the serial port interrupt Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE IE also contains a global disable bit EA which disables all interrupts at once Note that bit position IE6 is unimplemented User software should not write a 1 to this bit position since it may be used in future AT89 products Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON Nei-ther of these flags is cleared by hardware when the service routine is vectored to In fact the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt and that bit will have to be cleared in software The Timer 0 and Timer 1 flags TF0 and TF1 are set at S5P2 of the cycle in which the timers overflow The values are then polled by the circuitry in the next cycle However the Timer 2 flag TF2 is set at S2P2 and is polled in thesame cycle in which the timer overflows11 Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output respectively of an inverting amplifier that can be configured for use as an on-chip oscillator Either a quartz crystal or ceramic resonator may be used To drive the device from an external clock source XTAL2 should be left unconnected while XTAL1 is driven There are no requirements on the duty cycle of the external clock signal since the input to the internal clock-ing circuitry is through a divide-by-two flip-flop but minimum and imum voltage high and low time specifications must be observed12 Idle ModeIn idle mode the CPU puts itself to sleep while all the on-chip peripherals remain active The mode is invoked by software The content of the on-chip RAM and all the special functions regis-ters remain unchanged during this mode The idle mode can be terminated by any enabled interrupt or by a hardware reset Note that when idle mode is terminated by a hardware reset the device normally resumes pro-gram execution from where it left off up to two machine cycles before the internal reset algorithm takes control On-chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset the instruction following the one that invokes idle mode should notwrite to a port pin or to external memory13 Power-down ModeIn the Power-down mode the oscillator is stopped and the instruction that invokes Power-down is the last instruction executed The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt Reset redefines the SFRs but does not change the on-chip RAM The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize AT89S52单片机主要性能与MCS-51单片机产品兼容8K字节在系统可编程Flash存储器1000次擦写周期全静态操作0Hz~33Hz三级加密程序存储器32个可编程IO口线三个16位定时器计数器八个中断源全双工UART串行通道低功耗空闲和掉电模式掉电后中断可唤醒看门狗定时器双数据指针掉电标识符功能特征描述AT89S52是一种低功耗高性能CMOS8位微控制器具有8K 在系统可编程Flash 存储器使用Atmel 公司高密度非易失性存储器技术制造与工业80C51 产品指令和引脚完全兼容片上Flash允许程序存储器在系统可编程亦适于常规编程器在单芯片上拥有灵巧的8 位CPU 和在系统可编程Flash使得AT89S52为众多嵌入式控制应用系统提供高灵活超有效的解决方案AT89S52具有以下标准功能 8k字节Flash256字节RAM32 位IO 口线看门狗定时器2 个数据指针三个16 位定时器计数器一个6向量2级中断结构全双工串行口片内晶振及时钟电路另外AT89S52 可降至0Hz 静态逻辑操作支持2种软件可选择节电模式空闲模式下CPU 停止工作允许RAM定时器计数器串口中断继续工作掉电保护方式下RAM内容被保存振荡器被冻结单片机一切工作停止直到下一个中断或硬件复位为止引脚功能VCC 电源GND 接地P0口 P0口是一个8位漏极开路的双向IO口作为输出口每位能驱动8个TTL逻辑电平对P0端口写1时引脚用作高阻抗输入当访问外部程序和数据存储器时P0口也被作为低8位地址数据复用在这种模式下P0具有内部上拉电阻在flash编程时P0口也用来接收指令字节在程序校验时输出指令字节程序校验时需要外部上拉电阻24 P1口P1 口是一个具有内部上拉电阻的8 位双向IO 口p1 输出缓冲器能驱动4 个TTL 逻辑电平对P1 端口写1时内部上拉电阻把端口拉高此时可以作为输入口使用作为输入使用时被外部拉低的引脚由于内部电阻的原因将输出电流IIL此外P10和P12分别作定时器计数器2的外部计数输入P10T2和时器计数器2的触发输入P11T2EX具体如下表所示在flash编程和校验时P1口接收低8位地址字节引脚号第二功能P10 T2定时器计数器T2的外部计数输入时钟输出P11 T2EX定时器计数器T2的捕捉重载触发信号和方向控制P15 MOSI在系统编程用P16 MISO在系统编程用P17 SCK在系统编程用25 P2口P2 口是一个具有内部上拉电阻的8 位双向IO 口P2 输出缓冲器能驱动4 个TTL 逻辑电平对P2 端口写1时内部上拉电阻把端口拉高此时可以作为输入口使用作为输入使用时被外部拉低的引脚由于内部电阻的原因将输出电流IIL在访问外部程序存储器或用16位地址读取外部数据存储器例如执行MOVX DPTR时P2 口送出高八位地址在这种应用中P2 口使用很强的内部上拉发送1在使用8位地址如MOVX RI访问外部数据存储器时P2口输出P2锁存器的内容在flash编程和校验时P2口也接收高8位地址字节和一些控制信号26 P3口P3 口是一个有内部上拉电阻的8 位双向IO 口p2 输出缓冲器能驱动4 个TTL 逻辑电平对P3 端口写1时内部上拉电阻把端口拉高此时可以作为输入口使用作为输入使用时被外部拉低的引脚由于内部电阻的原因将输出电流IILP3口亦作为AT89S52特殊功能第二功能使用如下表所示在flash编程和校验时P3口也接收一些控制信号引脚号第二功能P30 RXD串行输入P31 TXD串行输出P32 外部中断0 P33 外部中断1 P34 T0定时器0外部输入P35 T1定时器1外部输入P36 外部数据存储器写选通P37 外部数据存储器写选通27 RST复位输入晶振工作时RST脚持续2 个机器周期高电平将使单片机复位看门狗计时完成后RST 脚输出96 个晶振周期的高电平特殊寄存器AUXR 地址8EH 上的DISRTO位可以使此功能无效DISRTO默认状态下复位高电平有效28 ALE地址锁存控制信号ALE是访问外部程序存储器时锁存低8 位地址的输出脉冲在flash编程时此引脚也用作编程输入脉冲在一般情况下ALE 以晶振六分之一的固定频率输出脉冲可用来作为外部定时器或时钟使用然而特别强调在每次访问外部数据存储器时ALE脉冲将会跳过如果需要通过将地址为8EH 的SFR的第0位置 1ALE操作将无效这一位置 1ALE 仅在执行MOVX 或MOVC指令时有效否则ALE 将被微弱拉高这个ALE 使能标志位地址为8EH的SFR的第0位的设置对微控制器处于外部执行模式下无效29 外部程序存储器选通信号是外部程序存储器选通信号当AT89S52从外部程序存储器执行外部代码时在每个机器周期被激活两次而在访问外部数据存储器时将不被激活210 VPP访问外部程序存储器控制信号为使能从0000H 到FFFFH的外部程序存储器读取指令必须接GND为了执行内部程序指令应该接VCC在flash编程期间也接收12伏VPP电压211 XTAL1振荡器反相放大器和内部时钟发生电路的输入端212 XTAL2振荡器反相放大器的输出端3 存储器结构MCS-51器件有单独的程序存储器和数据存储器外部程序存储器和数据存储器都可以64K寻址31 程序存储器如果引脚接地程序读取只从外部存储器开始对于89S52如果接VCC程序读写先从内部存储器地址为0000H~1FFFH开始接着从外部寻址寻址地址为2000HFFFFH32 数据存储器 AT89S52 有256 字节片内数据存储器高128 字节与特殊功能寄存器重叠也就是说高128字节与特殊功能寄存器有相同的地址而物理上是分开的当一条指令访问高于7FH 的地址时寻址方式决定CPU 访问高128 字节RAM 还是特殊功能寄存器空间直接寻址方式访问特殊功能寄存器SFR例如下面的直接寻址指令访问0A0HP2口存储单元MOV 0A0H data使用间接寻址方式访问高128 字节RAM例如下面的间接寻址方式中R0 内容为0A0H访问的是地址0A0H的寄存器而不是P2口它的地址也是0A0H MOV R0 data堆栈操作也是简介寻址方式因此高128字节数据RAM也可用于堆栈空间4 看门狗定时器WDT是一种需要软件控制的复位方式WDT 由13位计数器和特殊功能寄存器中的看门狗定时器复位存储器WDTRST构成WDT 在默认情况下无法工作为了激活WDT户用必须往WDTRST 寄存器地址0A6H中依次写入01EH 和0E1H当WDT激活后晶振工作WDT在每个机器周期都会增加WDT计时周期依赖于外部时钟频率除了复位硬件复位或WDT溢出复位没有办法停止WDT工作当WDT溢出它将驱动RSR引脚一个高个电平输出41 WDT的使用为了激活WDT用户必须向WDTRST寄存器地址为0A6H的SFR依次写入0E1H 和0E1H当WDT激活后用户必须向WDTRST写入01EH和0E1H喂狗来避免WDT溢出当计数达到8191 1FFFH 时13 位计数器将会溢出这将会复位器件晶振正常工作WDT激活后每一个机器周期WDT 都会增加为了复位WDT用户必须向WDTRST 写入01EH 和0E1HWDTRST 是只读寄存器WDT 计数器不能读或写当WDT 计数器溢出时将给RST 引脚产生一个复位脉冲输出这个复位脉冲持续96个晶振周期TOSC其中TOSC 1FOSC为了很好地使用WDT应该在一定时间内周期性写入那部分代码以避免WDT复位42 掉电和空闲方式下的WDT在掉电模式下晶振停止工作这意味这WDT也停止了工作在这种方式下用户不必喂狗有两种方式可以离开掉电模式硬件复位或通过一个激活的外部中断通过硬件复位退出掉电模式后用户就应该给WDT 喂狗就如同通常AT89S52 复位一样通过中断退出掉电模式的情形有很大的不同中断应持续拉低很长一段时间使得晶振稳定当中断拉高后执行中断服务程序为了防止WDT在中断保持低电平的时候复位器件WDT 直到中断拉低后才开始工作这就意味着WDT 应该在中断服务程序中复位为了确保在离开掉电模式最初的几个状态WDT不被溢出最好在进入掉电模式前就复WDT在进入待机模式前特殊寄存器AUXR的WDIDLE位用来决定WDT是否继续计数默认状态下在待机模式下WDIDLE=0WDT继续计数为了防止WDT 在待机模式下复位AT89S52用户应该建立一个定时器定时离开待机模式再重新进入待机模式5 UART在AT89S52 中UART 的操作与AT89C51 和AT89C52 一样6 定时器0 和定时器1在AT89S52 中定时器0 和定时器1 的操作与AT89C51 和AT89C52 一样7 定时器2定时器2是一个16位定时计数器它既可以做定时器又可以做事件计数器其工作方式由特殊寄存器T2CON中的CT2位选择如表2所示定时器2有三种工作模式捕捉方式自动重载向下或向上计数和波特率发生器如表 3 所示工作模式由T2CON中的相关位选择定时器2 有2 个8位寄存器TH2和TL2在定时工作方式中每个机器周期TL2 寄存器都会加1由于一个机器周期由12 个晶振周期构成因此计数频率就是晶振频率的112表3 定时器2工作模式RCLK TCLK CP TR2 MODE 0 0 1 16位自动重载0 1 1 16位捕捉 1 X 1 波特率发生器X X 0 不用在计数工作方式下寄存器在相关外部输入角T2 发生1 至0 的下降沿时增加1在这种方式下每个机器周期的S5P2期间采样外部输入一个机器周期采样到高电平而下一个周期采样到低电平计数器将加1在检测到跳变的这个周期的S3P1 期间新的计数值出现在寄存器中因为识别1-0的跳变需要2个机器周期24个晶振周期所以最大的计数频率不高于晶振频率的124为了确保给定的电平在改变前采样到一次电平应该至少在一个完整的机器周期内保持不变71 捕捉方式在捕捉模式下通过T2CON中的EXEN2来选择两种方式如果EXEN2 0定时器2时一个16位定时计数器溢出时对T2CON 的TF2标志置位TF2引起中断如果EXEN2 1定时器2做相同的操作除上述功能外外部输入T2EX引脚P111至0的下跳变也会使得TH2和TL2中的值分别捕捉到RCAP2H和RCAP2L中除此之外T2EX 的跳变会引起T2CON 中的EXF2 置位像TF2 一样T2EX 也会引起中断72 自动重载当定时器 2 工作于16 位自动重载模式可对其编程实现向上计数或向下计数这一功能可以通过特殊寄存器T2MOD见表4中的DCEN向下计数允许位来实现通过复位DCEN 被置为0因此定时器2 默认为向上计数DCEN 设置后定时器2就可以取决于T2EX向上向下计数DCEN 0 时定时器2 自动计数通过T2CON 中的EXEN2 位可以选择两种方式如果EXEN2 0定时器2计数计到0FFFFH后置位TF2溢出标志计数溢出也使得定时器寄存器重新从RCAP2H 和RCAP2L 中加载16 位值定时器工作于捕捉模式RCAP2H和RCAP2L的值可以由软件预设如果EXEN2 1计数溢出或在外部T2EXP11引脚上的1到0的下跳变都会触发16位重载这个跳变也置位EXF2中断标志位置位DCEN允许定时器2向上或向下计数在这种模式下T2EX引脚控制着计数的方向T2EX上的一个逻辑1使得定时器2向上计数定时器计到0FFFFH溢出并置位TF2定时器的溢出也使得RCAP2H和RCAP2L中的16位值分别加载到定时器存储器TH2和TL2中T2EX 上的一个逻辑0 使得定时器2 向下计数当TH2 和TL2 分别等于RCAP2H 和RCAP2L中的值的时候计数器下溢计数器下溢置位TF2并将0FFFFH加载到定时器存储器中定时器2上溢或下溢外部中断标志位EXF2 被锁死在这种工作模式下EXF2不能触发中断8 波特率发生器通过设置T2CON中的TCLK或RCLK可选择定时器2 作为波特率发生器如果定时器2作为发送或接收波特率发生器定时器1可用作它用发送和接收的波特率可以不同如图8 所示设置RCLK 和或TCLK 可以使定时器2 工作于波特率产生模式波特率产生工作模式与自动重载模式相似因此TH2 的翻转使得定时器2 寄存器重载被软件预置16位值的RCAP2H和RCAP2L中的值模式1和模式3的波特率由定时器2溢出速率决定定时器可设置成定时器也可为计数器在多数应用情况下一般配置成定时方式CP 0定时器 2 用于定时器操作与波特率发生器有所不同它在每一机器周期112晶振周期都会增加然而作为波特率发生器它在每一机器状态12晶振周期都会增加9 可编程时钟输出可以通过编程在P10 引脚输出一个占空比为50的时钟信号这个引脚除了常规的IO 角外还有两种可选择功能它可以通过编程作为定时器计数器 2 的外部时钟输入或占空比为50的时钟输出当工作频率为16MHZ时时钟输出频率范围为61HZ到4HZ为了把定时器2配置成时钟发生器位CT2CON1必须清0位T2OET2MOD1必须置1位TR2T2CON2启动停止定时器时钟输出频率取决于晶振频率和定时器2捕捉寄存器RCAP2HRCAP2L的重载值如公式所示在时钟输出模式下定时器2不会产生中断这和定时器2用作波特率发生器一样定时器2也可以同时用作波特率发生器和时钟产生不过波特率和输出时钟频率相互并不独立它们都依赖于RCAP2H和RCAP2L10 中断AT89S52 有6个中断源两个外部中断和三个定时中断定时器012和一个串行中断每个中断源都可以通过置位或清除特殊寄存器IE 中的相关中断允许控。

单片机外文翻译

单片机外文翻译

单片机外文翻译河北农业大学毕业设计(论文)外文资料翻译院(系): 信息科学与技术学院专业: 电子信息科学与技术姓名: 李洋学号: 2007234020316外文出处: from internetStructure and function of the MCS-51 series附件: 1.外文资料翻译译文,2.外文原文。

完成日期: 2011 年 3月1 日1. 外文资料翻译译文:51系列单片机的结构和功能51系列单片机是英特尔公司生产的具有一定结构和功能的单片机产品。

这家公司在1976年引入8位MCS - 48系列单片机后,于1980年又推出了8位高档的MCS - 51系列,8031,8751,80C51BH,80C31BH等,单片机。

它包含很多种这类型的单片机,如8051它们的基本组成,基本性能和指令系统都是一样的。

一般情况习惯用8051来代表51系列单片机。

一个单片机的系统是由以下几部分组成:(1)一个8位CPU微处理器。

(2)静态随机存取存储器,能够储存程序运行过程中产生的数据。

(3)程序存储器ROM / EPROM中(4KB/8KB),用来保存程序和一些初始数据。

但是在一些单片机中不使用ROM / EPROM中,如8031,8032,80c系列等。

(4)4个8排的I / O并行接口P0~P3,每个口可以用作输入,也可以用作输出。

(5)2个定时器/计数器,每个定时器/计数器可设置计数用来计数外部事件,可以设置成常用的定时方式,并可以根据计算或结果控制单片机的运行。

(6)五个中断源控制系统。

(7)1个双向串行I / O口的UART(通用异步接收器/发送器UART),用于实现单片机的串行通信。

(8)振荡器和时钟产生电路,需要外部电源的石英晶体微调电路,允许接在12v的振荡频率上。

上述部分通过内部数据总线连接。

其中,CPU是单片机的核心,它是单片机的控制和指挥中心,ALU算数逻辑运算单元可进行算术运算和逻辑运算,由1个 8暂时存储器,和2个 8位的累加器组成。

单片机【经典外文翻译】--单片机基础(译文+英文)—-毕业论文设计

单片机【经典外文翻译】--单片机基础(译文+英文)—-毕业论文设计

Fundamentals of Single-chip MicrocomputerTh e si ng le-ch i p mi cr oc om pu ter is t he c ul mi nat i on o f bo th t h e d ev el op me nt o f th e d ig it al com p ut er an d t he int e gr at ed ci rc ui ta r gu ab ly th e t ow m os t s i gn if ic ant i nv en ti on s o f t h e 20t h c en tury[1].Th es e to w typ e s of a rc hi te ctu r e ar e fo un d i n s in gl e-ch ip m i cr oc om pu te r. So m e em pl oy t he sp l it p ro gr am/d ata me mo ry o f th e H a rv ar d ar ch it ect u re, sh ow n in Fi g.3-5A-1, o th ers fo ll ow t hep h il os op hy, wi del y a da pt ed f or ge n er al-p ur po se co m pu te rs a ndm i cr op ro ce ss or s, of ma ki ng no lo gi c al di st in ct io n be tw ee n p ro gram a n d da ta m em or y a s i n th e Pr in cet o n ar ch it ec tu re,sh ow n inF i g.3-5A-2.In g en er al te r ms a s in gl e-chi p m ic ro co mp ut er i sc h ar ac te ri zed b y the i nc or po ra tio n of al l t he uni t s o f a co mp ut er i n to a s in gl e dev i ce, as s ho w n in Fi g3-5A-3.Fig.3-5A-1 A Harvard typeFig.3-5A-2. A conventional Princeton computerFig3-5A-3. Principal features of a microcomputerRead only memory (ROM).R OM i s u su al ly f or th e p er ma ne nt,n o n-vo la ti le s tor a ge o f an a pp lic a ti on s pr og ra m .M an ym i cr oc om pu te rs an d mi cr oc on tr ol le r s a re in t en de d fo r h ig h-v olume a p pl ic at io ns a nd h en ce t he e co nom i ca l ma nu fa ct ure of t he d ev ic es r e qu ir es t ha t the co nt en ts o f the pr og ra m me mo ry b e co mm it te dp e rm an en tl y d ur in g th e m an uf ac tu re o f c hi ps . Cl ear l y, th is im pl iesa ri g or ou s a pp roa c h t o R OM co de d e ve lo pm en t s in ce c ha ng es ca nnotb e m ad e af te r man u f a ct ur e .T hi s d e ve lo pm en t pr oce s s ma y in vo lv e e m ul at io n us in g a s op hi st ic at ed deve lo pm en t sy st em w i th a ha rd wa re e m ul at io n ca pa bil i ty a s we ll a s th e u se of po we rf ul so ft wa re t oo ls.So me m an uf act u re rs p ro vi de ad d it io na l RO M opt i on s byi n cl ud in g i n th ei r r a ng e de vi ce s wi th (or i nt en de d fo r us e with) u s er pr og ra mm ab le m em or y. Th e s im p le st of th es e i s us ua ll y d evice w h ic h ca n op er ate in a m ic ro pr oce s so r mo de b y usi n g so me o f th e i n pu t/ou tp ut li ne s as a n ad dr es s an d da ta b us f or acc e ss in g e xt er na l m e mo ry. T hi s t ype o f d ev ic e c an b e ha ve fu nc ti on al l y a s t he si ng le c h ip mi cr oc om pu te r fr om wh ic h i t i s de ri ve d a lb eit w it h r es tr ic ted I/O an d a mo di fie d e xt er na l ci rcu i t. T he u se o f t h es e RO Ml es sd e vi ce s is c om mo n e ve n in p ro du ct io n c ir cu it s wh er e t he v ol um e does n o t j u st if y th e d e ve lo pm en t co sts of c us to m on-ch i p RO M[2];t he re c a n st il l b e a si g ni fi ca nt s a vi ng in I/O a nd ot he r c hi ps co mp ared t o a c on ve nt io nal mi cr op ro ce ss or b as ed c ir cu it. M o re e xa ctr e pl ac em en t fo r RO M d ev ic es c an b e o bt ai ne d in t he f o rm o f va ri antsw i th 'pi gg y-ba ck'EP RO M(Er as ab le p ro gr am ma bl e ROM)s oc ke ts o rd e vi ce s w it h EP ROM i ns te ad o f R OM 。

单片机设计外文翻译---- 单片机工作原理

单片机设计外文翻译---- 单片机工作原理

单片机设计外文翻译---- 单片机工作原理单片机设计外文翻译单片机工作原理单片机,也被称为微控制器(Microcontroller Unit,MCU),是一种集成在单个芯片上的微型计算机系统。

它具有体积小、功耗低、性能强等优点,被广泛应用于各种电子设备中,从家用电器到工业自动化,从汽车电子到医疗设备,几乎无处不在。

单片机的工作原理可以从以下几个方面来理解。

首先,单片机包含了一个中央处理器(Central Processing Unit,CPU),这是其核心部分。

CPU 负责执行指令和进行数据处理。

与常见的个人电脑中的 CPU 相比,单片机的 CPU 通常较为简单,但在特定的应用场景中能够高效地完成任务。

其次,单片机具有存储器。

存储器包括程序存储器和数据存储器。

程序存储器用于存储预先编写好的控制程序,这些程序决定了单片机的工作方式和功能。

数据存储器则用于临时存储在运行过程中产生和需要处理的数据。

单片机还配备了输入/输出(Input/Output,I/O)接口。

这些接口使得单片机能够与外部设备进行通信和交互。

例如,通过 I/O 接口,单片机可以接收来自传感器的信号,如温度传感器、压力传感器等,也可以控制外部执行器,如电机、灯光等。

时钟电路也是单片机的重要组成部分。

时钟就像是单片机的“心跳”,为其提供了工作的节奏和时序。

通过时钟信号,单片机能够精确地控制指令的执行和数据的处理,确保各个操作按照预定的顺序和时间间隔进行。

单片机的工作过程大致如下:当电源接通后,单片机首先进行初始化操作,包括设置一些初始的寄存器值、初始化 I/O 端口等。

然后,它从程序存储器中读取第一条指令,并将其送入 CPU 进行执行。

在执行指令的过程中,可能会涉及到对数据存储器的读写操作,以及通过 I/O 接口与外部设备进行数据交换。

例如,在一个温度控制系统中,单片机通过温度传感器的 I/O 接口读取当前的温度值。

然后,根据预先编写的程序,将读取到的温度值与设定的温度范围进行比较。

(完整word版)基于单片机外文翻译

(完整word版)基于单片机外文翻译

河南理工大学毕业设计(论文)说明书Presented in this paper is a design of pulse measuring instrument based on MCU, as the circuit module plays an important role in the system, such as heart rate acquisition circuit, display circuit and STC89C52 microcontroller through the serial portto realize the connection. This design with STC89C52 microcontroller as the central control unit, through ST188 as infrared photoelectric sensor to collect the pulse signal, after the lm358 for op amp; again through before and after filtering, magnifying, shaping, and get stable signal; functions to achieve the rapid detection of heart. Youcan also through the button to set the pulse value scope; buzzer driver module In the range beyond the scope of the alarm prompt, the measurement results in the liquid crystal display.Experimental results show that the test results of the design and practical requirements are basically the same, STC89C52 MCU strong anti-interference ability and LCD1602 display control the advantages of more convenient so that thesefeatures can be successfully completed. The production cost less than 100 yuan,with low price, easy manipulation, low power consumption, high reliability, very applicable to families and individuals.Heart rate) in professional terms is used to describe the human heart beat cycle. Pulse of modern Chinese will be interpreted as "heart beating frequency value; so the heart rate can also said in a unit of time, heart rhythm speed.Everyone's heart rate signals mostly contains rich physiological and psychological information. This is due to the health of internal organs of the body can reflect in the pulse information. This discovery has gradually attracted the attention of many clinicians. In our country, pulse diagnosis has been regarded as the essence of Chinese medicine; so far the clinical practice has about 2600 years. However due to the use of fingers often there will be some sweat glands refers to pulse diagnosis in the presence of errors can not be ignored; and leads to inaccurate measurement. Then perhaps you would say and the ear vein measurement, instead of the previous is often used. Although by measuring ear ripple come to pulse signal relatively comparison Clean, but because the ear pulse signal is weak, especially when the seasonal changes, the measurement signal is vulnerable to the influence of environmental temperature,resulting in inaccurate measurement values.With the development and progress of world science and technology and economy, cherish life, health care has become a common pursuit of mankind throughout the world. According to the Health Bureau statistics, every year because of cardiovascular and cerebrovascular diseasesdeath of the highest number of human deaths first, not only the high cost of health care, back to the family, the government and the society caused great burden. In recent years, due to the accelerated pace of life, unreasonable eating habits and many junk food impact and other reasons, the incidence of cardiovascular and cerebrovascular is showing a trend of rising year by year. How to scientifically and harmless reduce cardiovascular disease morbidity and mortality, effectively reduce cardiovascular and cerebrovascular diseasesand social Family burden, has become a very serious problem faced by human beings all over the world.World first lever type pulse scanner is Vierordt was founded in 1854. It is a lever and a pressure drum scanner uses the notation to record the pulse waveform, also is the human for the first time through non invasion of recording the human body pulse, then caused a great sensation. However the starting point for the development of domestic relatively is relatively low, in the early 50s of the 20th century Zhu Yancaiwill pulse instrument reference to objective study on the pulse diagnosis in traditional Chinese medicine. In recent years, non invasive vascular function detection gradually attracted the eyes of the medical professionals. Since about 1980, no traumavascular function detection by using the small range, its principle is roughly Based on hemodynamic rheology theory and elastic chamber theory. Characterized in it by the module temperature, blood pressure cuff module, blood oxygen module of multi physiological signal acquisition module combination by of brachial artery blocking opening in the process of finger end temperature signal, oxygen saturation and pulse wave signal changes of the parameters of the, again according to the clinical trial data acquisition and through the method of signal processing and statistical analysis, establishment of vascular function quantitative evaluation formula and blood vessel function evaluation. It has noninvasive, simple operation, accurate, good repeatability and convenient for clinical application and automatically generates diagnosis ofcardiovascular function, health status analysis and gives related medical solution Release.Now pulse testing is no longer confined to the traditional manual testing or stethoscope test, only use electronic devices can be obtained more accurate data. In today's society, most of electronic measuring instruments has been directed towards the digitization, automation development direction. Pulse measuring instrument is not only good performance, simple structure, and has good value of application and popularization. In general, the pulse measurement instrument development is mainly the following trends: first, in the absence of human can automatically analyze the measurement of pulse value; the pulse of the traditional instrument need after experienced doctor pulse signal of the first initial analysis and then make a comprehensive analysis to final To confirm the results, this method of total said tonot only waste a lot of manpower and by factitious error is relatively large. The second: the wide application of digital technology and other advanced technology; pulse measuring instrument integration to want to achieve a higher degree, and are more convenient to carry must rely on the rapid development of digital science and technology; at the same time digital signal processing application will enable interference becomes smaller measurement result ismore accurate. The third: multi function of more and more obvious. The fourth: cheap, easy to carry and application and popularization value better, to the general public convenience.Has always been in the hospital for basis for clinical diagnosis and treatment of most source extracted from the human pulse wave in physiological and pathological information. In China, feeling the pulse is old doctor of traditional Chinese medicineis the most commonly used to diagnose disease, has been in use ever since. The pulse signal emitted by human body contains the velocity of heart rate, full waveform, period and amplitude, a full range of integrated information, in a large extent can reflect human body each part information (for example blood viscosity, blood velocity). Although these biological signals exist in the human body, the signal intensity relative to said is relatively weak; if in a noisy environment effect is more obvious.This graduation design principle is the use of single-chip microprocessorSTC89C52 as the center processor; pulse signal is collected by the sensor, through the microcontroller chip in the interior of the system timer to set the time; finally get the heart rate beat numerical by STC89C52 microcontroller to signal accumulation can be. Normal heartbeat is about 60-100 per minute times, circuit diagram of key module can through the button to set the scope of people's heart rate, above or below the setting range of possible heart there will be risks, buzzer driver module will drive buzzer alarm; the final measurement results Will be displayed on the LCD. The design can by viewing the IR indicates whether the lights and flashing, if sustained, stable flashing that test results are correct and error is small. With the assumption that the display results back and forth rock and numerical difference between the larger, there may exist error. Through the above steps, can roughly determine the body's own health, and is particularly suitable to be used to the individual or family, is also sometimes used in nursing homes and healthcare center.The design of the selection of SCM is STC89C52。

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毕设外文翻译--单片机基础毕业设计(论文)外文资料翻译系别: 电气系专业: 电气工程及其自动化班级:姓名:学号:外文出处: Atomation Professional English Course(用外文写) Pressed By Machinery Industry Press附件:1、外文原文;2、外文资料翻译译文。

指导教师评语:签字:年月日注:请将该封面与附件装订成册。

1、外文原文(复印件)A: Fundamentals of Single-chip MicrocomputerThe single-chip microcomputer is the culmination of both the development of the digital computer and the integrated circuit arguably the tow most significant inventions of the 20th century [1].These tow types of architecture are found in single-chip microcomputer. Some employ the split program/data memory of the Harvard architecture, shown in Fig.3-5A-1, others follow the philosophy, widely adapted for general-purpose computers and microprocessors, of making nological distinction between program and data memory as in the Princeton architecture, shown in Fig.3-5A-2.In general terms a single-chip microcomputer is characterized by the incorporation of all the units of a computer into a single device, as shown in Fig3-5A-3.ProgramInput& memoryOutputCPU unitDatamemoryFig.3-5A-1 A Harvard typeInput&Output CPU memoryunitFig.3-5A-2. A conventional Princeton computerExternal Timer/ System Timing Counter clock componentsSerial I/OReset ROMPrarallelI/OInterrupts RAMCPUPowerFig3-5A-3. Principal features of a microcomputerRead only memory (ROM).ROM is usually for the permanent,non-volatile storage of an applications program .Many microcomputers and microcontrollers are intended for high-volume applications and hence the economical manufacture of the devices requires that the contents of the program memory be committed permanently during the manufacture of chips . Clearly, this implies a rigorous approach to ROM code development since changes cannot be made after manufacture .This development process may involve emulation using a sophisticated development system with a hardware emulation capability as well as the use of powerful software tools.Some manufacturers provide additional ROM options by including in their range devices with (or intended for use with) user programmable memory. The simplest of these is usually device which can operate in a microprocessor mode by using some of the input/output lines as an address and data bus for accessing external memory. This type of device can behave functionally as the single chip microcomputer from which itis derived albeit with restricted I/O and a modified external circuit. The use of these ROMless devices is common even in production circuits where the volume doesnot justify the development costs of custom on-chip ROM[2];there can still be a significant saving in I/O and other chips compared to a conventional microprocessor based circuit. More exact replacement for ROM devices can be obtained in the form of variants with 'piggy-back'EPROM(Erasable programmable ROM )sockets or devices with EPROM insteadof ROM 。

These devices are naturally more expensive than equivalent ROM device, but do provide complete circuit equivalents. EPROM based devices are also extremely attractive for low-volume applications where they provide the advantages of a single-chip device, in terms of on-chip I/O, etc. ,with the convenience of flexible user programmability.Random access memory (RAM).RAM is for the storage of workingvariables and data used during program execution. The size of this memory varies with device type but it has the same characteristic width (4,8,16 bits etc.) as the processor ,Special function registers, such as stack pointer or timer register are often logically incorporated intothe RAM area. It is also common in Harard type microcomputers to treat the RAM area as a collection of register; it is unnecessary to make distinction between RAM and processor register as is done in the case of a microprocessor system since RAM and registers are not usuallyphysically separated in a microcomputer .Central processing unit (CPU).The CPU is much like that ofany microprocessor. Many applications of microcomputers and microcontrollers involve the handling of binary-coded decimal (BCD) data (for numerical displays, for example) ,hence it is common to find that the CPU is well adapted to handling this type of data .It is also common to find good facilities for testing, setting and resetting individualbits of memory or I/O since many controller applications involve the turning on and off of single output lines or the reading the single line.These lines are readily interfaced to two-state devices such as switches, thermostats, solid-state relays, valves, motor, etc.Parallel input/output. Parallel input and output schemes vary somewhat in different microcomputer; in most a mechanism is provided to at least allow some flexibility of choosing which pins are outputs and which are inputs. This may apply to all or some of the ports. Some I/O lines are suitable for direct interfacing to, for example, fluorescent displays, or can provide sufficient current to make interfacing other components straightforward. Some devices allow an I/O port to be configured as a system bus to allowoff-chip memory and I/O expansion. This facility is potentiallyuseful as a product range develops, since successive enhancements may become too big for on-chip memory and it is undesirable not to build on the existing software base.Serial input/output .Serial communication with terminaldevices is common means of providing a link using a small number of lines. This sort of communication can also be exploited for interfacing special function chips or linking several microcomputers together .Both the common asynchronous synchronous communication schemes require protocols that provide framing (start and stop) information .This can be implemented as a hardware facility or U(S)ART(Universal(synchronous) asynchronous receiver/transmitter) relieving the processor (and the applications programmer) of this low-level, time-consuming, detail. t is merely necessary to selected a baud-rate and possibly other options(number of stop bits, parity, etc.) and load (or read from) the serial transmitter (or receiver) buffer. Serialization of the data in the appropriate format is then handled by the hardware circuit.Timing/counter facilities. Many application of single-chipmicrocomputers require accurate evaluation of elapsed realtime .This can be determined by careful assessment of the execution time of each branch in a program but this rapidly becomes inefficient for all but simplest programs .The preferred approach is to use timer circuit that can independently count precise time increments and generate an interrupt after a preset time has elapsed .This type of timer is usually arranged to be reloadable with the required count .The timer then decrements this value producing an interrupt or setting a flag when the counter reaches zero. Better timers then have the ability to automatically reload the initial count value. This relieves the programmer of the responsibility of reloading the counter and assessing elapsed time before the timer restarted ,which otherwise wound be necessary if continuous precisely timed interrupts were required (as in a clock ,for example).Sometimes associated with timer is an event counter. With this facility there is usually a special input pin ,that can drive the counter directly.Timing components. The clock circuitry of most microcomputers requires only simple timing components. If maximum performance is required,a crystal must be used to ensure the maximum clock frequency is approached but not exceeded. Many clock circuits also work with aresistor and capacitor as low-cost timing components or can be driven from an external source. This latter arrangementis useful is external synchronization of the microcomputer is required.WORDS AND TERMSculmination n.顶点spilt adj.分离的volatile n. 易变的commit v.保证albeit conj.虽然custom adj.定制的variant adj.不同的piggy-back adj.背负式的socket n. 插座B:PLC[1]PLCs (programmable logical controller) face ever more complex challenges these days . Where once they quietly replaced relays and gave an occasional report to a corporate mainframe, they are now grouped into cells, given new job and new languages, and are forced to compete against a growing array of control products. For this year's annual PLC technology update ,we queried PLC makers on these topics and more .Programming languagesHigher level PLC programming languages have been around for sometime ,but lately their popularity has mushrooming. "As Raymond Leveille,vice president & general manager, Siemens Energy &Automation .inc; Programmable controls are being used for more and more sophisticated operations, languages other than ladder logic become more practical, efficient, and powerful. For example, it's very difficult to write a trigonometric function using ladder logic ."Languages gaining acceptance include Boolean, control system flowcharting, and such function chart languages as Graphcet and its variation .And there's increasing interest in languages like C and BASIC.PLCs in process controlThus far, PLCs have not been used extensively for continuous process control .Will this continue? "The feeling that I've gotten," says Ken Jannotta, manger, product planning, series One and Series Sixproduct ,at GE Fanuc North America ,'is that PLCs will be used in the process industry but not necessarily for process control."Several vendors -obviously betting that the opposite willhappen -have introduced PLCs optimized for processapplication .Rich Ryan, manger, commercial marketing, Allen-bradley Programmable Controls Div., cites PLCs's increasing use such industries as food ,chemicals ,and petroleum. Ryan feels there are two types of applications in which they're appropriate. "one," he says," is where the size of the process control system that's being automated doesn'tjustify DCS[distributed control system].With the starting price tags of chose products being relatively high, a programmable controller makes sense for small, low loop count application .The second is where youhave to integrate the loop closely with the sequential logical .Batch controllers are prime example ,where the sequence and maintaining the process variable are intertwined so closely that the benefits of having a programmable controller to do the sequential logical outweighs some of the disadvantages of not having a distributed control system."Bill Barkovitz, president of Triconex, predicts that "all future controllers that come out in the process control system business will embrace a lot of more PLC technology and a lot more PLC functionality than they ever did before ."Communications and MAPCommunications are vital to an individual automation cell and to be automated factory as a whole. We've heard a lot about MAP in the last few years ,and a lot of companies have jumped on the bandwagon.[2]Many, however, were disappointed when a fully-defined and completed MAP specification didn't appear immediately .Says Larry Komarek: "Right now, MAP is still a moving target for the manufacturers, a specification that is not final .Presently, for example. people are introducing products to meet the MAP2.1standard .Yet2.1-based products will be obsolete when the new standard for MAP3.0 is introduced."Because of this, many PLC vendors are holding off on full MAP implementations. Omron, for example, has an ongoingMAP-compatibility program;[3]but Frank Newburn, vice president of Omron's Industrial Division ,reports that because of the lack of a firm definition ,Omron's PLCs don't yet talk to MAP.Since it's unlikely that an individual PLC would talk to broad MAP anyway, makers are concentrating on proprietary networks. According to Sal Provanzano, users fear that if they do get on board and vendors withdraw from MAP, they'll be the ones left holding a communications structure that's not supported.Universal I/OWhile there are concerns about the lack of compatible communications between PLCs from different vendors, the connectionat the other end-the I/O-is even more fragmented .With rare exceptions, I/O is still proprietary .Yet there are those who feel that I/O will eventually become more universal .GE Fanuc is hoping to do that with its Genius smart I/O line. The independent I/O makers are pullingin the same direction.Many say that I/O is such a high-value item that PLC makers will always want to keep it proprietary .As Ken Jannotta, says: "The I/O is going to be a disproportionate amount of the hardware sale. Certainly each PLC vendor is going to try to protect that. "For that reason, he says, PLC makers won't begin selling universal I/O system from other vendor. "if we start selling that kind of product, "says jannotta, "what do we manufacture?"With more intelligent I/O appearing, Sal Provanzano feels this will lead to more differentiation among I/O from different makers. "Where the I/O becomes extremely intelligent and becomes part of the system, "he says, "it really is hard to define which is the I/O and which is CPU. Itreally CPU, if you will, is equally integrated into the system as theI/O."Connecting PLC I/O to PCsWhile different PLCs probably will continue to use proprietary I/O, several vendors make it possible to connect5 their I/O to IBM PC-compatible equipment. Alle-bradeley, Could, and Cincinnati Milacron already have, and rumor has it that GE is planning something along these same lines .[4]Bill Ketelhut, manage of product planning at GE Fanuc North America ,sees this sort of thing as alternative to universalI/O."I think the trend ,instead of toward universal I/O, will bemultiple host interface ," he says .Jodie Glore ,director of marking, Square D Automation Products, Views it as another indication that PLCs are, and have been for some time, industrial computers.PLCs VS PCsIf the IBM 7552, the Action Instruments BC22,and other computers are appearing on the factory floor, won't this mean new competition for PLCs? Rich Ryan: "There are some control functions that are better jobs for computers. Programmable controllers have been forced to fit into those applications. "Yet, the majority of vendors we surveyed don't like the "PC invasion" will pose a problem for them .Most said that PLCs and PCs are enough apart in architecture that they will usually do the control. They don't feel that PCs will take jobs from PLCs just because PLC I/O modules can now be connected to PCs; they believe this simply means that PLCs and PCs will be able to share the same data."There are inherent architectural differences between a general purpose computer," says Rich Ryan, "and a programmablecontroller .There are hardware constructs built into almost every manufacture's programmable controller today that customize the hardware to run ladder logic and to solve machine code. "One fundamental difference he cites is called state of the machine .Ryan: "When you shut the machine off, or interrupt the cycle, or you jump to another spot in the cycle, programmable controllers inherently remember the state of the machine: what the timers were, what the counters were ,what the states of all the latches were .Computers don't inherently do that."WORDS AND TERMSbet v.确信optimized n.优化程序corporate adj.共同的mushroom v.迅速发展trigonometric function 三角函数vendor n.厂商tag n.标签smart adj.智能型的compatible adj.兼容的2、外文资料翻译译文单片机基础单片机是电脑和集成电路发展的巅峰,有据可查的是他们也是20世纪最有意义的两大发明。

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