Allegro原理图设计

Allegro原理图设计原版教程

Allegro® Design Entry HDL User GuideProduct Version 16.6 October 20122Getting StartedThis chapter contains the following information:Starting Design Entry HDLDesign Entry HDL User InterfaceDesign Entry HDL TasksDesign Entry HDL BasicsStarting Design Entry HDLAfter you open the desired design project in Project Manager, the flow area of Project Manager displays the Cadence Board Design flow. In the Board Design flow, click the Design Entry icon.Note: You must be on the Common Desktop Environment (CDE) on a Sun workstation to run the Design Entry HDL set of tools.To launch Design Entry HDL, do one of the following:1. In Project Manager, open the .cpm file of a project and then click the Design Entry icon.--or--2. Choose Start - Programs - Cadence - Release 16.6 - Design Entry HDL.--or--3. At the command prompt, type concepthdl and press ENTER.Design Entry HDL User InterfaceWhen you launch Design Entry HDL using any of the three methods listed above, the Design Entry HDL user interface appears (as shown in the following figure).The Design Entry HDL interface consists of the following elements: Design windowMenu barToolbarsStatus barGlobal Navigation windowConsole command windowContext-sensitive menusMenu BarThe Design Entry HDL menu bar includes the following menus:FileFor operations such as opening, saving, and plotting a drawing.EditFor operations such as Undo, Copy, Paste, Delete, Spin, and Color.ViewFor operations such as Zoom, Pan, and Grid.ComponentFor operations that can be done on a part such as adding, replacing, and modifying a part.WireFor operations such as connecting parts and naming signals.TextFor operations such as adding properties and notes.BlockFor operations such as adding blocks.GroupFor operations such as creating groups and performing editing functions on groups.DisplayFor operations such as highlighting and de-highlighting components.AMS SimulatorFor performing analog, digital and mixed-signal simulation using the AMS Simulator. This menu is visible only if you have installed AMS Simulator.RF-PCBInvokes the RF-PCB IFF Import UI which enables you to import radio frequency design into your schematic.ToolsFor operations such as setting up defaults, customizing, updating the schematic with layout changes, updating the layout with schematic changes, finding nets and instances in your design, global navigation, checking your design, and running scripts.WindowFor operations such as opening a new window, cascading and tiling it.HelpInvokes the Design Entry HDL help page and web resources such as Cadence OnlineSupport and Education Services.In the Windows Mode, menu bar and menu options are different fromthe normal more. See Reorganized Menus for more information.ToolbarsDesign Entry HDL has the following toolbars:StandardNavigateToolsBlockAddEditColorMarkersGroupQuickPickSelection FiltersObject Visibility LayersSearch ToolbarIf you have installed AMS Simulator A/D, the following six additional toolbars are available. For more information on these toolbars, see the Allegro AMS Simulator User's Guide.AnalogPassiveSourceLinearDiscreteMiscStandard ToolbarThe Standard toolbar has the standard functions that operate on a drawing (Open, Save, Save All, Print, Undo, Redo, Check, Expand, Add New Page, and Import sheets).Navigate ToolbarThe Navigate toolbar includes the functions for navigating the drawing (Descend, Ascend, Previous drawing, Next drawing, Previous page, Next page, Zoom Points, Zoom Fit, Zoom In, and Zoom Out).Tools ToolbarThe Tools toolbar includes the functions to perform actions such as displaying the Attributes form, Highlighting, Dehighlighting, Showing/Hiding unconnected pins, Hiding/Displaying Hierarchy Viewer, and launching Constraint Manager and Part Manager.Block ToolbarThe Block toolbar lets you add blocks, add pins on blocks and draw wires to connect blocks. Add ToolbarThe Add toolbar lets you add objects (components, wires, and text) and graphics such as dots and circles.Edit ToolbarThe Edit toolbar lets you perform edit operations such as copy, paste, delete, and spin. Group ToolbarThe Group toolbar has all the commands for creating and modifying a group. A group is a collections of objects such as notes, components, wires, and properties.Markers ToolbarThe Markers toolbar helps you traverse through schematic errors.Color ToolbarThe Color palette lists the colors supported in Design Entry HDL and allows you to quickly change the colors of various objects.QuickPick ToolbarThe QuickPick toolbar helps you quickly add commonly-used cells, parts, and local blocks to the design.Object Visibility Layers ToolbarThe object visibility toolbar enables you to control the visibility of each object layer. The visibility of each of the object layers can be controlled by pressing or de-pressing the toolbar buttons.Page Search Tool BarThe search toolbar enables you to search for text on the current page. The text could be a symbol text, net name, property or part of a note.Status BarThe status bar displays a single line about the action you are performing or when Design Entry HDL expects you to perform an action.Console Command WindowYou can type commands in this window. The window can also be used to manually test any scripts that you have written for Design Entry HDL. To enable or disable the console command window, choose View - Console Window.Context-Sensitive MenusEvery object in Design Entry HDL has a context-sensitive menu attached to it. The menu appears when you right-click on the object. The menu contains options to perform certain operations that are relevant to the current object and its context. Examples of operations on a symbol are copy, delete, edit, and rotate.Design Entry HDL TasksThe Design Entry HDL tasks covered in this section areCreating a SchematicCreating a Hierarchical DesignCreating a SchematicThe following figure illustrates the sequence of tasks you perform in Design Entry HDL to create a schematic.Tasks of Creating a SchematicCreating a Hierarchical DesignThe following figure illustrates the sequence of tasks you perform to create a hierarchical design.Tasks in Creating a Hierarchical DesignDesign Entry HDL BasicsThis section answers the basic questions that are useful when you start working in Design Entry HDL.Where can I enter commands?You can type commands in the console window that appears below the drawing area when you choose View - Console Window. If you exit Design Entry HDL with the console window option enabled, the console window will appear automatically the next time you start Design Entry HDL.Command Conventions and Entering CommandsEach menu item has an associated Design Entry HDL command. To run a command: Choose a command from a menu.Type a command in the console window, which appears below the drawing area when you choose View - Console Window.Click a toolbar icon.Press the control keys, which are noted next to the frequently used menu commands.Draw a stroke pattern.Write commands in a script file and run the script.You can abbreviate Design Entry HDL commands. Design Entry HDL recognizes the smallest unique portion of the command name and arguments. Design Entry HDL commands are not case-sensitive.Where are setup options?Global setup options are located in the Project Manager. Y ou can access Design Entry HDL setup options both through the Project Manager and through the Tools menu in Design Entry HDL (Tools - Options).How do I pan drawings?You can pan a drawing using the mouse, scroll bars, the keyboard, or the View menu.How do I zoom in and out of a drawing?To zoom into a drawingChoose View - Zoom In.Choose View - Zoom Scale and enter a scale factor such as 2.Choose View - Zoom by Points and stretch a rectangle around the area you want to zoom into:a. Click slightly above and to the left or right of the objects you want to group.b. Drag the cursor down diagonally from where you first clicked.c. Click again.To zoom out of a drawingChoose View - Zoom Out or View - Zoom Scale and enter a scale factor such as 0.5.To fit a drawing in the screenChoose View - Zoom Fit.How do I customize Design Entry HDL?You can customize toolbars, commands, menus, and keys in Design Entry HDL using Tools - Customize.What commands can I use to edit schematic text?You can use the following keyboard commands when running the change command (Text - Change):Are there menu shortcuts?Toolbars provide shortcuts to several functions. Y ou can turn on any or all of the toolbars with the View - Toolbars menu command.Control keys also provide shortcuts to several menu commands. Control-key shortcuts are noted next to the frequently-used menu commands.Press predefined function keys (F1-F12).Standard Windows Alt key functions are also available.How do I browse drawings and components?The capability to add and edit components used to be contained in a single browser. These are now separate functions.Choose File - Open to display a file browser from which you select the drawing you want to edit.Choose Component - Add to display the Component Browser from which you can select components to add to your drawing.How do I add libraries?You add libraries using Tools - Setup in Project Manager. Within Design Entry HDL, you can control the available library list and the search order for libraries using File - View Search Stack. How do I add notes?You can add notes and attach them to the schematic using Text - Note.How do I add parts?You can add parts using Component - Add.How do I connect parts?You can connect parts with wires using Wire - Draw or Wire - Route. Wire - Draw lets youmanually route around objects while Wire - Route automatically routes the wire around objects. Alternatively, right-click the component where you want to add the wire, and choose Add Wire from the pop up menu.How do I name signals?You can name signals using Wire - Signal Name. Y ou can also create buses by naming signals in the appropriate manner. If you name a wire as DATA<15..0>, Design Entry HDL converts the wire to a 16-bit bus.How do I add properties?You can add properties on parts, pins, and signals using Text - Property. Y ou can view, add, and modify the visibility of properties using Text - Attributes.How do I add ports?You can use the ports available in the Standard Library using Component - Add.How do I check my drawing for errors?You control settings for error checks in the Design Entry HDL Setup options accessed through the Tools menu in Design Entry HDL.The Tools - Check menu choice or the Check icon in the Standard toolbar lets you run a check.You can view error messages and locate them in your design using the Markers control window (Tools - Markers). This window also lets you view long, detailed error messages that correspond with the short error messages that are typically displayed.Error Status BarUsing the status bar in combination with the Markers toolbar, you can view short error messages without the Markers control window. Tools - Error controls to navigate the markers file.How do I save a design?You can save a design using File - Save.What is Page Locking?When a user who has write permissions is editing a page in a design, Design Entry HDL locks the page. If a second user opens the same page for editing, Design Entry HDL displays a message that the page is locked by the first user and that the second user cannot save any changes made in the page.If the root design schematic page is a read-only page, or locked by another user, then the "save" option is completely disabled. Y ou cannot make any incontext or schematic changes to the page. If the root schematic context property data file (dcf) is Read Only, then the context save is skipped. Y ou are not able to change the attributes in-context in DEHDL. However, if a lower level schematic page is read only or locked by another user, then you can only make context changes. Y ou will not be able to edit the schematic page. On saving the page, the dcf file is saved with the context changes.Design Entry HDL creates a lock file called pagen_csb.lck in the schematic view when you open a schematic page.How do I add additional pages?Design Entry HDL supports multiple page schematics. Choose File - Edit Page/Symbol - Add New Page to add a new page to the schematic.How do I go to a specific page in a design?1. Choose File - Edit Page/Symbol - Go To.The Go To Page/Symbol dialog box appears.2. Enter the page number and click OK.To go to a specific page in a hierarchical design, select the Calculate page number in hierarchy check box, enter the page number and click OK.Note: If you do not select the Calculate page number in hierarchy check box, you can only go to a page within the cell in which the currently open schematic page exists. For example, if the currently open schematic page is LAPTOP.SCH.1.1, you can only go to pages within the LAPTOP cell.Note: You can also use the gotosheet console command to go to a specific page in a hierarchical design. When the "Calculate sheet number in hierarchy" option is selected, you are navigated to the sheet number, when this option is not selected, the specified page number is edited in the current cell. In this case, the sheet number used by the gotosheet command is the sequential numbering of pages in the entire design hierarchy, while the page number used by the edit command is the physical page number in the current block.For more information on page numbering in Design Entry HDL, see Displaying and W orking with Schematic Page Numbers .How do I plot a design?You can plot a design using File - Plot. On UNIX, you have the option of using the HPF plotting utility also depending on the option you select (Windows plotting or HPF) using Tools - Options - Plotting.What are groups?When you wish to perform a common edit operation like Copy, Move, or Delete on a collection of objects on the schematic, you can define the collection as a group and carry out the operation using the options available in the Group menu.What is different about working with groups?Functions for creating and working with groups are contained in one group menu.A separate toolbar contains the frequently-used group operations.Design Entry HDL makes it easy to set the current group. It clearly shows the group that you are working with at any time by indicating the group name in brackets next to group menu items.Design Entry HDL provides a Group Contents dialog box using which you can see the contents of the groups defined in the schematic.How do I locate parts and wires in a design?You can locate parts and wires in a design using Tools - Global Find. Y ou can also use wildcards on names and narrow down the search using properties and values.How do I generate a symbol view from a schematic?You can generate symbol views from schematics using Tools - Generate View.How do I package my design?You can invoke Packager-XL using the Design Synchronization tool of the Project Manager.Y ou can also use File - Export Physical in Design Entry HDL. For more information on packaging, see Design Synchronization and Packaging User Guide.How do I backannotate a design?Backannotation updates the schematic with the layout changes. It annotates your schematic with physical information such as pin numbers and location designators produced by the Design Synchronization process. Choose Tools - Back Annotate to specify the file (typically pstback.dat) containing the physical information with which you update the schematic.Do not run backannotation if any other user who has writepermissions is working on the design. Running backannotation whenanother user is working on the design results in incompletebackannotation.How do I highlight objects in a design?To highlight an object in a drawing, choose Display - Highlight and click on the object to be highlighted.You might want to highlight objects in your design for the following reasons: To trace a signal on multiple pages of an expanded drawingTo trace a signal in the drawing hierarchy between expanded drawingsTo correlate the circuit logic to changes you made in the schematic or to navigate the nets between a physical layout and the corresponding schematic between Design Entry HDL and other system tools.Choose Display - Dehighlight to remove highlighting.How do I cross-reference a design?When you view a plot of a schematic, it is often difficult to trace a signal or instances of a part. The Cross Referencer tool traces the signals and parts in a schematic and annotates the location of each one.On a cross-referenced design, Cross Referencer writes the page number and the location of the part or signal in relation to the page border. These annotations can be found beside each signaland part that has been cross-referenced.Choose Tools - CRefer in Project Manager to cross-reference your design.How do I archive a design?You can use the Archiver tool to archive your design. This tool copies over all the libraries that are referenced by your design to the archived area. Archiving lets you work on the design at a location where connectivity to the Libraries server is not available.To archive your design, choose Tools - New Archive in Project Manager.How do I view the bias point values in Design Entry HDL?You can enable the bias display feature of Design Entry HDL to view the bias point information, such as bias point voltage, bias point current, and bias power on the schematic. To view bias point values on the schematic you need to perform the following steps:1. Load bias point values.From the AMS Simulator menu choose Bias Point - Preferences. In the Bias Point Preferences dialog box, select the Update Bias Point Information Automatically check box and click OK.2. Choose AMS Simulator - Bias Points - Enable.Menu options for displaying Bias point voltage, bias point current, and bias power are enabled.3. Specify the bias point information to be displayed on the schematic.To display bias point voltages on the schematic, choose AMS Simulator - BiasPoints> Enable Bias V oltage Display.To display bias currents on the schematic, choose AMS Simulator - Bias Points -Enable Bias Current Display.To display bias power values, choose AMS Simulator - Bias Points - Enable BiasPower Display.Note: If you do not want the bias point values to be loaded automatically, skip 1. Instead, select AMS Simulator - Bias Points - Annotate Bias V alues whenever you want to load the latest bias point information on to the schematic.To know more about the bias display feature in Design Entry HDL, see Chapter 15, "Simulating using AMS Simulator".Return to top of pageFor support, see Cadence Online Support service.Copyright © 2012, Cadence Design Systems, Inc.All rights reserved.。

Allegro16.5原理图与PCB新功能介绍

Allegro/OrCAD V16.5Front-EndБ߹඀۞າΑਕ̬௜Graser -AddiSPB V16.5 Front-End Tools•What’s New in OrCAD V16.5 Capture/CIS-Generate Reports for FIND Results-Graphical Locking Support-NetGroup Support-PSpice Test-bench-Separate INI Settings•What’s New in Allegro V16.5 Design Entry-HDL-Selection Filters-Visibility Layers-Advance Find & Navigate-Auto-Complete for Signal Name-Generate Reports for FIND Results : Part Search•After you executethe Find commandon a design, youcan generate areport (CSV orHTML) for theresults from thecommand. What’s New in OrCAD V16.5 Capture/CIS-Generate Reports for FIND Results : Net Search-Graphical Locking Support•Lock / Unlock Components from any graphical move–By selection–By page–By designWhat’s New in OrCAD V16.5 Capture/CIS-NetGroup SupportGROUPA[0..31]GROUPA.A[0..7]GROUPA.B[0..7]GROUPA.C[0..7]GROUPA.D[0..7]GROUPA[0..31]NetGroup-PSpice Test-bench•Ability to generate test-benchdesign and inherit simulationprofile from master•Ability to activate portion of test-bench by–Selection in Master–Selection in Project–Selection in Test-bench•Ability to auto-identify floating nets•SVS for updating Master withchanges in TBWhat’s New in OrCAD V16.5 Capture/CIS -PSpice Test-bench•Extract a portion of design into new design for simulation•ECO between Master and Test-bench design-Separate INI Settings•While the Capture INI settings are always dynamic, the CIS settings are more or less static and usually do not change after the initial CIS database related setup.•To allow change in Capture INI settings without affecting CIS settings•16.5 now retains the CIS INI settings in a separate back-up file.These settings are then restored during re-initialization of Capture INIWhat’s New in Allegro V16.5 Design Entry-HDL -Selection Filters-Visibility LayersWhat’s New in Allegro V16.5 Design Entry-HDL -Advance Find & Navigate•Define Objects for Search–Components, Nets, Properties, Notes, Images,Pins, Plumbing Bodies–Current Page, Design or Current–Search String stored for reuse–Wildcard Support•Selection area on Schematic–Search Method•Docking Window–Windows Standard Columns to show information–Filter results–Double click on object to navigate to it–Copy the display data and paste in ExcelAuto-Complete for Signal NameGraser -JonathanAllegro/OrCAD V16.5Back-EndБ߹඀۞າΑਕ̬௜TopicUser Interface¾Status Bar Updates¾Highlighting with Stipples ¾3-D Viewer Update ¾Color View UpdateUsability Enhancements¾Group Route Via Patterns ¾Differential Pair Phase Tuning ¾Tapered Traces ¾Snake Breakout¾Stacked Via Enhancements ¾HDI –Tangent Via Update ¾Max Neck Length DRC Update ¾Associative Dimensioning ¾Allegro PDF PublisherTopicDFM¾DFA Enhancement¾Backdrill Enhancement¾New Short Detection ReportIDX FlowEmbedded Component Design¾Overview¾Front to Back Flow¾Setup & Methodology¾Placement Applications¾Class-Subclass Support¾Global Parameters¾Design Constraints¾Substrate Cavities¾Manufacturing Output¾ReportsTopicSI¾App Mode¾Setup and Audit¾Source Synchronous Analysis Enhancements¾PDN Analysis Abilities¾IR Drop Current Path Display¾3D VisualizationUser InterfaceStatus Bar Updates¾Functional responses for¾Class-subclass¾App modes¾Super filter¾Number of selected objects User InterfaceStatus Bar Updates¾Pick Dialog¾Support Zoom-Center in App ModeOLD Version16.5 VersionHighlighting with Stipples¾Color Dialog is enhanced tosupport 15 stipple patternsAssign color optionsHighlight optionsUser InterfaceHighlighting with Stipples¾Highlighting of FixedNets/Components¾Differentiation of Keepout areasConstraint Manager¾Color swatches adjacent to nets with color overridesUser Interface3-D Viewer Update¾Synchronize with layer visibility changes made in the design canvas ¾This mode is enabled by default.¾In previous releases, the 3-D Viewer would have to be closed and then re-opened upon any visibility changes.Color View Update¾Preserve Flip State Option added¾Saved color files sorted alphabeticallyOLD Version16.5 Version Usability EnhancementsGroup Route Via Patterns¾Available when using¾Interactive Group Route¾Multiline Router¾Options leveraged from Specctra¾Via pattern options¾PerpendicularUsability Enhancements Group Route Via Patterns¾Via pattern options¾Stagger¾Via pattern options¾Diagonal Left¾Diagonal RightUsability Enhancements Group Route Via Patterns¾Via pattern options¾In Taper¾Out Taper¾New Phase Tune CommandUsability Enhancements Differential Pair Phase Tuning¾Parameter options include:¾Bump width and height¾Line or Arc¾Parameter options include:¾Bump width and height¾Line or ArcUsability Enhancements Tapered Traces¾New dynamic fillet option¾Shape based fillet designed to “taper”line width changes along a clineTapered Traces¾Set option in gloss parameter form¾Fillet and Tapered TraceUsability Enhancements Snake Breakout¾Designed for Hex Pattern BGABreakout¾Diff Pair and single route¾User Preference Variable¾Made available in 16.3Stacked Via Enhancements¾B/B Via Label¾New color option to differentiate stacked vias from single B/B via¾Copy/Move Stacked Vias¾Command support for maintaining complete stackUsability EnhancementsHDI –Tangent Via Update¾New option to run on selected clinesOLD Version16.5 VersionMax Neck Length DRC update¾Check will transform segment from based to cumulativeUsability Enhancements Associative Dimensioning¾Dimension lines/text dynamically update when associated objects are moved¾Eliminate the need to “re-dimension”when changes are madeOLD Version16.5 Version¾Dimension lines/text dynamically update when associated objects are moved¾Eliminate the need to “re-dimension”when changes are madeUsability Enhancements Associative Dimensioning¾Dimension lines/text dynamically update when associated objects are moved¾Eliminate the need to “re-dimension”when changes are made¾New Dimension Edit Environment¾New ones introduced¾Align, z-copy, instance parametersUsability EnhancementsAllegro PDF Publisher (option)NonͲfilledComponent RefdesComponent OutlineBoard OutlineFilled¾PDF Output driven by Artwork film records¾Existing color settingsUsability Enhancements Allegro PDF Publisher (option)¾Exported Data¾Components¾Component Refdes( with pin numbers)¾Component Properties¾Nets¾Net Name¾Net Properties¾Test pointsUsability Enhancements Allegro PDF Publisher (option)¾Zoom to SelectionDFA Enhancement¾DFA Table to support 4th spacing entry¾“End to Side”¾New syntax –S:S;E:E;S-E;E-S¾In the example below, A and B must be different spacing values¾Usability improvement¾Easier to place component to minimum spacing (dfa pause = 3)Design for ManufacturabilityDFA Enhancement¾DFA Table to support 4th spacing entry¾“End to Side”¾New syntax –S:S;E:E;S-E;E-S¾In the example below, A and B must be different spacing values¾Usability improvement¾Easier to place component to minimum spacing (dfa pause = 3)Backdrill Enhancement¾Any Layer Backdrilling¾Required on Type I HDI Designs where backdrilling of “Core”vias is required¾Currently backdrilling is permitted from only the top & bottom sides of the PCBDesign for Manufacturability New Short Detection Report¾Status dialog now indicates “NetShorting Errors”¾Net Short report also added tostandard report listECAD/MCAD EDMD 1.2 (IDX)¾EDMD Schema v1.2¾Same features as IDF3.0 w/o Panelization¾Standards managed by ProStep consortium ¾Incremental Format¾Baseline¾Incremental change of baseline¾Collaboration¾Accept, reject, suggest changes¾View change before action¾Add comments about changes¾Corporate Partnership¾Cadence/PTCIDX FlowInitial baseline,Incremental modificationsFinal baseline synchronizationInitial baseline,Incremental modificationsFinal baseline synchronizationIDX FlowInitial baseline,Incremental modificationsFinal baseline synchronizationOverview¾Both Active and Passive components can be embedded ¾Passives¾0402 & 0201¾Resistors 10 to 10Meg Ohm¾Caps up to 100 nF¾Height 4 to 13 mils (100-350um)¾Actives¾Ultrathin (4 to 6 mils)¾ESD protection diodes¾Dies (30-50 IO)Embedded Component Design Setup & Methodology¾Embedded Layer Setup¾Define legal layer(s) to embeddedcomponents on¾Controls direction of component¾Body Up¾Body Down¾Permit layers to be “Protruding”¾Components extend in adjacentlayers¾Define Methodology¾Direct Attach¾Indirect AttachPlacement Applications¾Interactive Placement¾RMB support to drop componentto internal layer(s)¾Pre-selection support¾Hover over component thenuse RMB context sensitivemenu to change layer¾Embedded labels¾Options form support forEmbedded Required andOptionalEmbedded Component Design Placement Applications¾Quickplace Application¾Use to quickly placeembedded components totheir destination layer¾Reduce dependency onmanually droppingcomponents to internal layer¾Enhanced to filter componentswith embedded property¾Board Layer pull downsupports embedded layersConstraint ManagerEmbedded_Placement properties can be applied in CM “Properties”Domain Layer, Status and Attach are read-only fieldsEmbedded Component Design Placement Applications¾DFA Support¾Top side table valuesare used to drivecomponent tocomponent clearancePlacement Applications¾Placement Replication¾Supports embeddedcomponents as part ofreplicated circuitryEmbedded compsEmbedded Component Design Class-Subclass Support¾Enabling the “Body up/down”triggers the relevantdatabase infrastructuresupport¾New Embedded GeometryClass¾Placebounds¾Pastemask¾Assembly¾DisplayGlobal Parameters¾Package Height Buffer¾Define a clearance or buffer whencalculating component heightviolations in a substrate¾Minimum Cavity Gap for Merge¾Define the minimum spacingbetween the edges of a cavity beforea merger takes place¾Placebound to via keepout expansion¾Create a via keepout area based onthe Placebound geometry¾Package to Cavity spacing¾Define the clearance from the edgeof the placebound shape to the cavityoutlineEmbedded Component Design Global Parameters¾Via Connect Height¾Define a height constant for the gapbetween the conductor layer andcomponent pin suspended in thedielectric area¾Default Via Connect Padstack¾Use to define connect point ofcomponent. Typically a single layermicro via.¾Cavity to Route Keepout Expansion¾Become available when a layer is setto “Protruding Allowed”. While thecavity has inherent route keepoutbehavior, it may be desirable toextend the keepout area beyond thecavity profileConstraints¾Package to Cavity¾Define the clearance betweenthe symbol’s place-boundshape to edge of cavity¾Package Height to Layer¾Enable to detect symbolheight violations in dielectricspace¾Integrated Spacing DRCs¾Basic metal to metal¾Embedded SMD pin to viashown in figureEmbedded Component Design Substrate Cavities¾Closed Cavity¾The space around the embedded component in the dielectric between two etch layers. The XY dimensions of the cavity aredriven by the size of the component. In most applications, the cavitywill be between two adjacent layers; however, multilayer cavities issupported.¾Open Cavity¾A blind hole in the substrate in which components are placed. This hole is open to one of the external substrate surfaces and may beseveral layers deep. The cavity may have progressively smallerlengths and widths from the external surface to the depth of thecavity.Manufacturing Output¾Cross Section Chart¾New in 16.5¾Menu Path: Manufacturing–Cross Section Chart¾Drill Legend¾Support of Cavities¾Start:Stop Layer¾Qty of comps¾Artwork Film Records¾ODB++ ver9.1Embedded Component Design Reports¾New Reports¾Embedded Component¾Embedded Cavity¾Updates to Existing Reports¾Component¾Placed Component¾Summary Drawing¾Design Rule ChecksSI App Mode¾Improved integration for board levelsimulation¾Available and Launched like other App Modes ¾No need to switch editors¾Super Command for SI related tasks and includes:Highlight on hover Context sensitive RMB menusSI Setup and Audit¾New commands to replace existing¾Both are Wizard based¾Addresses issues with currenterror / warning pop-ups¾New menu location (Setup)¾Both offer Category & Net selectionSource Synchronous Analysis Enhancements ¾Multi Strobe Support¾(aka Address topology)¾Timing Margin Calculation¾Updated Bus Simulation Report¾Added flexibility for derating tablesPDN Analysis Abilities¾Static IR Drop Analysis¾Voltage drop distribution¾Current distribution¾Current density distribution¾Temperature distribution¾PI Plane Analysis¾Design guide¾Pre-route analysis¾PI Network Analysis¾Post-route verificationIR Drop Current Path Display¾Showing current flowing direction with arrows¾Canvas selection reveals current value in Options paneIR Drop Current Density Display ¾Easy to find “hot spots”¾Current direction shown as well3D Visualization ¾Stretch Item¾Env var: PDNS_3DVIEWER ¾Ability to display¾Impedance (FD)¾Voltage Ripple (TD)¾Current Density (TD)¾Temperature Rise(TD)¾Binary file created (.emv)¾Threshold plane display¾Worse case display¾Layer-based display63。

Allegro设计步骤-PCB设计-于博士视频笔记(转+修改)

视频笔记_于博士视频笔记(转+修改)备注：1、未掌握即未进行操作2、操作软件是15.5版本，若有修改则为16.5版本26、非电气引脚零件的制作1、建圆形钻孔：（1）、parameter：没有电器属性（non-plated）（2）、layer：只需要设置顶层和底层的regular pad，中间层以及阻焊层和加焊层都是null。

注意：regular pad要比drill hole大一点。

27、PCB电路板的建立主要内容：建立电路板及绘制相关区域步骤：0、建立电路板：File - New - 选择路径及Board1、设置绘图区参数，包括单位，大小：Setup - Drawing Size2、定义outline区域：Add - Line（Optons - Board Geometry - Outline）- (可使用命令模式输入坐标 x 0 0和ix iy)备注：添加导角（倒角）：Manufacture - Dimension/Draft - Chamfer(方形导角)或者Fillet(圆形导角) - 左键依次选择需要导角的边。

16.53、定义route keepin区域：Setup - Areas - Route keepin - (可使用命令模式输入坐标 x 0 0和ix iy)（可使用Z-copy操作：Edit - Z-Cpoy - 在Options里subclass 中选择Route Keepin，contract：内缩，Expand：外扩，Offset：内或外的偏移数量）备注：一般大板子（空间够大）：一般走线（route Keepin）限制在板框40mil以内，放置元件(package keepin)在80mil以内route keepout 一般是用于螺丝孔，使用route keepout包围螺丝孔意味着该区域内不可布线。

4、定义package keepin区域：Setup - Areas - Package keepin - (可使用命令模式输入坐标 x 0 0和ix iy)（可使用Z-copy操作）5、添加定位孔：place - manually - advance setting - 勾选Library - Placement List 中下拉框中选择Package Symbols或者Mechanical symbols中选择定位孔28、Allegro PCB 的参数设置主要内容：内电层的建立及其覆铜Allegro定义层叠结构：对于最简单的四层板，只需要添加电源层和底层，步骤如下：1、Setup –> cross-section2、添加层，电源层和地层都要设置为plane（内电层），同时还要在电气层之间加入电介质，一般为FR-43、指定电源层和地层都为负片（negtive）4、设置完成可以再Visibility看到多出了两层：GND和POWER5、铺铜（可以放到布局后再做）6、Edit->z-copy –> find面板选shape（因为铺铜是shape） –> option面板的copy to class/subclass选择ETCH/GND（注意选择create dynamic shape：动态覆铜）- 左键选择图形（比如route keepin） - 完成GND层覆铜7、相同的方法完成POWER层覆铜补充：Allegro生成网表1、重新生成索引编号：tools –> annotate2、DRC检查：tools –> Design Rules Check，查看session log。

Allegro17_2基本学习流程的思维导图_V1.0_20200204

添加丝印 PCB检查事项生成钻孔表
导出Gerber文件导出光绘文件PDF 导出PCB的3D文件导出贴片的坐标文件
导出文件
封装的制作
PCB设计预处理
手动建立电路板建立电路板向导建立电路板
导入DXF文件绘图参数的设置
Allegro环境的设置 Grid的设置颜色属性的设置
层叠设置导入网络表
物理规则设置间距规则设置差分等长设置规则开关的设置
约束管理器的设置
布局布线覆铜子主题
Pt 丝印处理调整位号
Cadence Allegro 基本学习流程
Orcad Capture CIS原理图设计
菜单栏详解
建立单逻辑器件
建立多逻辑器件
绘制原理图
建立工程绘制过程
DRC检查
生成网络表的操作
生成网络表交互设置
常见错误解析
PCB 焊盘设计
通孔焊盘表贴焊盘过孔不规则焊盘
SMD封装的制作插件封装的制作不规则封装的制作封装上的焊盘的更新与替换

allegro操作流程

allegro操作流程下载温馨提示:该文档是我店铺精心编制而成，希望大家下载以后，能够帮助大家解决实际的问题。

文档下载后可定制随意修改，请根据实际需要进行相应的调整和使用，谢谢!并且，本店铺为大家提供各种各样类型的实用资料，如教育随笔、日记赏析、句子摘抄、古诗大全、经典美文、话题作文、工作总结、词语解析、文案摘录、其他资料等等，如想了解不同资料格式和写法，敬请关注!Download tips: This document is carefully compiled by theeditor. I hope that after you download them,they can help yousolve practical problems. The document can be customized andmodified after downloading,please adjust and use it according toactual needs, thank you!In addition, our shop provides you with various types ofpractical materials,such as educational essays, diaryappreciation,sentence excerpts,ancient poems,classic articles,topic composition,work summary,word parsing,copy excerpts,other materials and so on,want to know different data formats andwriting methods,please pay attention!1. 启动 Allegro 软件打开 Allegro 软件。

Allegro层次原理图(模块reuse)设计流程

Module reuse1.在orcad中画好模块的原理图，设定好封装，做好drc，做好元件编号。

2.在annotate-->allegro reuse中，选中generate reuse module, renumber design forusing modules不选,选中unconditional,其它不选。

3.生成netlist.4.将netlist导入到allegro，布线，布局，若无rename等需要与orcad交互的动作，，选tools-->create modules生成mdd文件.mdd文件的文件名一定要定义为：DSN NAME_ROOT SCHEMATIC NAME.mdd。

DSN NAME为你定义的orcad中的dsn文件名，ROOT SCHEMATIC NAME是这个文件中的页名字。

这里若定义不对，在reuse时找不到mdd文件。

之后跳到第6步。

5.在orcad中back annotate,之后回到第2步。

6.模块制作完成。

使用生成的模块1.在新的orcad设计中，选place-->herarhical block,reference中填入BLK?(注意，这里不能用BLK是为了与原理图中的U？R？C？区别，保证BLK这个名字专用于moduel，不然在做完allegro后，rename 时，导回到orcad中出问题。

)在implementation type中选schematic view，在implementtation name中填入先前模块的页名称ROOT SCHEMATIC NAME，在path and file name中选择相应的dsn文件，之后在你的原理图中出现一个block.2.继续其它设计(包括放入其它block)，当你双击任一个BLOCK时会发现都将进入到模块原理图中，注意每个模块位号现在还是一样的。

之后开始控制位号，为了区别各个模块的位号，可以控制其各个模块的REF区间在annotate-->allegro reuse中,选中,renumber design for using modules,选中incremental,选中do not change the page number,选中select modules to mark for框里的内容。

Allegro16.3—原理图的设计-曹世鹏

打开原理图软件1）开始——程序——Candence——Release 16.3——Design Entry CIS——选择OrCAD Capture CIS进入原理图设计界面2）3）设置画线时引脚自动捕捉功能4）可以在File——Change Product中更改。

5）可以首先对原理图进行一下设置。

Option——Design Template弹出对话框菜单其中Title Block选项是原理图右下角的信息若不想显示此信息框，可以在Options——Schematic Page Properties中设置不勾选Displayed3）开始创建工程文件File——New——Project4）点击OK后打开的页面是这样的。

其中PAGE1可以修改名字。

在PAGE1上面右击选择rename即可修改5）然后可以修改原理图背景颜色。

Options——Preferences。

其中修改Colors/Print选项中的Background项，选择自己喜欢的颜色就可以了。

2创建元件库1）开始——程序——Candence——Release 16.3——Design Entry CIS——选择OrCAD Capture CIS进入原理图设计界面2）File——New——Library3）其中库的根目录可以修改。

在上面右击，选择Save as另存到自己喜欢的文件夹里面就可以了。

4）创建元器件可以在库的根目录上右击，选择New part。

也可以Design——New part其中Part per Pkg不是指的引脚个数。

是因为如果原件引脚比较大，则可以把原件分为多个部分，然后拼起来。

这是指的原件所分成的多少部分。

下面是常见元器件的命名规则电阻R 电感L排阻RN 电容 C磁珠FB 芯片U模块MOD 晶振Y三极管Q或T普通小信号放大用QMOSEFT管采用T整流二极管ZD 发光二极管LED连接器X 跳线J开关K或者SW 电池BAT 固定通孔MH Mark点H测试点TP 二极管 D然后点击Ok以后生成。

Allegro原理图设计
三、电路原理图绘制
8、添加文字(place text) 点击place text… 按钮，系统弹出如下对话框：
Allegro原理图设计
四、原理图页相关操作
1、移动原理图页面及原理图文件夹 a原理图页面在多个原理图文件夹间转移 b原理图页面在不同工程之间转移
2、重命名操作 a原理图与原理图文件夹重命名 b工程文件.opj重命名 c设计文件.dsn重命名
Allegro原理图设计
三、电路原理图绘制
放置好层次图后，接下来就是放置层次图的管脚。放置层次图管脚时，必须保证层次图被选中。点击Place Pin，调出下示对话框：
Allegro原理图设计
三、电路原理图绘制
6、放置端口与分页图纸间的界面点击 Place Hierarchical Port (或place Off-page connector )放置端口(或分页图纸间的接口)，调出如下对话框：
Allegro原理图设计
三、电路原理图绘制
3、放置网络名称(place net name)
点击place net alias 按钮，调出place net alias 对话框，在alias对话框中输入要定义的名称，然后点击OK 退出对话框，把鼠标移动到你要命名的网络连接线上，点击鼠标左键即可。
Allegro原理图设计
二、工程文件的创建与设置
Allegro原理图设计
二、工程文件的创建与设置
4、创建原理图文件夹和原理图子图创建完成的工程文件如下图所示。
Allegro原理图设计
二、工程文件的创建与设置
Allegro原理图设计
三、电路原理图绘制
新建 project 后，进入Schematic 窗口，则在窗口右边会出现下图的工具栏：

Allegro原理图和PCB设计流程学习指南

Allegro原理图和PCB设计流程学习指南一、非电气引脚零件的制作1、建圆形钻孔：1）、parameter：没有电器属性（non-plated）2）、layer：只需要设置顶层和底层的regular pad，中间层以及阻焊层和加焊层都是null。

注意：regular pad要比drill hole大一点。

二、Allegro建立电路板板框步骤：1、设置绘图区参数，包括单位，大小。

2、定义outline区域3、定义route keepin区域（可使用Z-copy操作）4、定义package keepin区域5、添加定位孔三、Allegro定义层叠结构对于最简单的四层板，只需要添加电源层和底层，步骤如下：1、Setup –> cross-section2、添加层，电源层和地层都要设置为plane，同时还要在电气层之间加入电介质，一般为FR-43、指定电源层和地层都为负片（negtive）4、设置完成可以再Visibility看到多出了两层：GND和POWER5、铺铜（可以放到布局后再做）6、z-copy –> find面板选shape（因为铺铜是shape）–> option面板的copy to class/subclass选择ETCH/GND（注意选择create dynamic shape）完成GND 层覆铜7、相同的方法完成POWER层覆铜四、Allegro生成网表1、重新生成索引编号：tools –> annotate2、DRC检查：tools –> Design Rules Check，查看session log。

3、生成网表：tools –> create netlist，产生的网表会保存到allegro文件夹，可以看一下session log内容。

五、Allegro导入网表1、file –> import –> logic –> design entry CIS（这里有一些选项可以设置导入网表对当前设计的影响）2、选择网表路径，在allegro文件夹。

【Allegro档案】CADENCE从原理图到PCB

CADENCE从原理图到PCB步骤一．原理图1．建立工程与其他绘图软件一样，OrCAD以Project来管理各种设计文件。

点击开始菜单，然后依次是所有程序-- Allegro SPB 15.5--Design Entry CIS，在弹出的Studio Suite Selection对话框中选择第一项OrCAD_Capture_CIS_option with capture，点击Ok进入Capture CIS。

接下来是File--New--Project，在弹出的对话框中填入工程名、路径等等，点击Ok进入设计界面。

2．绘制原理图新建工程后打开的是默认的原理图文件SCHEMATIC1 PAGE1，右侧有工具栏，用于放置元件、画线和添加网络等等，用法和Protel类似。

点击上侧工具栏的Project manager（文件夹树图标）进入工程管理界面，在这里可以修改原理图文件名、设置原理图纸张大小和添加原理图库等等。

1）修改原理图纸张大小：双击SCHEMATIC1文件夹，右键点击PAGE1，选择Schematic1 Page Properties，在Page Size 中可以选择单位、大小等；2）添加原理图库：File--New--Library，可以看到在Library文件夹中多了一个library1.olb的原理图库文件，右键单击该文件，选择Save，改名存盘；3）添加新元件：常用的元件用自带的（比如说电阻、电容的），很多时候都要自己做元件，或者用别人做好的元件。

右键单击刚才新建的olb库文件，选New Part，或是New Part From Spreadsheet，后者以表格的方式建立新元件，对于画管脚特多的芯片元件非常合适，可以直接从芯片Datasheet中的引脚描述表格中直接拷贝、粘贴即可（pdf格式的Datasheet按住Alt键可以按列选择），可以批量添加管脚，方便快捷。

4）生成网络表（Net List）：在画板的时候需要导入网络表，在这之前原理图应该差不多完工了，剩下的工作就是查缺补漏。

PCB设计流程-Allegro

Add Pin
Schematic Design
Add Package Outline
Schematic Design
Add Package Outline
Schematic Design
Save Schematic Package
Schematic Design
Save as Schematic Library
Schematic Design
Create NetlistCreat Allegro PCB Editor
Schematic Design
Select Cadence Product to open PCB
PCB Layout
Setup Drawing Parameters
PCB Layout
PCB Layout
Find 上视图
PCB Layout
Move 上视图 to origin
Origin
PCB Layout
Place Board Outline
Shape
Layer Board Outline
PCB Layout
Z-Copy route keep in Outline
DRC原理图，若有问题，查看Session Log，根据Warning or Error 对原理图修正
DRC
Schematic Design
Design Rules Check
Schematic Design
Session Log
Schematic Design
Create Netlist
PCB Layout
Place Drill Table
UNIT

Allegro原理图设计原版教程

Allegro® Design Entry HDL User GuideProduct Version 16.6 October 20122Getting StartedThis chapter contains the following information:Starting Design Entry HDLDesign Entry HDL User InterfaceDesign Entry HDL TasksDesign Entry HDL BasicsStarting Design Entry HDLAfter you open the desired design project in Project Manager, the flow area of Project Manager displays the Cadence Board Design flow. In the Board Design flow, click the Design Entry icon.Note: You must be on the Common Desktop Environment (CDE) on a Sun workstation to run the Design Entry HDL set of tools.To launch Design Entry HDL, do one of the following:1. In Project Manager, open the .cpm file of a project and then click the Design Entry icon.--or--2. Choose Start - Programs - Cadence - Release 16.6 - Design Entry HDL.--or--3. At the command prompt, type concepthdl and press ENTER.Design Entry HDL User InterfaceWhen you launch Design Entry HDL using any of the three methods listed above, the Design Entry HDL user interface appears (as shown in the following figure).The Design Entry HDL interface consists of the following elements: Design windowMenu barToolbarsStatus barGlobal Navigation windowConsole command windowContext-sensitive menusMenu BarThe Design Entry HDL menu bar includes the following menus:FileFor operations such as opening, saving, and plotting a drawing.EditFor operations such as Undo, Copy, Paste, Delete, Spin, and Color.ViewFor operations such as Zoom, Pan, and Grid.ComponentFor operations that can be done on a part such as adding, replacing, and modifying a part.WireFor operations such as connecting parts and naming signals.TextFor operations such as adding properties and notes.BlockFor operations such as adding blocks.GroupFor operations such as creating groups and performing editing functions on groups.DisplayFor operations such as highlighting and de-highlighting components.AMS SimulatorFor performing analog, digital and mixed-signal simulation using the AMS Simulator. This menu is visible only if you have installed AMS Simulator.RF-PCBInvokes the RF-PCB IFF Import UI which enables you to import radio frequency design into your schematic.ToolsFor operations such as setting up defaults, customizing, updating the schematic with layout changes, updating the layout with schematic changes, finding nets and instances in your design, global navigation, checking your design, and running scripts.WindowFor operations such as opening a new window, cascading and tiling it.HelpInvokes the Design Entry HDL help page and web resources such as Cadence OnlineSupport and Education Services.In the Windows Mode, menu bar and menu options are different fromthe normal more. See Reorganized Menus for more information.ToolbarsDesign Entry HDL has the following toolbars:StandardNavigateToolsBlockAddEditColorMarkersGroupQuickPickSelection FiltersObject Visibility LayersSearch ToolbarIf you have installed AMS Simulator A/D, the following six additional toolbars are available. For more information on these toolbars, see the Allegro AMS Simulator User's Guide.AnalogPassiveSourceLinearDiscreteMiscStandard ToolbarThe Standard toolbar has the standard functions that operate on a drawing (Open, Save, Save All, Print, Undo, Redo, Check, Expand, Add New Page, and Import sheets).Navigate ToolbarThe Navigate toolbar includes the functions for navigating the drawing (Descend, Ascend, Previous drawing, Next drawing, Previous page, Next page, Zoom Points, Zoom Fit, Zoom In, and Zoom Out).Tools ToolbarThe Tools toolbar includes the functions to perform actions such as displaying the Attributes form, Highlighting, Dehighlighting, Showing/Hiding unconnected pins, Hiding/Displaying Hierarchy Viewer, and launching Constraint Manager and Part Manager.Block ToolbarThe Block toolbar lets you add blocks, add pins on blocks and draw wires to connect blocks. Add ToolbarThe Add toolbar lets you add objects (components, wires, and text) and graphics such as dots and circles.Edit ToolbarThe Edit toolbar lets you perform edit operations such as copy, paste, delete, and spin. Group ToolbarThe Group toolbar has all the commands for creating and modifying a group. A group is a collections of objects such as notes, components, wires, and properties.Markers ToolbarThe Markers toolbar helps you traverse through schematic errors.Color ToolbarThe Color palette lists the colors supported in Design Entry HDL and allows you to quickly change the colors of various objects.QuickPick ToolbarThe QuickPick toolbar helps you quickly add commonly-used cells, parts, and local blocks to the design.Object Visibility Layers ToolbarThe object visibility toolbar enables you to control the visibility of each object layer. The visibility of each of the object layers can be controlled by pressing or de-pressing the toolbar buttons.Page Search Tool BarThe search toolbar enables you to search for text on the current page. The text could be a symbol text, net name, property or part of a note.Status BarThe status bar displays a single line about the action you are performing or when Design Entry HDL expects you to perform an action.Console Command WindowYou can type commands in this window. The window can also be used to manually test any scripts that you have written for Design Entry HDL. To enable or disable the console command window, choose View - Console Window.Context-Sensitive MenusEvery object in Design Entry HDL has a context-sensitive menu attached to it. The menu appears when you right-click on the object. The menu contains options to perform certain operations that are relevant to the current object and its context. Examples of operations on a symbol are copy, delete, edit, and rotate.Design Entry HDL TasksThe Design Entry HDL tasks covered in this section areCreating a SchematicCreating a Hierarchical DesignCreating a SchematicThe following figure illustrates the sequence of tasks you perform in Design Entry HDL to create a schematic.Tasks of Creating a SchematicCreating a Hierarchical DesignThe following figure illustrates the sequence of tasks you perform to create a hierarchical design.Tasks in Creating a Hierarchical DesignDesign Entry HDL BasicsThis section answers the basic questions that are useful when you start working in Design Entry HDL.Where can I enter commands?You can type commands in the console window that appears below the drawing area when you choose View - Console Window. If you exit Design Entry HDL with the console window option enabled, the console window will appear automatically the next time you start Design Entry HDL.Command Conventions and Entering CommandsEach menu item has an associated Design Entry HDL command. To run a command: Choose a command from a menu.Type a command in the console window, which appears below the drawing area when you choose View - Console Window.Click a toolbar icon.Press the control keys, which are noted next to the frequently used menu commands.Draw a stroke pattern.Write commands in a script file and run the script.You can abbreviate Design Entry HDL commands. Design Entry HDL recognizes the smallest unique portion of the command name and arguments. Design Entry HDL commands are not case-sensitive.Where are setup options?Global setup options are located in the Project Manager. Y ou can access Design Entry HDL setup options both through the Project Manager and through the Tools menu in Design Entry HDL (Tools - Options).How do I pan drawings?You can pan a drawing using the mouse, scroll bars, the keyboard, or the View menu.How do I zoom in and out of a drawing?To zoom into a drawingChoose View - Zoom In.Choose View - Zoom Scale and enter a scale factor such as 2.Choose View - Zoom by Points and stretch a rectangle around the area you want to zoom into:a. Click slightly above and to the left or right of the objects you want to group.b. Drag the cursor down diagonally from where you first clicked.c. Click again.To zoom out of a drawingChoose View - Zoom Out or View - Zoom Scale and enter a scale factor such as 0.5.To fit a drawing in the screenChoose View - Zoom Fit.How do I customize Design Entry HDL?You can customize toolbars, commands, menus, and keys in Design Entry HDL using Tools - Customize.What commands can I use to edit schematic text?You can use the following keyboard commands when running the change command (Text - Change):Are there menu shortcuts?Toolbars provide shortcuts to several functions. Y ou can turn on any or all of the toolbars with the View - Toolbars menu command.Control keys also provide shortcuts to several menu commands. Control-key shortcuts are noted next to the frequently-used menu commands.Press predefined function keys (F1-F12).Standard Windows Alt key functions are also available.How do I browse drawings and components?The capability to add and edit components used to be contained in a single browser. These are now separate functions.Choose File - Open to display a file browser from which you select the drawing you want to edit.Choose Component - Add to display the Component Browser from which you can select components to add to your drawing.How do I add libraries?You add libraries using Tools - Setup in Project Manager. Within Design Entry HDL, you can control the available library list and the search order for libraries using File - View Search Stack. How do I add notes?You can add notes and attach them to the schematic using Text - Note.How do I add parts?You can add parts using Component - Add.How do I connect parts?You can connect parts with wires using Wire - Draw or Wire - Route. Wire - Draw lets youmanually route around objects while Wire - Route automatically routes the wire around objects. Alternatively, right-click the component where you want to add the wire, and choose Add Wire from the pop up menu.How do I name signals?You can name signals using Wire - Signal Name. Y ou can also create buses by naming signals in the appropriate manner. If you name a wire as DATA<15..0>, Design Entry HDL converts the wire to a 16-bit bus.How do I add properties?You can add properties on parts, pins, and signals using Text - Property. Y ou can view, add, and modify the visibility of properties using Text - Attributes.How do I add ports?You can use the ports available in the Standard Library using Component - Add.How do I check my drawing for errors?You control settings for error checks in the Design Entry HDL Setup options accessed through the Tools menu in Design Entry HDL.The Tools - Check menu choice or the Check icon in the Standard toolbar lets you run a check.You can view error messages and locate them in your design using the Markers control window (Tools - Markers). This window also lets you view long, detailed error messages that correspond with the short error messages that are typically displayed.Error Status BarUsing the status bar in combination with the Markers toolbar, you can view short error messages without the Markers control window. Tools - Error controls to navigate the markers file.How do I save a design?You can save a design using File - Save.What is Page Locking?When a user who has write permissions is editing a page in a design, Design Entry HDL locks the page. If a second user opens the same page for editing, Design Entry HDL displays a message that the page is locked by the first user and that the second user cannot save any changes made in the page.If the root design schematic page is a read-only page, or locked by another user, then the "save" option is completely disabled. Y ou cannot make any incontext or schematic changes to the page. If the root schematic context property data file (dcf) is Read Only, then the context save is skipped. Y ou are not able to change the attributes in-context in DEHDL. However, if a lower level schematic page is read only or locked by another user, then you can only make context changes. Y ou will not be able to edit the schematic page. On saving the page, the dcf file is saved with the context changes.Design Entry HDL creates a lock file called pagen_csb.lck in the schematic view when you open a schematic page.How do I add additional pages?Design Entry HDL supports multiple page schematics. Choose File - Edit Page/Symbol - Add New Page to add a new page to the schematic.How do I go to a specific page in a design?1. Choose File - Edit Page/Symbol - Go To.The Go To Page/Symbol dialog box appears.2. Enter the page number and click OK.To go to a specific page in a hierarchical design, select the Calculate page number in hierarchy check box, enter the page number and click OK.Note: If you do not select the Calculate page number in hierarchy check box, you can only go to a page within the cell in which the currently open schematic page exists. For example, if the currently open schematic page is LAPTOP.SCH.1.1, you can only go to pages within the LAPTOP cell.Note: You can also use the gotosheet console command to go to a specific page in a hierarchical design. When the "Calculate sheet number in hierarchy" option is selected, you are navigated to the sheet number, when this option is not selected, the specified page number is edited in the current cell. In this case, the sheet number used by the gotosheet command is the sequential numbering of pages in the entire design hierarchy, while the page number used by the edit command is the physical page number in the current block.For more information on page numbering in Design Entry HDL, see Displaying and W orking with Schematic Page Numbers .How do I plot a design?You can plot a design using File - Plot. On UNIX, you have the option of using the HPF plotting utility also depending on the option you select (Windows plotting or HPF) using Tools - Options - Plotting.What are groups?When you wish to perform a common edit operation like Copy, Move, or Delete on a collection of objects on the schematic, you can define the collection as a group and carry out the operation using the options available in the Group menu.What is different about working with groups?Functions for creating and working with groups are contained in one group menu.A separate toolbar contains the frequently-used group operations.Design Entry HDL makes it easy to set the current group. It clearly shows the group that you are working with at any time by indicating the group name in brackets next to group menu items.Design Entry HDL provides a Group Contents dialog box using which you can see the contents of the groups defined in the schematic.How do I locate parts and wires in a design?You can locate parts and wires in a design using Tools - Global Find. Y ou can also use wildcards on names and narrow down the search using properties and values.How do I generate a symbol view from a schematic?You can generate symbol views from schematics using Tools - Generate View.How do I package my design?You can invoke Packager-XL using the Design Synchronization tool of the Project Manager.Y ou can also use File - Export Physical in Design Entry HDL. For more information on packaging, see Design Synchronization and Packaging User Guide.How do I backannotate a design?Backannotation updates the schematic with the layout changes. It annotates your schematic with physical information such as pin numbers and location designators produced by the Design Synchronization process. Choose Tools - Back Annotate to specify the file (typically pstback.dat) containing the physical information with which you update the schematic.Do not run backannotation if any other user who has writepermissions is working on the design. Running backannotation whenanother user is working on the design results in incompletebackannotation.How do I highlight objects in a design?To highlight an object in a drawing, choose Display - Highlight and click on the object to be highlighted.You might want to highlight objects in your design for the following reasons: To trace a signal on multiple pages of an expanded drawingTo trace a signal in the drawing hierarchy between expanded drawingsTo correlate the circuit logic to changes you made in the schematic or to navigate the nets between a physical layout and the corresponding schematic between Design Entry HDL and other system tools.Choose Display - Dehighlight to remove highlighting.How do I cross-reference a design?When you view a plot of a schematic, it is often difficult to trace a signal or instances of a part. The Cross Referencer tool traces the signals and parts in a schematic and annotates the location of each one.On a cross-referenced design, Cross Referencer writes the page number and the location of the part or signal in relation to the page border. These annotations can be found beside each signaland part that has been cross-referenced.Choose Tools - CRefer in Project Manager to cross-reference your design.How do I archive a design?You can use the Archiver tool to archive your design. This tool copies over all the libraries that are referenced by your design to the archived area. Archiving lets you work on the design at a location where connectivity to the Libraries server is not available.To archive your design, choose Tools - New Archive in Project Manager.How do I view the bias point values in Design Entry HDL?You can enable the bias display feature of Design Entry HDL to view the bias point information, such as bias point voltage, bias point current, and bias power on the schematic. To view bias point values on the schematic you need to perform the following steps:1. Load bias point values.From the AMS Simulator menu choose Bias Point - Preferences. In the Bias Point Preferences dialog box, select the Update Bias Point Information Automatically check box and click OK.2. Choose AMS Simulator - Bias Points - Enable.Menu options for displaying Bias point voltage, bias point current, and bias power are enabled.3. Specify the bias point information to be displayed on the schematic.To display bias point voltages on the schematic, choose AMS Simulator - BiasPoints> Enable Bias V oltage Display.To display bias currents on the schematic, choose AMS Simulator - Bias Points -Enable Bias Current Display.To display bias power values, choose AMS Simulator - Bias Points - Enable BiasPower Display.Note: If you do not want the bias point values to be loaded automatically, skip 1. Instead, select AMS Simulator - Bias Points - Annotate Bias V alues whenever you want to load the latest bias point information on to the schematic.To know more about the bias display feature in Design Entry HDL, see Chapter 15, "Simulating using AMS Simulator".Return to top of pageFor support, see Cadence Online Support service.Copyright © 2012, Cadence Design Systems, Inc.All rights reserved.。

allegro各层的含义

allegro各层的含义【实用版】目录1.Allegro 概述2.Allegro 各层的含义3.总结正文【1.Allegro 概述】Allegro 是一款用于电子设计自动化（EDA）的软件，广泛应用于集成电路（IC）设计和 PCB（印刷电路板）设计领域。

它提供了强大的原理图编辑、PCB 布局、库管理等功能，是电子设计工程师的重要工具之一。

【2.Allegro 各层的含义】Allegro 软件的各个层次可以概括为以下几个方面：a.文件层：Allegro 中的文件主要包括原理图文件、PCB 文件、库文件等。

原理图文件包含了设计的电路原理图，PCB 文件包含了设计的印刷电路板布局，库文件则包含了各种元器件的属性和符号。

b.符号层：Allegro 中的符号是构成原理图的基本元素，包括各种元器件符号、线、角点等。

通过符号，设计人员可以搭建和编辑电路原理图。

c.原理图层：原理图层是 Allegro 软件的核心部分，包含了设计的电路原理图的详细信息。

原理图层可以通过符号层进行编辑和修改，可以实现对电路的精确控制。

d.PCB 层：Allegro 中的 PCB 层主要用于设计和编辑印刷电路板。

在这一层，设计人员可以进行布局布线，将原理图转换为实际的电路板。

e.库层：Allegro 中的库包含了各种元器件和符号的属性和信息。

库可以分为标准库和用户库，标准库包含了常用的元器件，用户库则可以自定义元器件和符号。

【3.总结】总之，Allegro 软件的各个层次涵盖了电子设计的各个方面，从原理图设计、PCB 布局到库管理等，为电子设计工程师提供了全方位的支持。

_Allegro原理图设计教程

原理图设计简介本文简要介绍了原理图的设计过程，希望能对初学者有所帮助。

一．建立一个新的工程在进行一个新的设计时，首先必须利用Project Manager 对该设计目录进行配置，使该目录具有如下的文件结构。

所用的文件库信息。

Design directory 启动Project ManagerOpen: 打开一个已有Project .New :建立一个新的Project . 点击New 如下图：cadence 将会以你所填入的project name 如：myproject 给project file 和design library 分别命名为myproject.cpm和myproject.lib点击下一步Available Library：列出所有可选择的库。

包括cadence自带库等。

Project Library：个人工程中将用到的所有库。

如myproject_lib点击下一步点击下一步点击Finish完成对设计目录的配置。

为统一原理图库，所有共享的原理图库统一放在CDMA硬件讨论园地----PCB设计专栏内。

其中：libcdma 目录为IS95项目所用的器件库。

libcdma1目录为IS95项目之后所用的器件库。

每台机器上只能存放一套共享的原理图库，一般指定放在D：盘的根目录下，即：D：\libcdma , D：\libcdma1 ...* 注意：设计开始时，应该首先将机器上的库与共享的原理图库同步。

下面介绍如何将共享库加入到自己的工程库中。

点击Setup点击Edit 编辑cds.lib文件。

添入以下语句:define libcdma d:\libcdmadefine libcdma1 d:\libcdma1则库libcdma , libcdma1被加入Availiable Library 项内。

如下图：点击Add 依次将库libcdma , libcdma1加入右边自己的工程库中。

另：可通过右端 Up, Down 键排列库的优先级。

AllegroComponentPlacement设计

I NVENTIVE Allegro Component Placement设计主要内容：一、按ROOM属性进行Placement二、原理图器件给定属性Page进行Placement三、Allegro Editor Placement replication按ROOM属性进行Placement按ROOM布局的好处就是，可以把相关电路按功能模块分区域摆放在PCB板中。

大体上可以分三个步骤完成：第一步：在原理图中添加元件的room属性第二步：在PCB板中绘制room区域第三步：按照PCB板中给定的room区域摆放元器件1、在原理图中选定元器件右键Editor properties2、Filter by下拉选Cadence Allegro，并在ROOM栏里给定属性名称。

第二步：在PCB板中绘制room区域1、把刚才修改的ROOM属性原理图保存，并重新NET IN到PCB中。

这样可以把刚才修改的属性NET IN到新板中。

2、执行PCB中Setup →Outlines →Room Outlines第二步：在PCB板中绘制room区域3、Room Outlines的一些参数设置，按住左键绘制Outline 适当外形，然后点击OK完成。

第三步：按照PCB板中给定room区域摆放元器件1、执行PlaceQuikplace2、选Place by room下拉选对应摆放区域的名称。

3、选择元器件你要摆放到的层面。

4、点击Place，完成。

原理图器件给定属性Page进行Placement原理图器件给定属性Page布局，实际上和ROOM属性布局类似，可以是分区域或是整页布局，只是该种方法需要自己给元器件给定属性，而不是原理图自带属性。

大体上也是分三个步骤完成：第一步：在原理图中添加元件的Page属性第二步：重新Net in 时重要参数设置第三步：按照Page属性摆放元器件第一步：在原理图中添加元件的Page属性1、选中原理图里需要给定属性的元器件或页。

Allegro Design Entry HDL

DATASHEETALLEGRO DESIGN ENTRY HDL 610强壮和高度集成的原理图设计Cadence Allegro设计输入HDL610，作为Allegro系统互连设计平台600系列的一个产品，提供了一个原理图设计输入和分析环境。

它的功能与扩展模拟（数字电路和模拟电路）以及电路板半途设计解决方案集成在一起。

它是作为所有与系统和高速设计流程相关的CAE要求的任务的生产率中心。

原理图设计方法已经通过若干提高生产率的特点得以简化，Allegro设计输入HDL610使得设计的每一个阶段流水线化。

Allegro系统互联设计平台ALLEGRO系统互联设计平台Cadence Allegro系统互连设计平台支持协同设计跨集成电路、封装以及印制电路板领域的高性能系统互连。

平台独特的协同设计方法优化I/O缓冲器之间和跨集成电路、封装以及印制电路板的系统互连，避免硬件返工、降低成本、缩短设计周期。

Allegro设计约束驱动的流程具有高级功能用于设计输入、信号完整性以及物理实现。

应用硅内部设计套件，集成电路公司能缩短新器件的采用时间，系统公司能够加快印制电路板的设计周期以尽快获得收益。

得到Cadence Encounter与Virtuoso平台的支持，Allegro协同设计方法确保有效的设计链协同工作。

ALLEGRO设计输入HDL610ALLEGRO设计输入HDL610(DE-HDL610)能够完成真正的同步工程设计实践从而提高了设计捕捉的生产率。

除此之外，当与约束管理器一起使用的时候，通过自动在工程师与CAD设计者之间交流高速设计要求，DE-HDL610加快了设计过程。

优点•高度集成、规则驱动的设计流程与Allegro 集成在一起DE-HDL610与Allegro 印制电路板编辑器之间的集成使得DE-HDL610成为设计者使用印制电路板编辑器进行物理设计的原理图编辑器的正确选择。

特性流程编辑器允许你配置哪个特性流程从原理图到电路板，哪个特性应当从电路板反标注回原理图。

详细了解一下Allegro原理图设计工具SDA 的十大主要功能和改变

详细了解一下Allegro原理图设计工具SDA 的十大主要功能和改变当谈到在EDA领域选择原理图设计工具时，没有人可以找到万能的解决方案。

多变的因素加之不尽相同的个人偏好，使得“最好的原理图设计工具是什么？”这个问题始终没有一个统一的答案。

目前市面上的工具基本都可以完成大多数设计工作，甚至有些工具可能看起来还极其相似。

在这种情况下，某一种产品能否脱颖而出则是非常主观的，简单易用、兼顾效率，成为了是否受用户欢迎的关键决定因素。

通常，电路/硬件设计工程师在进行产品比较时会进行以下评估和考虑：使用工具之前，我需要预先学习多少相关知识？有多少问题需要我去弄清楚？对于同样的工作，需要花费的时间和步骤是否有区别？从设计到生产流程中，和其他需要使用到的工具是否完美兼容？不同部门从工具中提取信息是否便捷？工具是否包含一个强大的库？我是否可以自由扩展可用的库？是否可以重用我的设计？工具的自动化程度有多高？综合以上考虑，Allegro System Design Authoring（SDA）是一款功能强大的企业级原理图设计工具。

不仅可以达到以上评估的要求，更可以为电路/硬件设计工程师提供灵活的选项：既有强大的Design Entry HDL功能；也有简洁的OrCAD® Capture功能。

SDA提供了一系列新功能以及更加简单、快捷的原理图设计解决方案。

接下来，让我们详细了解一下Allegro原理图设计工具SDA 的十大主要功能和改变，以及这些功能如何帮助设计工程师更好地完成工作：1简洁直观的用户界面取消了以往的菜单或命令栏、以及多个窗口来回切换的模式，相关菜单和选项会根据用户的工作任务显示出来。

SDA界面非常易于学习和使用，其“符合设计意图”的创建功能。