SiT9005数据手册-1–141MHz任意频率SiTime扩频单端振荡器

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SiT8008数据手册-SiTime低功耗1-110MHz任意频率单端有源晶振

Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated. Typical values are at 25°C and nominal supply voltage.
+50 ppm Operating Temperature Range +70 °C
Hale Waihona Puke – +85 °C Industrial Supply Voltage and Current Consumption 1.8 2.5 2.8 3.0 3.3 – 3.8 3.7 3.5 – – 2.1 1.1 1.98 2.75 3.08 3.3 3.63 3.63 4.5 4.2 4.1 4.2 4.0 4.3 2.5 V V V V V V mA mA mA mA mA A A Contact SiTime for 1.5V support
Table 2. Pin Description
Pin Symbol Output Enable 1 OE/ST/NC Standby No Connect 2 3 4 GND OUT VDD Power Output Power Functionality H[1]: specified frequency output L: output is high impedance. Only output driver is disabled. H[1]: specified frequency output L: output is low (weak pull down). Device goes to sleep mode. Supply current reduces to I_std. Any voltage between 0 and Vdd or Open[1]: Specified frequency output. Pin 1 has no function. Electrical ground Oscillator output Power supply voltage[2] OE/ST/NC

SiT3809数据手册-80-220 MHz任意频率SiTime压控振荡器,牵引范围最大±1600ppm

FeaturesApplications⏹Any frequency between 80.000001 MHz and 220 MHz with 6 decimal places of accuracy⏹Telecom clock synchronization, instrumentation⏹Low bandwidth analog PLL, jitter cleaner, clock recovery, audio ⏹100% pin-to-pin drop-in replacement to quartz-based VCXO ⏹Video, 3G/HD-SDI, FPGA, broadband and networking⏹Frequency stability as tight as ±10 ppm⏹Widest pull range options from ±25 ppm to ±1600 ppm ⏹Industrial or extended commercial temperature range⏹Superior pull range linearity of ≤1%, 10 times better than quartz ⏹LVCMOS/LVTTL compatible output⏹Four industry-standard packages: 2.5 mm x 2.0 mm (4-pin),3.2 mm x 2.5mm (4-pin), 5.0 mm x 3.2 mm (6-pin), 7.0 mm x 5.0 mm (6-pin)⏹Instant samples with Time Machine II and field programmableoscillators⏹RoHS and REACH compliant, Pb-free, Halogen-free and Antimony-freeElectrical SpecificationsTable 1. Electrical Characteristics [1, 2, 3]ParameterSymbolMin.Typ.Max.Unit ConditionFrequency Range Output Frequency Range f 80.000001–220MHz Frequency Stability and AgingFrequency StabilityF_stab-10–+10ppm Inclusive of Initial tolerance [4] at 25°C, and variation over temperature, rated supply voltage and load.-25–+25ppm -50–+50ppm AgingF_aging -5–+5ppm 10 years, 25°C Operating Temperature RangeT_use-20–+70°C Extended Commercial -40–+85°C IndustrialSupply Voltage and Current ConsumptionSupply VoltageVdd1.71 1.8 1.89V Additional supply voltages between2.5V and3.3V can be supported. Contact SiTime for additional information.2.25 2.5 2.75V 2.52 2.8 3.08V 2.973.3 3.63V Current Consumption Idd –3436mA No load condition, f = 100 MHz, Vdd = 2.5V, 2.8V or 3.3V –3033mA No load condition, f = 100 MHz, Vdd = 1.8VStandby CurrentI_std––70μA Vdd = 2.5V, 2.8V, 3.3V, ST = GND, output is Weakly Pulled Down ––10μA Vdd = 1.8V, ST = GND, output is Weakly Pulled Down VCXO CharacteristicsPull Range [5, 6]PR ±25, ±50, ±100, ±150, ±200,±400, ±800, ±1600ppm See the Absolute Pull Range and APR table on page 8Upper Control VoltageVC_U1.7––V Vdd = 1.8V, Voltage at which maximum deviation is guaranteed.2.4––V Vdd = 2.5V, Voltage at which maximum deviation is guaranteed.2.7––V Vdd = 2.8V, Voltage at which maximum deviation is guaranteed.3.2––V Vdd = 3.3V, Voltage at which maximum deviation is guaranteed.Lower Control VoltageVC_L ––0.1V Voltage at which minimum deviation is guaranteed.Control Voltage Input Impedance Z_in 100––kΩControl Voltage Input Capacitance C_in –5–pF LinearityLin –0.11%Frequency Change Polarity –Positive slope–Control Voltage Bandwidth (-3dB)V_BW–8–kHzContact SiTime for 16 kHz and other high bandwidth optionsNotes:1.All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.2.The typical value of any parameter in the Electrical Characteristics table is specified for the nominal value of the highest voltage option for that parameter and at 25°C temperature.3.All max and min specifications are guaranteed across rated voltage variations and operating temperature ranges, unless specified otherwise4.Initial tolerance is measured at Vin = Vdd/25.Absolute Pull Range (APR) is defined as the guaranteed pull range over temperature and voltage.6.APR = pull range (PR) - frequency stability (F_stab) - Aging (F_aging)Electrical Specifications (continued)Table 1. Electrical Characteristics [1, 2, 3]ParameterSymbol Min.Typ.Max.Unit ConditionLVCMOS Output CharacteristicsDuty Cycle DC 45–55% f <= 165 MHz, all Vdds. Refer to Note 11 for definition of Duty Cycle.40–60% f > 165 MHz, all Vdds. Refer to Note 11 for definition of Duty Cycle . Rise/Fall Time Tr, Tf – 1.52ns Vdd = 1.8V, 2.5V, 2.8V or 3.3V, 10% - 90% Vdd level Output High VoltageVOH90%––VddIOH = -7 mA (Vdd = 3.0V or 3.3V)IOH = -4 mA (Vdd = 2.8V or 2.5V) IOH = -2 mA (Vdd = 1.8V)Output Low Voltage VOL ––10%VddIOL = 7 mA (Vdd = 3.0V or 3.3V)IOL = 4 mA (Vdd = 2.8V or 2.5V)IOL = 2 mA (Vdd = 1.8V)Input CharacteristicsInput Pull-up Impedance Z_in –100250kΩFor the OE/ST pin for 6-pin devices Input Capacitance C_in –5–pF For the OE/ST pin for 6-pin devicesStartup and Resume TimingStartup TimeT_start ––10ms See Figure 7 for startup resume timing diagramOE Enable/Disable Time T_oe ––115ns f = 80.000001 MHz, all Vdds. For other freq, T_oe = 100 ns + 3clock periodsResume Time T_resume –710msSee Figure 8 for resume timing diagram JitterRMS Period JitterT_jitt – 1.52ps f = 156.25 MHz, Vdd = 2.5V, 2.8V or 3.3V –23ps f = 156.25 MHz, Vdd = 1.8VRMS Phase Jitter (random)T_phj–0.51ps f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHzTable 2. Pin Description. 4-Pin Configuration(For 2.5 x 2.0 mm and 3.2 x 2.5 mm packages)Pin Symbol Functionality1VIN Input 0-Vdd: produces voltage dependent frequency change2GND Power Electrical ground 3CLK Power Power supply voltage 4VDDInput PowerOscillator output power [7]Note:7. A capacitor value of 0.1 µF between VDD and GND is recommended.Table 3. Pin Description. 6-Pin Configuration(For 5.0 x 3.2 mm and 7.0 x 5.0 mm packages)Pin Symbol Functionality1VINInput 0-Vdd: produces voltage dependent frequency change 2NC/OE/ STNo ConnectH or L or Open: No effect on output frequency or other device functionsOutput Enable H or Open [8]: specified frequency output L: output is highStandbyH or Open [8]: specified frequency outputL: output is low (weak pull down)[9]. Oscillation stops 3GND Power Electrical ground 4CLK Output Oscillator output5NC No Connect H or L or Open: No effect on output frequency or other device functions6VDDPowerPower supply voltage [10]Notes:8. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 2 in the 6-pin package is not externally driven. If pin 2 needs to be left floating, use the NC option9. Typical value of the weak pull-down impedance is 5 mΩ10. A capacitor value of 0.1 µF between VDD and GND is recommended.Table 4. Absolute Maximum LimitsAttempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.ParameterMin.Max.Unit Storage Temperature -65150°C VDD-0.54V Electrostatic Discharge–2000V Soldering Temperature (follow standard Pb free soldering guidelines)–260°CTable 5. Thermal ConsiderationParameter θJA, 4 Layer Board(°C/W)θJA, 2 Layer Board(°C/W)θJC, Bottom(°C/W)70501912633050329719924322510921227252011722226Table 6. Environmental ComplianceParameterCondition/Test MethodMechanical Shock MIL-STD-883F, Method 2002Mechanical Vibration MIL-STD-883F, Method 2007Temperature Cycle JESD22, Method A104SolderabilityMIL-STD-883F, Method 2003Moisture Sensitivity LevelMSL1 @ 260°CTop ViewNotes:11.Duty Cycle is computed as Duty Cycle = TH/Period.12.SiT3809 supports the configurable duty cycle feature. For custom duty cycle at any given frequency, contact SiTime .Phase Noise PlotFigure 3. Phase NoiseTest Circuit and WaveformFigure 4. Test Circuit (4-Pin Device)Figure 5. Test Circuit (6-Pin Device)Figure 6. WaveformTiming DiagramFigure 7. Startup Timing (OE/ST Mode)Figure 8. Standby Resume Timing (ST Mode Only)Figure 9. OE Enable Timing (OE Mode Only)Figure 10. OE Disable Timing (OE Mode Only)Notes:13. SiT3809 supports “no runt” pulses and “no glitch” output during startup or resume.14. SiT3809 supports gated output which is accurate within rated frequency stability from the first cycle.Instant Samples with Time Machine and Field Programmable OscillatorsSiTime supports a field programmable version of the SiT3809MEMS VCXO for fast prototyping and real time customization of features. The field programmable devices (FP devices) are available for all four standard SiT3809 package sizes and can be configured to one’s exact specification using the Time Machine II , an USB powered MEMS oscillator programmer. Customizable Features of the SiT3809 FP Devices Include •Any frequency between 80.000001 MHz to 220 MHz •Three frequency stability options: ±10 ppm, ±25 ppm,±50 ppm•Two operating temperatures: -20 to 70°C or -40 to 85°C •Four supply voltage options: 1.8V, 2.5V, 2.8V, and 3.3V •Eight pull range options: ±25 ppm, ±50 ppm, ±100 ppm,±150 ppm, ±200 ppm, ±400 ppm, ±800 ppm, ±1600 ppmFor more information regarding SiTime’s field programmable solutions, visit /time-machine and /fp-devices .SiT3809 is typically factory-programmed per customer ordering codes for volume delivery.Note:15.Top marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device.Dimensions and PatternsOrdering InformationNote:16. Contact SiTime for different drive strength to drive multiple loads or to reduce EMI.Note:17.“–” indicates “not available.”Table 7. APR DefinitionAbsolute pull range (APR) = Norminal pull range (PR) - frequency stability (F_stab) - Aging (F_aging)Frequency StabilityNominal Pull Range± 10± 25± 50APR (PPM)± 25± 10––± 50± 35± 20–± 100± 85± 70± 45± 150± 135± 120± 95± 200± 185± 170± 145± 400± 385± 370± 345± 800± 785± 770± 745± 1600± 1585± 1570± 1545Table 8. Ordering Codes for Supported Tape & Reel Packing Method [17]Device Size 12 mm T&R (3ku)12 mm T&R (1ku)8 mm T&R (3ku)8 mm T&R 1ku)2.5 x 2.0 mm ––D E3.2 x 2.5 mm ––D E 5.0 x 3.2 mm T Y ––7.0 x 5.0 mmTY––© SiTime Corporation 2015. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liability for any loss, damage or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii)unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress.Disclaimer: SiTime makes no warranty of any kind, express or implied, with regard to this material, and specifically disclaims any and all express or implied warranties, either in fact or by operation of law, statutory or otherwise, including the implied warranties of merchantability and fitness for use or a particular purpose, and any implied warranty arising from course of dealing or usage of trade, as well as any common-law duties relating to accuracy or lack of negligence, with respect to this material, any SiTime product and any product documentation. Products sold by SiTime are not suitable or intended to be used in a life support application or component, to operate nuclear facilities, or in other mission critical applications where human life may be involved or at stake. All sales are made conditioned upon compliance with the critical uses policy set forth below.CRITICAL USE EXCLUSION POLICYBUYER AGREES NOT TO USE SITIME'S PRODUCTS FOR ANY APPLICATION OR IN ANY COMPONENTS USED IN LIFE SUPPORT DEVICES OR TO OPERATE NUCLEAR FACILITIES OR FOR USE IN OTHER MISSION-CRITICAL APPLICATIONS OR COMPONENTS WHERE HUMAN LIFE OR PROPERTY MAY BE AT STAKE.SiTime owns all rights, title and interest to the intellectual property related to SiTime's products, including any software, firmware, copyright, patent, or trademark. The sale of SiTime products does not convey or imply any license under patent or other rights. SiTime retains the copyright and trademark rights in all documents, catalogs and plans supplied pursuant to or ancillary to the sale of products or services by SiTime. Unless otherwise agreed to in writing by SiTime, any reproduction, modification, translation, compilation, or representation of this material shall be strictly prohibited.Table 9. Additional InformationDocument DescriptionDownload LinkManufacturing Notes Tape & Reel dimension, reflow profile and other manufacturing related info /component/docman/doc_download/85-manufaturing-notes-for-sitime-oscillatorsQualification Reports RoHS report, reliability reports, composition reports/support/quality-and-reliabilityPerformance ReportsAdditional performance data such as phase noise, current consumption and jitter for selected frequencies /support/performance-measurement-reportTermination Techniques Termination design recommendations /support/application-notes Layout Techniques Layout recommendations /support/application-notesVCXOSpecifications Definition of key VCXO specifications such as APR and Kv/support2/documents/AN10020_VCXO_SpecDefinitions_rev1.pdfVCXO in PLL DesignSelection of VCXO parameters and trade-offs in PLL designs/support2/documents/AN10021_VCXO_PLL_Design_Guidelines_1v0.pdfRevision HistoryTable 10. Datasheet Version and Change LogVersion Release Date Change Summary 0.61/24/2013Preliminary 1.03/18/14•Preliminary removed from title •Updated features and application •Updated electrical specifications table •Updated figure 4,•Added new 6-pin device for figure 5•Updated timing diagrams•Updated ordering information drawing •Updated APR table•Updated ordering codes for tape and reel table •Reformatted additional information table columns1.011/8/15•Corrected CLK and VDD functionality description in Table 2•Revised VIN functionality description in Table 3Supplemental Information The Supplemental Information section is not part of the datasheet and is for informational purposes only.Silicon MEMS Outperforms QuartzBest ReliabilitySilicon is inherently more reliable than quartz. Unlike quartz suppliers, SiTime has in-house MEMS and analog CMOS expertise, which allows SiTime to develop the most reliable products. Figure 1 shows a comparison with quartz technology.Why is SiTime Best in Class:•SiTime’s MEMS resonators are vacuum sealed using an advanced EpiSeal™ process, which eliminates foreign par-ticles and improves long term aging and reliability •World-class MEMS and CMOS design expertiseFigure 1. Reliability Comparison [1]Best AgingUnlike quartz, MEMS oscillators have excellent long term aging performance which is why every new SiTime product specifies 10-year aging. A comparison is shown in Figure 2.Why is SiTime Best in Class:•SiTime’s MEMS resonators are vacuum sealed using an advanced EpiSeal process, which eliminates foreign parti-cles and improves long term aging and reliability •Inherently better immunity of electrostatically driven MEMS resonatorFigure 2. Aging Comparison [2]Best Electro Magnetic Susceptibility (EMS)SiTime’s oscillators in plastic packages are up to 54 times more immune to external electromagnetic fields than quartz oscillators as shown in Figure 3.Why is SiTime Best in Class:•Internal differential architecture for best common mode noise rejection•Electrostatically driven MEMS resonator is more immune to EMSFigure 3. Electro Magnetic Susceptibility (EMS)[3]Best Power Supply Noise RejectionSiTime’s MEMS oscillators are more resilient against noise on the power supply. A comparison is shown in Figure 4.Why is SiTime Best in Class:•On-chip regulators and internal differential architecture for common mode noise rejection•Best analog CMOS design expertiseFigure 4. Power Supply Noise Rejection [4]SiTime 20X Better1.53.53.08.02468101-Year 10-YearSiTime MEMS vs. Quartz AgingSiTime MEMS OscillatorQuartz OscillatorA g i n g (±P P M )SiTime 2X Better- 39- 40- 42- 43- 45- 73Kyocera Epson TXC CW SiLabs SiTimeSiTime 54X Better1,000Power Supply Noise Frequency (kHz)SiTime SiTime 3X BetterBest Vibration RobustnessHigh-vibration environments are all around us. All electronics,from handheld devices to enterprise servers and storage systems are subject to vibration. Figure 5 shows a comparison of vibration robustness.Why is SiTime Best in Class:•The moving mass of SiTime’s MEMS resonators is up to 3000 times smaller than quartz•Center-anchored MEMS resonator is the most robust designFigure 5. Vibration Robustness [5]Best Shock RobustnessSiTime’s oscillators can withstand at least 50,000 g shock.They all maintain their electrical performance in operation during shock events. A comparison with quartz devices is shown in Figure 6.Why is SiTime Best in Class:•The moving mass of SiTime’s MEMS resonators is up to 3000 times smaller than quartz•Center-anchored MEMS resonator is the most robust designFigure 6. Shock Robustness [6]Vibration Frequency (Hz)SiTime Up to 30x Better14.312.63.92.92.50.6Kyocera Epson TXC CW SiLabs SiTimeSiTime Up to 25x BetterNotes:1.Data Source: Reliability documents of named companies.2.Data source: SiTime and quartz oscillator devices datasheets.3.Test conditions for Electro Magnetic Susceptibility (EMS):• According to IEC EN61000-4.3 (Electromagnetic compatibility standard)• Field strength: 3V/m• Radiated signal modulation: AM 1 kHz at 80% depth • Carrier frequency scan: 80 MHz – 1 GHz in 1% steps • Antenna polarization: Vertical• DUT position: Center aligned to antenna Devices used in this test:SiTime, SiT9120AC-1D2-33E156.250000 - MEMS based - 156.25 MHz Epson, EG-2102CA 156.2500M-PHPAL3 - SAW based - 156.25 MHz TXC, BB-156.250MBE-T - 3rd Overtone quartz based - 156.25 MHz Kyocera, KC7050T156.250P30E00 - SAW based - 156.25 MHzConnor Winfield (CW), P123-156.25M - 3rd overtone quartz based - 156.25 MHz SiLabs, Si590AB-BDG - 3rd overtone quartz based - 156.25 MHz 4.50 mV pk-pk Sinusoidal voltage.Devices used in this test:SiTime, SiT8208AI-33-33E-25.000000, MEMS based - 25 MHz NDK, NZ2523SB-25.6M - quartz based - 25.6 MHzKyocera, KC2016B25M0C1GE00 - quartz based - 25 MHz Epson, SG-310SCF-25M0-MB3 - quartz based - 25 MHz5.Devices used in this test: same as EMS test stated in Note 3.6. Test conditions for shock test:• MIL-STD-883F Method 2002• Condition A: half sine wave shock pulse, 500-g, 1ms• Continuous frequency measurement in 100 μs gate time for 10 seconds Devices used in this test: same as EMS test stated in Note 37.Additional data, including setup and detailed results, is available upon request to qualified customers. Please contact productsupport@ .The Smart Timing Choice ™The Smart Timing Choice ™Document Feedback FormSiTime values your input in improving our documentation. Click here for our online feedback form or fill out and email the form below to productsupport@ .1.Does the Electrical Characteristics table provide complete information?Yes NoIf No, what parameters are missing?_________________________________________________________________________________________________2. Is the organization of this document easy to follow?YesNoIf “No,” please suggest improvements that we can make:_________________________________________________________________________________________________3.Is there any application specific information that you would like to see in this document? (Check all that apply)Shock and vibration performanceOtherIf “Other,” please specify:_________________________________________________________________________________________________4. Are there any errors in this document? YesNoIf “Yes”, please specify (what and where):_________________________________________________________________________________________________5.Do you have additional recommendations for this document?_________________________________________________________________________________________________Name ________________________________________________________________________________Title________________________________________________________________________________Company _________________________________________________________________________________________Address _________________________________________________________________________________________City / State or Province / Postal Code / Country ___________________________________________________________Telephone __________________________________Application ________________________________________________________________________________________Would you like a reply?YesNoThank you for your feedback. Please click the email icon in your Adobe Reader tool bar and send to productsupport@ .Or you may use our online feedback form .。

SiTime MEMS振荡器相位噪声测量指南

SiTime MEMS振荡器相位噪声测量指南1 简介相位噪声是振荡器的基本指标之一。

经验丰富的工程师可以通过查看相位噪声图来了解有关振荡器质量以及它是否适合应用的很多信息。

RF 工程师专注于某些载波偏移频率下的相位噪声水平，以确保可以支持所需的调制方案。

设计40GbE 等高速串行链路的专业人员将带通滤波器应用于参考时钟的相位噪声，对其进行积分，并将其转换为相位抖动以预测系统的误码率。

本应用指南首先简要介绍相位噪声和相位噪声测量方法的理论概述，然后重点介绍实用的相位噪声测量建议，例如将被测信号正确连接到仪器、设置相位噪声分析仪以及选择合适的相位噪声分析仪。

设置。

本文档中的所有测量均使用Keysight E5052B 相位噪声分析仪进行，该分析仪是北美最常用的相位噪声测量仪器之一。

2 什么是相位噪声相位噪声是信号短期相位不稳定性的频域表示。

相位噪声通常被描述为单边带(SSB) 相位噪声并表示为L(f)。

相位噪声的经典定义是在载波偏移频率处测得的功率谱密度与信号总功率之比。

出于实际目的，此定义已稍作修改，以便在载波偏移频率处测量的功率谱密度以载波功率为参考，而不是以总积分信号功率为参考（图2-1）。

图2-1：经典相位噪声定义使用频谱分析仪测量相位噪声时，经典定义很方便，但它结合了幅度和相位噪声效应。

它还对具有高相位噪声的信号有限制。

经典定义通常适用于峰峰值相位偏差远小于1 弧度的信号。

它也永远不能大于0 dB，因为信号中的噪声功率不能大于信号的总功率。

最近，相位噪声被重新定义为相位波动L(f) = SΦ(f)/2 的功率谱密度的一半。

理想的正弦波可以表示为f(t) = A∙sin(ωt + φ)。

具有相位噪声的正弦波可以表示为f(t) =A∙sin(ωt + φ(t))，其中φ(t) 是相位噪声。

那么SΦ(f) 是φ(t) 的功率谱密度。

以这种方式定义时，相位噪声与幅度噪声是分开的。

它也可以大于0 dB，这意味着相位变化大于1 弧度。

Sitime产品选型手册中文2012

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压控振荡器 — VCXO
SiT3807 网络、电信、医疗、ATE、视频、xDSL、及嵌入式系统 VCXO • 可选标准频率，最大程度降低成本 • 超低相位抖动: 0.5 psrms • 最广牵引范围 • 1%牵引线性度 • 超低相位抖动: 0.5 psrms 1.5-45 (标准频点范围) 1-80 10, 25, 50 80-220 25, 50 25-200 (1%线性度) CMOS LVTTL 32 70 µA (待机) C, I 2.5x2.0 mm 3.2x2.5 mm 5.0x3.2 mm 7.0x5.0 mm
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要求低EMI的计算机设备应用应用、服务器
SiT9002
SSXO
• 扩频设计: 中心展频或向下展频
1-220
25, 50
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LVPECL LVDS HCSL CML
48-75
C, I
5.0x3.2 mm 7.0x5.0 mm
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差分压控振荡器 — VCXO
SiT3821 网络、电信、医疗、ATE、视频、xDSL、嵌入式系统 SiT3822 VCXO • 最佳稳定度 • 1%牵引线性度 • 超低相位抖动: 0.5 psrms 220-625 1-220 10, 25, 50 25-1600 (1% 牵引线性度) LVPECL LVDS 55-69 C, I 5.0x3.2 mm 7.0x5.0 mm
单端数控振荡器 — DCXO
网络及电信
SiT3907
DCXO
• 单引脚串口可编程 • 0.1% 牵引线性度动 • 超低相位抖动 0.5 psrms

Sitime MEMS硅晶振介绍

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Programmable Oscillator
MEMS Resonator
VDD
Oscillator
5MHz
Frac-N PLL
CLK
(1~800MHz)
Prog. frequency Temperature Sensor GND A/D Digital Temperature Compensation
OSC、震盪器、晶振、有源晶振
長晶
切割清洗、抛光
披银
測試校正
封装、黏贴氮气密封
老化测试
测试筛选
打标
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自日系起振芯片厂商采购起振芯片以及基座
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石英振荡器与MEMS硅晶振的区别
石英振荡器
• • • 石英切割组合简单三极管电路，易受环境影响（湿度、温度、震动等）金属封装，存在气密性问题人工切割，人工的参与质量不稳定，产能扩充困难，每一个频点需要不同的晶片
SiTime整合 8 个供应商
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SiTime MEMS时脉产品价值和优势
SiTime可编程 MEMS振荡器
交货期质量
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２-4周全自动生产，质量稳定
只需2-4周存货，节省库存成本
传统固定频率石英振荡器
８－１6周人工切割，质量受工人素质影响
进货周期长，需存货不同频点，电压，等
SiTime 全硅 MEMS 时钟方案
可靠性更高、任意频点可编程、成本更低
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SiTime 概览
• 美国硅谷VC投资Fabless IC创业公司具有业界唯一量产，Bosch验证成熟的MEMS时脉技术及最小，最薄的封装（<0.30um) 2007年三季量产，无一客户产品质量问题高性能可编程MEMS时脉产品支持低抖动，高频率，展频，低功耗，差分输出，多锁相环 (PLL)、多输出频率等功能在九大应用领域里(网通,通讯,消费,服务器等）超过800个客户,1500个计划进行测试或量产与石英振荡器比较,超短交货期(2周),24小时克制化样品,10倍的质量稳定性及无温飘的烦恼业界标准封装，焊接管脚，直接替代石英组件全球硅机电时钟领导者，年出货超越三千五百万，并以指数快速增长。

sit8103,1-110MHZ 输出,可编程振荡器

SiT8103/2是SiTime 最早推出的小体积，高性能的单端全硅MEMS 振荡器，用于对传统普通石英振荡器的升级与改造，无需改动PCB 设计，管脚100%完全兼容。

不仅可以降低产品成本，改善交货周期，而且从根本上有效解决了石英振荡器所伴随的温漂、一致性差等问题。

SiT8103支持1-110MHZ 任意频点可编程输出，且可精确到小数点后五位数。

内部具有温补功能，全温范围内无温漂，可直接替代石英，整体稳定度可提升10倍以上。

● 1-110MHZ 范围任一频点输出 ● 无温漂、低抖动● 工作电压：1.8V 、2.5V 、2.8V 、3.3V● 工作精度可达±20PPM 、±25PPM 、±30PPM 、±50PPM 、±100PPM ● 兼容LVCMOS/LVTTL 电平输出 ● 工作电流：6.1mA● 具有标准/使能两种工作模式● 同一频点多种封装：2.5×2.0，3.2×2.5，5.0×3.2，7.0×5.0mm ● 全硅半导体工艺，10倍于石英的稳定性 ● 2-4周交货周期应用：● 消费电子、视频、图像采集、机顶盒、HDTV 、DVR 、扫描仪、打印机、复印机、网络摄像头 ●USB1.1、USB2.0、SATA 、SAS 、光端机、IEEE 1394、以太网、PCI 总线等等电气特性表：工作参数标识最小典型最大单位测试说明输出频率 f 1 - 110 MHZ频率稳定性F_stab -20 - +20 PPM 此处的精度指工作频偏、温度变化、电压变化、负载变化等条件下的综合考量。

±20PPM 仅限于商规（-20--+70℃）-25 - +25 PPM -30 - +30 PPM -50- +50 PPM老化率 Ag -1.0-+1.0ppM 25℃情况下每年的老化率工作温度T_use-20 - +70 ℃ 商规 -40 - +85 ℃ 工规工作电压 Vdd1.71 1.8 1.89 V2.25 2.5 2.75 V 2.52 2.83.08 V 2.973.3 3.63 V工作电流 Idd- 6.7 7.5 mA 无负载，f=20MHZ 、Vdd=2.5V,2.8V or 3.3V -6.16.7mA无负载，f=20MHZ 、Vdd=1.8V■ 特色，优点和应用 ■ 产品简介■ 技术参数工作参数标识最小典型最大单位测试说明静态电流I_std - 2.4 4.3 μA ST=GND, Vdd=3.3V, Output is WeaklyPulled Down- 1.2 2.2 μA ST = GND, Vdd = 2.5V or 2.8V, Output isWeakly Pulled Down- 0.4 0.8 μA ST=GND, Vdd=1.8V, Output is WeaklyPulled Down占空因数DC 45 50 55 % All Vdds. F<=75MHZ40 50 60 % All Vdds. F>75MHZ上升/下降时间Tr,Tf - 1 2 ns 20%--80% Vdd=2.5v,2.8v or 3.3v15pF Load- 1.3 2.5 ns 20%--80% Vdd=1.8v 15pF Load输出高电平VOH 90% - - Vdd IOH=-4mA (Vdd=3.3v)IOH=-3mA (Vdd=2.8v or 2.5v)IOH=-2mA (Vdd=1.8v)输出低电平VOL - - 10% Vdd IOL=4mA (Vdd=3.3v)IOL=3mA (Vdd=2.8v or 2.5v)IOL=2mA (Vdd=1.8v)输出负载Output load Ld - - 15PF At maximum frequency and supplyvoltage.Contact SiTime for higheroutput load option输入高电平VIH 70% - - Vdd Pin 1,OE or ST输入低电平VIL - - 30% Vdd Pin 1,OE or ST建立时间Startup TimeT_osc - - 10 ms 如下图1所示恢复时间Resume TimeT_resume - 3.0 4 ms 如下图1所示周期抖动T_jitt - - 4.0 ps f=75MHZ,Vdd=2.5V,2.8V or 3.3V- - 6.5 ps f=75MHZ,Vdd=1.8V相位抖动T_phj - 0.6 - ps f=75MHZ,测试带宽：900Khz to 7.5MHZ,Vdd=2.5V,2.8V or 3.3V.- 0.8 - ps f=75MHZ,测试带宽：900Khz to 7.5MHZ,Vdd=1.8V.图1管脚说明：OE 模式：当1脚为高或悬空时，正常输出CLK 信号；当1脚为低时，输出禁止，呈高阻状态。

SiTime推出目前业界最小可编程扩频时钟振荡器系列产品

SiTime推出目前业界最小可编程扩频时钟振荡器系列产品
佚名
【期刊名称】《微纳电子技术》
【年(卷),期】2009(46)7
【摘要】MEMS Si计时设备领域的领衔企业SiTime最新推出了业界尺寸最小的
低周期到周期抖动宽频可编程扩频振荡器系列产品。

首款高性能产品包括
SiT9001和SiT9002。

SiT9001在业界空间占位堪称最小，适用于空间受限产品。

SIT9002是目前市场上唯一一款差分输出可编程扩频时钟振荡器。

这两款产品都
以内置MEMS谐振器作为时钟参考，而无需额外组件。

此外，两种产品都采用了SiTime成熟的MEMS技术，
【总页数】1页(P447-447)
【关键词】高性能产品;时钟振荡器;可编程;扩频;MEMS谐振器;MEMS技术;周期
抖动;差分输出
【正文语种】中文
【中图分类】TP316.7;TQ340.47
【相关文献】
1.Dallas推出扩频电阻可编程振荡器 [J],
2.赛普拉斯推出新型可编程FleXO时钟发生器系列产品 [J],
3.奥地利微电子推出具备降压功能的高效200mA DC-DC升压转换器/德州仪器推出业界最小正弦至正弦波时钟缓冲器 [J],
4.SiTime高精度MEMS振荡器颠覆全球电信与网络时钟市场 [J], 王颖
5.PMC-Sierra新推出maxSAS系列产品/Philips推出业界最小的4通道UART芯片 [J],
因版权原因，仅展示原文概要，查看原文内容请购买。

SiTime MEMS 振荡器产品数据手册说明书

SiTime introduced two families of ultra-robust AEC-Q100-qualified MEMS oscillators. The SiT2024/25 and SiT8924/25 oscillators deliver the highest performance and best robustness and are designed for ASIL (Automotive Safety Integrity Level) compliant automotive applications such as advanced driver assistance systems (ADAS), in-vehicle Ethernet, powertrain and electronic control units (ECUs).“The automotive industry is going through a massive transformation, with new features such as advanced safety and driver assistance systems, electrification, automation and real-time big data analytics. The usage of electronic components in automobiles is increasing rapidly and requires stringent levels of quality, reliability and performance,” said Piyush Sevalia, executive vice president of marketing at SiTime. “MEMS technologies are playing a significant role in this transformation. SiTime is leveraging our revolutionary silicon MEMS, advanced analog technology and standard semiconductor packaging to provide unique timing solutions that deliver the highest reliability and dynamic performance under extreme temperatures, shock and vibration.”SiTime’s new automotive product families offer a unique combination of the widest frequency range, tightest stability at ±20 ppm and the best reliability. The SiT2024/25 oscillators are optimized for under-the-hood systems such as engine control, transmission control, active suspension control, electronic steering and other ECUs. These oscillators are available in a SOT23-5 leaded package to enable visual inspection and the best solder joint reliability, especially in hot and cold environments. The SiT8924/25 oscillators, available in industry-standard QFN footprints as small as 2.0 x 1.6 mm, are ideal for camera modules and other small form factor systems.than quartz oscillators and deliver the following features and benefits.The SiT2024, SiT2025, SiT8924 and SiT8925 oscillators are in production now. Pricing information and Production Part Approval Process (PPAP) documentation, compliant with the AIAG manual, is available upon request.• AEC-Q100 qualified, Grade 1 (-40°C to +125°C), Grade 2 (-40°C to +105°C) and extended temperature range (-55°C to +125°C)3-wire version with a short-circuit protected open-drain output• SiT2024/2025: SOT23-5 leaded package for best board-level solder-joint reliability and ease-of-use in manufacturing and testLow current consumption of typ. 1.6 mA• SiT8924/8925: Five package options in industry-standard oscillator footprint• Excellent frequency stability at ±20 ppm for best timing margin• Highest reliability at over 1 billion hours MTBF (< 1 FIT)• Best shock resistance at 50,000 g• Best vibration resistance at 70 g• Lowest vibration sensitivity (g-sensitivity) at 0.1 ppb/g • Widest frequency range of 1 to 137 MHz with 6 decimal places of accuracy• Unique, programmable output drive strength for EMI reduction• Supply voltage options of 1.8 V, 2.5 to 3.3 VFEATURESHeadlightsEMI reductionSiT8924/5 & SiT2024/5AEC-Q100 MEMS Oscillator Applications & BenefitsPerformance in Presence of Vibration2016 2520 3225 5032 7050SOT23 SOIC-81. Contact SiTime for ≤±10 ppm stability options.2. Contact SiTime for AEC-Q100 compliance status.3. Contact SiTime for 95°C & 105°C products.。

压阻式硅MEMS谐振器的结构设计及工艺仿真

AbstractCompared with quartz resonators，MEMS resonator has advantages of high quality factor,low temperature drift,excellent phase noise performance,low power consumption, and especially the compatibility with the CMOS fabrication process which makes MEMS resonator promisingly to replace quartz resonator in the future integrated circuit systems.Piezoresistive silicon MEMS resonator is electrostatic actuated and the motion is detected by the piezoresistive effect of silicon.Different from other resonators such as electromagnetic and piezoelectric,it only needs silicon,the basic IC material,without needing other special pared with the capacitive MEMS resonator,it has low output resistance and can be highly integrated in the circuit.In this thesis,we analysed the piezoresistive silicon MEMS resonator with resonant frequency over hundreds of MHz by COMSOL Multiphysics simulation software. Frequency responses of the resonators with four geometrical structures were studied.The relationships between the critical dimension and the resonant characteristics such as resonator frequency,quality factor and output voltage were calibrated when scaled down with feature size of5μm,1μm,500nm,350nm,180nm,100nm and50nm,respectively.By optimizing the structure,a906.4MHz resonator with the quality factor of4352under the critical dimension of500nm and a1.3GHz resonator with the quality factor of2817under the critical dimension of350nm were obtained with great application potential.The fabrication process of the resonator was simulated by SILVACO TCAD focusing on the photolithographic and RIE etch process.Keywords:Piezoresistive Silicon MEMS resonator Finite Element Analysis Processing Simulation目录摘要 (I)Abstract (II)1绪论1.1MEMS谐振器 (1)1.2压阻式硅MEMS谐振器及其发展现状 (3)1.3本文的研究内容 (6)2压阻式硅MEMS谐振器的工作原理2.1压阻式硅MEMS谐振器工作原理 (7)2.2压阻式硅MEMS谐振器的机电耦合小信号模型 (11)2.3压阻式硅MEMS谐振器的关键参数 (12)2.4本章小结 (13)3压阻式硅MEMS谐振器的有限元模拟3.1多物理场耦合软件COMSOL M ULTIPHYSICS简介 (14)3.2压阻式硅MEMS谐振器模型 (14)3.3压阻式硅MEMS谐振器的谐振特性 (18)3.4压阻式硅MEMS谐振器的优化 (28)3.5考虑工艺误差的仿真 (30)3.6本章小结 (32)4压阻式硅MEMS谐振器的工艺仿真4.1二维工艺模拟器ATHENA简介 (33)4.2SOI衬底制备压阻式硅MEMS谐振器的工艺仿真 (34)4.3工艺模拟优化 (44)4.4本章小结 (51)5总结 (52)致谢 (53)参考文献 (54)华中科技大学硕士学位论文1绪论1.1MEMS谐振器1.1.1MEMS谐振器的发展现状MEMS谐振器是微机电系统中非常重要的元件，其作用是将微机械振动转换为电学信号，或者使用电信号对微结构进行激励，实现对频率信号的调制[1]。

SiTime温补振荡器和三级钟产品培训

5023/4Diff
1-650 MHz 0.5 PPM
9121/2Diff
1-650 MHz
5301/2
1-220 MHz Stratum 3 Diff = Differential Output

7
400-888-2483
业界最为完整的全硅MEMS时钟产品系列
智能电网(Smart Grid)
LTE Access Points 网络同步定时协议 (1588)

14
测试设备
400-888-2483
不同类型(VC)TCXO的差异
标准频率和稳定度市场均价频率 $0.5 - $2.0 10-20 标准频率 (<40 MHz) 1 – 5 PPM WiFi, 3G VoIP Industrial tester 2.5x2.0 3.2x2.5 4-pin $0.7 - $5.0 10-20 标准频率 (<40 MHz) 0.5 PPM GPS Broadcast Video RFID 2.5x2.0 3.2x2.5 4-pin 定制频率和稳定度 $5 - $20 定制频率或 40MHz以上高频 0.1 - 0.5 PPM Broadband Router Switch 7.0x5.0 14.0x9.0 4, 6-pin 三级钟 $15 - $25 1-5 个标准频率 0.1 – 0.28 PPM 4.6 PPM (20-年) 0.37 PPM (24小时 holdover) Basestation Core routers Smart Grid 7.0x5.0 14.0x9.0 4, 6, 8, 10-pin

3
400-888-2483
2011 Encore产品推出计划

SiT2025数据手册-SOT23-5封装115.20–137MHz任意频率SiTimeAECQ-100认证汽车级振荡器

Note: 5. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Table 5. Maximum Operating Junction Temperature[5]
Max Operating Temperature (ambient) 85°C 105°C 125°C Maximum Operating Junction Temperature 95°C 115°C 135°C
Parameter Mechanical Shock Mechanical Vibration Temperature Cycle Solderability Moisture Sensitivity Level Condition/Test Method MIL-STD-883F, Method 2002 MIL-STD-883F, Method 2007 JESD22, Method A104 MIL-STD-883F, Method 2003 MSL1 @ 260°C
(°C/W) 421
θJC, Bottom
(°C/W) 175
Note: 4. Refer to JESD51 for θJA and θJC definitions, and reference layout used to determine the θJA and θJC values in the above table.
Hale Waihona Puke Supply Voltage and Current Consumption

SiT5356数据手册-晶圆电子SiTime硅晶振一级代理商

SiT53561 – 60 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXODescriptionThe SiT5356 is a ±100 ppb precision MEMS Super-TCXO that is fully compliant to Telcordia GR-1244-CORE Stratum 3 oscillator specifications. Engineered for best dynamic performance, the SiT5356 is ideal for high reliability telecom, wireless and networking, industrial, precision GNSS and audio/video applications.L everaging SiTime’s unique DualMEMS™ temperature sensi ng and TurboCompensation™ technolog ies, the SiT5356 delivers the best dynamic performance for timing stability in the presence of environmental stressors due to air flow, temperature perturbation, vibration, shock, and electromagnetic interference. This device also integrates multiple on-chip regulators to filter power supply noise, eliminating the need for a dedicated external LDO.The SiT5356 offers three device configurations that can be ordered using Ordering Codes for:1)TCXO with non-pullable output frequency,2)VCTCXO allowing voltage control of outputfrequency, and3)DCTCXO, enabling digital control of output frequencyusing an I2C interface, pullable to 5 ppt (parts pertrillion) resolution.The SiT5356 can be factory programmed for any combination of frequency, stability, voltage, and pull range. Programmability enables designers to optimize clock configurations while eliminating long lead times and customization costs associated with quartz devices where each frequency is custom built.Refer to Manufacturing Guideline for proper reflow profile and PCB cleaning recommendations to ensure best performance. Features⏹Any frequency from 1 MHz to 60 MHz in 1 Hz steps ⏹Factory programmable options for low lead time⏹Best dynamic stability under airflow, thermal shock▪±100 ppb stability across temperature▪±1 ppb/ C typical frequency slope (ΔF/ΔT)▪3e-11 ADEV at 10 second averaging time⏹-40°C to +105°C operating temperature⏹No activity dips or micro jumps⏹Resistant to shock, vibration and board bending⏹On-chip regulators eliminate the need for external LDOs ⏹Digital frequency pulling (DCTCXO) via I2C▪Digital control of output frequency and pull range ▪Up to ±3200 ppm pull range▪Frequency pull resolution down to 5 ppt⏹ 2.5V, 2.8V, 3.0V and 3.3V supply voltage⏹LVCMOS or clipped sinewave output⏹RoHS and REACH compliant⏹Pb-free, Halogen-free, Antimony-free Applications⏹4G/5G radio, Small cell⏹IEEE1588 boundary and grandmaster clocks⏹Carrier-grade routers and switches⏹Synchronous Ethernet⏹Optical transport – SONET/SDH, OTN, Stratum 3⏹DOCSIS 3.x remote PHY⏹GPS disciplined oscillators⏹Precision GNSS systems⏹Test and measurementBlock DiagramFigure 1. SiT5356 Block Diagram 5.0 x 3.2 mm2 Package PinoutOE / VC / NC12345678910SCL / NCNCGNDNCNCVDDCLKA0 / NCSDA / NCFigure 2. Pin Assignments (Top view) (Refer to Table 13for Pin Descriptions)Ordering InformationThe following part number guide is for reference only. To customize and build an exact part number, use theSiTime Part Number Generator. To validate the part number, use the SiTime Part Number Decoder.Notes:1. “-“ corresponds to the default rise/fall time for LVCMOS output as specified in Table 1 (Electrical Characteristics). Contact SiTime for other rise/fall time optionsfor best EMI.2. Bulk is available for sampling onlyTABLE OF CONTENTSDescription (1)Features (1)Applications (1)Block Diagram (1)5.0 x 3.2 mm2 Package Pinout (1)Ordering Information (2)Electrical Characteristics (4)Device Configurations and Pin-outs (10)Pin-out Top Views (10)Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs (11)Waveforms (13)Timing Diagrams (14)Typical Performance Plots (15)Architecture Overview (19)Frequency Stability (19)Output Frequency and Format (19)Output Frequency Tuning (19)Pin 1 Configuration (OE, VC, or NC) (20)Device Configurations (20)TCXO Configuration (20)VCTCXO Configuration (21)DCTCXO Configuration (22)VCTCXO-Specific Design Considerations (23)Linearity (23)Control Voltage Bandwidth (23)FV Characteristic Slope K V (23)Pull Range, Absolute Pull Range (24)DCTCXO-Specific Design Considerations (25)Pull Range and Absolute Pull Range (25)Output Frequency (26)I2C Control Registers (28)Register Descriptions (28)Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) (28)Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) (29)Register Address: 0x02. DIGITAL PULL RANGE CONTROL[14] (30)Serial Interface Configuration Description (31)Serial Signal Format (31)Parallel Signal Format (32)Parallel Data Format (32)I2C Timing Specification (34)I2C Device Address Modes (35)Schematic Example (36)Dimensions and Patterns (37)Layout Guidelines (38)Manufacturing Guidelines (38)Electrical CharacteristicsAll Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated. Typical values are at 25°C and 3.3V Vdd.Table 1. Output CharacteristicsTable 1. Output Characteristics (continued)Table 2. DC CharacteristicsTable 3. Input CharacteristicsNote:3. APR = PR – initial tolerance – 20-year aging – frequency stability over temperature. Refer to Table 17 for APR with respect to other pull range options.Table 5. Jitter & Phase Noise – Clipped Sinewave, -40 to 85 °CTable 7. Jitter & Phase Noise – Clipped Sinewave, -40 to 105 °CTable 8. Absolute Maximum LimitsAttempted operation outside the absolute maximum ratings may cause permanent damage to the part.Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.Note:4. Exceeding this temperature for an extended period of time may damage the device.Table 9. Thermal Considerations[5]Note:5. Measured in still air.Table 10. Maximum Operating Junction Temperature[6]Note:6. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.Table 11. Environmental ComplianceDevice Configurations and Pin-outsTable 12. Device ConfigurationsPin-out Top ViewsOE/NC12345678910NC NC GNDNC NC VDD CLKNCNCFigure 3. TCXOVC 12345678910NC NC GNDNC NC VDD CLKNCNCFigure 4. VCTCXOOE / NC 12345678910 SCL NC GNDNC NC VDD CLKA0 / NCSDAFigure 5. DCTCXOTable 13. Pin DescriptionNotes:7. In OE mode for noisy environments, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option.8. A 0.1 μF capacitor in parallel with a 10 μF capacitor are required between Vdd and GND. The 0.1 μF capacitor is recommended to place close to the device, and place the 10 μF capacitor less than 2 inches away.9. All NC pins can be left floating and do not need to be soldered down.Test Circuit Diagrams for LVCMOS and Clipped Sinewave OutputsFigure 6. LVCMOS Test Circuit (OE Function)Figure 7. Clipped Sinewave Test Circuit (OE Function)for AC and DC MeasurementsVC FunctionFigure 8. LVCMOS Test Circuit (VC Function)VC FunctionFigure 9. Clipped Sinewave Test Circuit (VC Function)for AC and DC MeasurementsNC FunctionFigure 10. LVCMOS Test Circuit (NC Function)NC FunctionFigure 11. Clipped Sinewave Test Circuit (NC Function)for AC and DC MeasurementsTest Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs (continued)FunctionFigure 12. LVCMOS Test Circuit (I2C Control), DCTCXO modeFunction2C Control), DCTCXO mode for AC and DC MeasurementsFigure 13. Clipped Sinewave Test Circuit (IFigure 14. Clipped Sinewave Test Circuit for Phase Noise Measurements, Applies to All Configurations(NC Function shown for example only)Note:10.SDA is open-drain and may require pull-up resistor if not present in I2C test setup.Waveforms90 % Vdd 50 % Vdd10 % VddFigure 15. LVCMOS Waveform Diagram[11]Figure 16. Clipped Sinewave Waveform Diagram[11]Note:11.Duty Cycle is computed as Duty Cycle = TH/Period.Timing DiagramsVdd Pin CLK OutputT_start: Time to start from power-offFigure 17. Startup Timing T_oe: Time to re-enable the clock outputFigure 18. OE Enable Timing (OE Mode Only)Typical Performance PlotsFigure 19. ADEV (±0.1 ppm)Figure 20. TDEV (0.1 Hz loop bandwidth, ±0.1 ppm)Figure 21. MTIE (0.1 Hz loop bandwidth, ±0.1 ppm)Figure 22. Frequency vs Temperature (±0.1 ppm), 105°CFigure 23. Freq. vs. Temp. Slope (ΔF/ΔT), ±0.1 ppm deviceFigure 24. VCTCXO frequency pull characteristicFigure 25. 1-day aging rate (to 62 days), ±0.1 ppm deviceFigure 26. Drift over 30 days relative to the first readingTypical Performance Plots (continued)Figure 27. Load sensitivity (±0.1 ppm )Figure 28. VDD sensitivity (±0.1 ppm)Figure 31. IDD TCXO (LVCMOS)Figure 32. IDD VCTCXO (LVCMOS)Figure 33. T_phj, RMS Random, (DC)TCXO (LVCMOS)Figure 34. Period Jitter, RMS (LVCMOS)Figure 35. IDD DCTCXO (LVCMOS)Figure 36. T_phj, RMS Random, VCTCXO (LVCMOS)Figure 37. DCTCXO frequency pull characteristicFigure 38. Rise Time (Clipped Sinewave)Figure 39. IDD TCXO (Clipped Sinewave)Figure 40. IDD VCTCXO (Clipped Sinewave)Figure 41. T_phj, RMS Random, (DC)TCXO (Clipped Sine)Figure 42. IDD DCTCXO (Clipped Sinewave)Figure 43. T_phj, RMS Random, VCTCXO (Clipped Sine)Figure 44. Duty Cycle (Clipped Sinewave)Architecture OverviewBased on SiTime’s innovative Elite Platform™, the SiT5356 delivers exceptional dynamic performance, i.e. resilience to environmental stressors such as shock, vibration, and fast temperature transients. Underpinning the Elite platform are SiTime’s unique DualMEMS™temperature sensing architecture and TurboCompensation™ technologies. DualMEMS is a noiseless temperature compensation scheme. It consists of two MEMS resonators fabricated on the same die substrate. The TempFlat™resonator is designed with a flat frequency characteristic over temperature whereas the temperature sensing resonator is by design sensitive to temperature changes. The ratio of frequencies between these two resonators provides an accurate reading of the resonator temperature with 20 µK resolution.By placing the two MEMS resonators on the same die, this temperature sensing scheme eliminates any thermal lag and gradients between resonator and temperature sensor, thereby overcoming an inherent weakness of legacy quartz TCXOs.The DualMEMS temperature sensor drives a state-of-the-art CMOS temperature compensation circuit. The TurboCompensation design, with >100 Hz compensation bandwidth, achieves a dynamic frequency stability that is far superior to any quartz TCXO. The digital temperature compensation enables additional optimization of frequency stability and frequency slope over temperature within any chosen temperature range for a given system design.Figure 45. Elite ArchitectureThe Elite platform also incorporates a high resolution, low noise frequency synthesizer along with the industry standard I2C bus. This unique combination enables system designers to digitally control the output frequency in steps as low as 5 ppt and over a wide range up to ±3200 ppm. For more information regarding the Elite platform and its benefits please visit:⏹SiTime's breakthroughs section⏹TechPaper:DualMEMS Temperature Sensing Technology ⏹TechPaper:DualMEMS Resonator TDC Functional OverviewThe SiT5356 is designed for maximum flexibility with an array of factory programmable options, enabling system designers to configure this precision device for optimal performance in a given application.Frequency StabilityThe SiT5356 comes in two factory-trimmed stability grades that are optimized for different applications. Both Stratum 3+ and Stratum 3 devices are compliant with Stratum 3 stability of ±4.6 ppm over 20 years.Table 14. Stability Grades vs. Ordering Codes⏹Stratum 3+ grade with ΔF/ΔT of ±3.5 ppb/︒C isengineered to provide significantly better performancethan legacy quartz TCXOs in time and phasesynchronization applications such as IEEE1588, smallcells, and 5G C-RAN (cloud RAN).⏹Stratum 3 grade is designed to replace classicStratum 3 TCXOs in applications such as SyncE withbetter dynamic performance and shorter lead time. Output Frequency and FormatThe SiT5356 can be factory programmed for an outputfrequency without sacrificing lead time or incurring an upfront customization cost typically associated with custom-frequency quartz TCXOs.The device supports both LVCMOS and clipped sinewave output. Ordering codes for the output format are shown below: Table 15. Output Formats vs. Ordering CodesOutput Frequency TuningIn addition to the non-pullable TCXO, the SiT5356 can also support output frequency tuning through either an analog control voltage (VCTCXO), or I2C interface (DCTCXO). The I2C interface enables 16 factory programmed pull-range options from ±6.25 ppm to ±3200 ppm. The pull range can also be reprogrammed via I2C to any supported pull-range value.Refer to Device Configuration section for details.Pin 1 Configuration (OE, VC, or NC)Pin 1 of the SiT5356 can be factory programmed to support three modes: Output Enable (OE), Voltage Control (VC), or No Connect (NC).Table 16. Pin Configuration OptionsWhen pin 1 is configured as OE pin, the device output is guaranteed to operate in one of the following two states:⏹Clock output with the frequency specified in the partnumber when Pin 1 is pulled to logic high⏹Hi-Z mode with weak pull down when pin 1 is pulled tologic low.When pin 1 is configured as NC, the device is guaranteed to output the frequency specified in the part number at all times, regardless of the logic level on pin 1.In the VCTCXO configuration, the user can fine-tune the output frequency from the nominal frequency specified in the part number by varying the pin 1 voltage. The guaranteed allowable variation of the output frequency is specified as pull range. A VCTCXO part number must contain a valid pull-range ordering code. Device ConfigurationsThe SiT5356 supports 3 device configurations –TCXO,VCTCXO, and DCTCXO. The TCXO and VCTCXO options are directly compatible with the quartz TCXO and VCTCXO. The DCTCXO configuration provides performance enhancement by eliminating VCTCXO’s sensitivity to control voltage noise with an I2C digital interface for frequency tuning.Figure 46. Block Diagram – TCXOTCXO ConfigurationThe TCXO configuration generates a fixed frequency output, as shown in Figure 46. The frequency is specified by the user in the frequency field of the device ordering code and then factory programmed. Other factory programmable options include supply voltage, output types (LVCMOS or clipped sinewave), and pin 1 functionality (OE or NC).Refer to the Ordering Information section at the end of the datasheet for a list of all ordering options.A VCTCXO, shown in Figure 47, is a frequency control device whose output frequency is an approximately linear function of control voltage applied to the voltage control pin. VCTCXOs have a number of use cases including the VCO portion of a jitter attenuation/jitter cleaner PLL Loop.The SiT5356 achieves a 10x better pull range linearity of <0.5% via a high-resolution fractional PLL compared with 5% to 10% typical of quartz VCTCXOs that rely on pulling a resonator. By contrast, quartz-based VCTCXOs change output frequency by varying the capacitive load of a crystal resonator using varactor diodes, which results in poor linearity.Figure 47. Block Diagram – VCTCXO Note that the output frequency of the VCTCXO is proportional to the analog control voltage applied to pin 1. Because this control signal is analog and directly controls the output frequency, care must be taken to minimize noise on this pin.The nominal output frequency is factory programmed per the customer’s request to 6 digits of precision and is defined as the output frequency when the control voltage equals Vdd/2. The maximum output frequency variation from this nominal value is set by the pull range, which is also factory programmed to the customer’s desired value and specified by the ordering code. The Ordering Information section shows all ordering options and associated ordering codes. Refer to VCTCXO-Specific Design Considerations for more information on critical VCTCXO parameters including pull range linearity, absolute pull range,control voltage bandwidth, and Kv.The SiT5356 offers digital control of the output frequency, as shown in Figure 48. The output frequency is controlled by writing frequency control words over the I2C interface. There are several advantages of DCTCXOs relative to VCTCXOs:1)Frequency control resolution as low as 5 ppt. Thishigh resolution minimizes accumulated time error insynchronization applications.2)Lower system cost – A VCTCXO may need a Digital toAnalog Converter (DAC) to drive the control voltageinput. In a DCTXCO, the frequency control is achieveddigitally by register writes to the control registers viaI2C, thereby eliminating the need for a DAC.3)Better noise immunity –The analog signal used todrive the voltage control pin of a VCTCXO can besensitive to noise, and the trace over which the signalis routed can be susceptible to noise coupling from thesystem. The DCTCXO does not suffer from analognoise coupling since the frequency control isperformed digitally through I2C.Figure 48. Block Diagram4)No frequency-pull non-linearity – The frequency pullingis achieved via fractional feedback divider of the PLL, eliminating any pull non-linearity concerns typical of quartz-based VCTCXOs. This improves dynamic performance in closed-loop applications.5)Programmable wide pull range –The DCTCXOpulling mechanism is via the fractional feedback divider and is therefore not constrained by resonator pullability as in quartz-based solutions. The SiT5356 offers 16 frequency pull-range options from ±6.25ppm to ±3200ppm, providing system designers great flexibility.Refer to DCTCXO-Specific Design Considerations for more information on critical DCTCXO parameters including pull range, absolute pull range, frequency output, and I2Ccontrol registers.VCTCXO-Specific Design ConsiderationsLinearityIn any VCTCXO, there will be some deviation of the frequency-voltage (FV) characteristic from an ideal straight line. Linearity is the ratio of this maximum deviation to the total pull range, expressed as a percentage. Figure 49 below shows the typical pull linearity of a SiTime VCTCXO. The linearity is excellent (1% maximum) relative to most quartz offerings because the frequency pulling is achieved with a PLL rather than varactor diodes.Figure 49. Typical SiTime VCTCXO LinearityControl Voltage BandwidthControl voltage b andwidth, sometimes called “modulation r ate” or “modulation b andwidth”, indicates how fast a VCO can respond to voltage changes at its input. The ratio of the output frequency variation to the input voltage variation, previously denoted by K V, has a low-pass characteristic in most VCTCXOs. The control voltage bandwidth equals the modulating frequency where the output frequency deviation equals 0.707 (e.g. -3 dB) of its DC value, for DC inputs swept in the same voltage range.For example, a part with a ±6.25 ppm pull range and a 0-3V control voltage can be regarded as having an average KV of 4.17 ppm/V (12.5 ppm/3V = 4.17 ppm/V). Applying an input of 1.5V DC ± 0.5V (1.0 V to 2.0V) causes an output frequency change of 4.17 ppm (±2.08 ppm). If the control voltage bandwidth is specified as 10 kHz, the peak-to-peak value of the output frequency change will be reduced to 4.33 ppm/√2 or 2.95 ppm, as the frequency of the control voltage change is increased to 10 kHz.FV Characteristic Slope K VThe slope of the FV characteristic is a critical design parameter in many low bandwidth PLL applications. The slope is the derivative of the FV characteristic –the deviation of frequency divided by the control voltage change needed to produce that frequency deviation, over a small voltage span, as shown below:inoutV VfK∆∆=It is typically expressed in kHz/Volt, MHz/Volt, ppm/Volt, or similar units. This s lope is usually called “K V” based on terminology used in PLL designs.The extreme linear characteristic of the SiTime SiT5356 VCTCXO family means that there is very little K V variation across the whole input voltage range (typically <1%), significantly reducing the design burden on the PLL designer. Figure50below illustrates the typical K V variation.Figure 50. Typical SiTime K V VariationPull Range, Absolute Pull RangePull range (PR) is the amount of frequency deviation that will result from changing the control voltage over its maximum range under nominal conditions.Absolute pull range (APR) is the guaranteed controllable frequency range over all environmental and aging conditions. Effectively, it is the amount of pull range remaining after taking into account frequency stability, tolerances over variables such as temperature, power supply voltage, and aging, i.e.:agingstability F F PR APR --=where stability F is the device frequency stability due to initial tolerance and variations on temperature, power supply, and load.Figure 51 shows a typical SiTime VCTCXO FV characteristic. The FV characteristic varies with conditions, so that the frequency output at a given input voltage can vary by as much as the specified frequency stability of the VCTCXO. For such VCTCXOs, the frequency stability and APR are independent of each other. This allows very wide range of pull options without compromising frequency stability.Figure 51. Typical SiTime VCTCXO FV Characteristic The upper and lower control voltages are the specified limits of the input voltage range as shown in Figure 51 above. Applying voltages beyond the upper and lower voltages do not result in noticeable changes of output frequency. In other words, the FV characteristic of the VCTCXO saturates beyond these voltages. Figures 1 and 2 show these voltages as Lower Control Voltage (VC_L) and Upper Control Voltage (VC_U).Table 17 below shows the pull range and corresponding APR values for each of the frequency vs. temperature ordering options.Table 17. VCTCXO Pull Range, APR Options [12] Typical unless specified otherwise. Pull range (PR) is ±6.25 ppm.Notes:12.APR includes initial tolerance, frequency stability vs. temperature, and the corresponding 20-year aging.DCTCXO-Specific Design ConsiderationsPull Range and Absolute Pull RangePull range and absolute pull range are described in theprevious section. Table 18 below shows the pull range andcorresponding APR values for each of the frequency vs.temperature ordering options.Table 18. APR Options[13]Notes:13.APR includes initial tolerance, frequency stability vs. temperature, and the corresponding 20-year aging.Output FrequencyThe device powers up at the nominal operating frequency and pull range specified by the ordering code. After power-up both pull range and output frequency can be controlled via I2C writes to the respective control registers. The maximum output frequency change is constrained by the pull range limits.The pull range is specified by the value loaded in the digital pull-range control register. The 16 pull range choices are specified in the control register and range from ±6.25ppm to ±3200ppm.Table 19 below shows the frequency resolution versus pull range programmed valueTable 19. Frequency Resolution versus Pull RangeThe ppm frequency offset is specified by the 26 bit DCXO frequency control register in two’s complement format as described in the I2C Register Descriptions. The power up default value is 00000000000000000000000000b which sets the output frequency at its nominal value (0 ppm). To change the output frequency, a frequency control word is written to 0x00[15:0] (Least Significant Word) and 0x01[9:0] (Most Significant Word). The LSW value should be written first followed by the MSW value; the frequency change is initiated after the MSW value is written.Figure 52. Pull Range and Frequency Control WordFigure 52shows how the two’s complement signed value of the frequency control word sets the output frequency within the ppm pull range set by 0x02:[3:0]. This example shows use of the ±200 ppm pull range. Therefore, to set the desired output frequency, one just needs to calculate the fraction of full scale value ppm, con vert to two’s complement binary, and then write these values to the frequency control registers.The following formula generates the control word value: Control word value = RND((225-1) × ppm shift from nominal/pull range), where RND is the rounding function which rounds the number to the nearest whole number. Two examples follow, assuming a ±200 ppm pull range: Example 1:⏹Default Output Frequency = 19.2 MHz⏹Desired Output Frequency = 19.201728 MHz (+90 ppm) 225-1 corresponds to +200 ppm, and the fractional value required for +90 ppm can be calculated as follows.⏹90 ppm / 200 ppm × (225-1) = 15,099,493.95.Rounding to the nearest whole number yields 15,099,494 and converting to two’s complement gives a binary value of 111001100110011001100110, or E66666 in hex.Example 2:⏹Default Output Frequency = 10 MHz⏹Desired Output Frequency = 9.998 MHz (-50 ppm) Following the formula shown above,⏹(-50 ppm / 200 ppm) × (225-1) = -8,388,607.75. Rounding this to the nearest whole number results in-8,388,608.Converting this to two’s complement binary results in 11100000000000000000000000, or 3800000 in hex. To summarize, the procedure for calculating the frequency control word associated with a given ppm offset is as follows:1)Calculate the fraction of the half-pull range needed.For example, if the total pull range is set for ±100 ppmand a +20 ppm shift from the nominal frequency isneeded, this fraction is 20 ppm/100 ppm = 0.22)Multiply this fraction by the full-half scale word value,225-1 = 33,554,431, round to the nearest wholenumber, and convert the result to two’s complementbinary. Following the +20ppm example, this value is0.2 × 33,554,431 = 6,710,886.2 and rounded to6,710,886.3)Write the two’s complement binary value starting withthe Least Significant Word (LSW) 0x00[16:0],followed by the Most Significant Word (MSW),0x01[9:0]. If the user desires that the output remainsenabled while changing the frequency, a 1 must alsobe written to the OE control bit 0x01[10] if the devicehas software OE Control Enabled.It is important to note that the maximum Digital Control update rate is 38 kHz regardless of I2C bus speed.I2C Control RegistersThe SiT5356 enables control of frequency pull range, frequency pull value, and Output Enable via I2C writes to the control registers. Table 20 below shows the register map summary, and detailed register descriptions follow.Table 20. Register Map SummaryRegister DescriptionsRegister Address: 0x00. Digital Frequency Control Least Significant Word (LSW)。

PCM-9005用户手册中文版V22

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第一章产品概要感谢阁下选用深圳市迈控科技的PCM-9005模块！PCM-9005用于将TTL信号转换成LVDS信号，它支持18/24位数据宽度的LVDS真彩液晶屏，支持20~65MHz的移位时钟信号。

PCM-9005将18/24位CMOS/TTL数据信号转换成LVDS 信号流即3/4路数据信号,1路时钟信号。

在传输时钟频率达到65MHz时，R-G-B数据信号及3个时序控制信号FPLIN，FPFRAME，DRDY通过LVDS通道以高达455Mbps的速率进行传送。

SiT8002-SITIME规格书

Features•Operating temperature range:•Automotive, -40°C to +125°C•Mechanically robust:•Shock, 50 KG•Vibration, 70 G•Wide frequency range•1 MHz to 125 MHz•Low frequency tolerance•±100 ppm or ±200 ppm or ±500•Operating voltage•1.8V or 2.5 or 3.3 V•Small footprint•2.5 x 2.0 x 0.85 mm•3.2 x 2.5 x 0.85 mm•5.0 x 3.2 x 0.85 mm•7.0 x 5.0 x 0.85 mm•All packages are Pb-free and ROHs compliant (QFN SMD)•Ultra-reliable start up and greater immunity from interfer-ence•High drive option: 30pF load (contact factory)Benefits•No crystal or capacitors required•Eliminates crystal qualification time•50% + board saving space•Most cost effective than Quartz oscillators, Quartz crystals and Clock ICs.•completely quartz-freeApplications•Automotive•Industrial•Automation•Space•SatellitePin DescriptionPin Pin Description1ST/OE Standby/ Output Enable2GND Connect to Ground3OUT 1 to 125 MHz Programmed Clock output 4VDD Connect to 1.8V or 2.5V or 3.3V Pin1Pin #1 FunctionalityOEH or Open; specified frequency outputL: output is high impedanceSTH or Open; specified frequency outputL: output is low level (weak pull down) oscillation stopsDescriptionThe SiT8002AA oscillator family is composed of the world’s smallest, high-performance programmable oscillators. The SiT8002AA is suitable for use in clock generation for automotive, industrial, and space/Satellite applications.MEMS resonators are 1000x smaller by volume than quartz resonators and are built in high volume CMOS fabs instead of small custom manufacturing facilities. Due to their small size,massive lot sizes, and simpler manufacturing processes MEMS oscillators are inherently more reliable, have more consistent performance and are always in stock.The SiT8002AA, by eliminating the quartz crystals, has improved immunity to the environmental effects of vibration,shock, strain, and humidity.Absolute Maximum RatingsAttempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications not absolute maximum ratings.Notes:1.The2.5V device can operate from 2.25V to3.63V with higher output drive, however, the data sheet parameters cannot be guaranteed. Please contact factory for this option.2.The output driver strenght can be programmed to drive up to 30pF load. Please contact factory for this option.Ab solute Maximum TableParameterMin.Max.Unit Storage Temperature -65150°C VDD-0.5+3.65V Electrostatic Discharge6000V Theta JA ( with copper plane on VDD and GND)–75°C/W Theta JC (with PCB traces of 0.010 inch to all pins)–24°C/W Soldering Temperature (follow standard Pb free soldering guidelines)260°C Number of Program Writes1NA Program Retention over -40 to 125C, Process, VDD (0 to 3.6V)1,000+yearsOperating ConditionsParameterMin.Typ.Max.Unit Supply Voltages, VDD [1]2.973.3 3.63V 2.25 2.5 2.75V 1.71.8 1.9V Automotive OperatingTemperature -40-125°C Maximum Load Capacitance [2]--15pF VDD Ramp Time-200msEnvironmental ComplianceParameter Condition/Test MethodMechanical Shock MIL-STD-883F, Method 2002, 50 KG Mechanical Vibration MIL-STD-883F, Method 2007, 70 G Temperature Cycle JESD22, Method A104SolderabilityMIL-STD-883F, Method 2003Moisture Sensibility LevelMSL1@VDD = 3.3V ±10%, -40 to 125°CParameter Condition Min.Typ.Max.Unit Voltage Output High IOH = -20 mA 70--%Vdd Voltage Output Low IOL = 20 mA --30%Vdd Input Voltage High Pin 170--%Vdd Input Voltage Low Pin 1 --30%Vdd Operating Current Output frequency = 65 MHz, 15 pF load--30mA Standby Current Output is weakly pulled down, ST = GND-3080uA Power Up Time Time from minimum power supply voltage-1250ms@VDD = 2.5V ±10%, -40 to 125°CParameter Condition Min.Typ.Max.Unit Voltage Output High IOH = -15 mA 70--%Vdd Voltage Output Low IOL = 15 mA --30%Vdd Input Voltage High Pin 170--%Vdd Input Voltage Low Pin 1 --30%Vdd Operating Current Output frequency = 65 MHz, 15 pF load--30mA Standby Current Output is weakly pulled down, ST = GND-3080uA Power Up Time Time from minimum power supply voltage-1250ms@VDD = 1.8V ±5%, -40 to 125°CParameter Condition Min.Typ.Max.Unit Voltage Output High IOH = -10 mA 70--%Vdd Voltage Output Low IOL = 10 mA --30%Vdd Input Voltage High Pin 170--%Vdd Input Voltage Low Pin 1 --30%Vdd Operating Current Output frequency = 65 MHz, 15 pF load--25mA Standby Current Output is weakly pulled down, ST = GND-3080uA Power Up Time Time from minimum power supply voltage-1250ms@VDD = 3.3V ±10%, -40 to 125°CParameter Condition Min.Typ.Max.Unit Clock Output Frequency1-125MHzFrequency Tolerance Initial tolerance, operating temperature, ratedpower supply voltage change, load change,aging,shock and vibration -100-+100ppm -200-+200ppm -500-+500ppmClock Output Duty Cycle Output frequency= 1 MHz to 125 MHz45-55% Clock Output Rise Time15 pF Load, 20% to 80% VDD- 1.03ns Clock Output Fall Time15 pF Load, 80% to 20% VDD- 1.03ns Pk-pk Period Jitter Output frequency = 24 MHz-100125psOutput frequency = 100 MHz-6075ps @VDD = 2.5V ±10%, -40 to 125°CParameter Condition Min.Typ.Max.Unit Clock Output Frequency1-125MHzFrequency Tolerance Initial tolerance, operating temperature, ratedpower supply voltage change, load change,aging,shock and vibration -100-+100ppm -200-+200ppm -500-+500ppmClock Output Duty Cycle Output frequency= 1MHz to 125MHz45-55% Clock Output Rise Time15 pF Load, 20% to 80% VDD- 1.03ns Clock Output Fall Time15 pF Load, 80% to 20% VDD- 1.03ns Pk-pk Period Jitter Output frequency = 24 MHz-130150psOutput frequency = 100 MHz-6075ps@VDD = 1.8V ±5%, -40 to 125°CParameter Condition Min.Typ.Max.Unit Clock Output Frequency1-125MHzFrequency Tolerance Initial tolerance, operating temperature, ratedpower supply voltage change, load change,aging,shock and vibration -50-+50ppm -100-+100ppmClock Output Duty Cycle Output frequency= 1 MHz to 65MHz45-55%Output frequency= 65 MHz to 125MHz40-60% Clock Output Rise Time15 pF Load, 20% to 80% VDD- 1.03ns Clock Output Fall Time15 pF Load, 80% to 20% VDD- 1.03ns Pk-pk Period Jitter Output frequency = 24 MHz-185225psOutput frequency = 100 MHz-100125psOrdering InformationPackage Information[3]Dimension (mm) Land Pattern (recommneded) (mm)2.5 x 2.0 x 0.85mmNote:3.xxxx top marking denotes manufacturing lot number..Package Information (continued)[3]Dimension (mm) Land Pattern (recommneded) (mm)3.2 x 2.5 x 0.85mm5.0 x 3.2 x 0.85mm7.0 x 5.0 x 0.85mma Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress.Disclaimer: SiTime makes no warranty of any kind, express or implied, with regard to this material, and specifically disclaims any and all express or implied warranties, either in fact or by operation of law, statutory or otherwise, including the implied warranties of merchantability and fitness for use or a particular purpose, and any implied warranty arising from course of dealing or usage of trade, as well as any common-law duties relating to accuracy or lack of negligence, with respect to this material, any sitime product and any product documentation. products sold by sitme are not suitable or intended to be used in a life support application or component, to operate nuclear facilities, or in other mission critical applications where human life may be involved or at stake. all sales are made conditioned upon compliance with the critical uses policy set forth below.CRITICAL USE EXCLUSION POLICYBUYER AGREES NOT TO USE SITIME'S PRODUCTS FOR ANY APPLICATION OR IN ANY COMPONENTS USED IN LIFE SUPPORT DEVICES OR TO OPERATE NUCLEAR FACILITIES OR FOR USE IN OTHER MISSION-CRITICAL APPLICATIONS OR COMPONENTS WHERE HUMAN LIFE OR PROPERTY MAY BE AT STAKE.SiTime owns all rights, title and interest to the intellectual property related to SiTime's products, including any software, firmware, copyright, patent, or trademark. The sale of SiTime products does not convey or imply any license under patent or other rights. SiTime retains the copyright and trademark rights in all documents, catalogs and plans supplied pursuant to or ancillary to the sale of products or services by SiTime. Unless otherwise agreed to in writing by SiTime, any reproduction, modification, translation, compilation, or representation of this material shall be strictly prohibited.。

SiT9002数据手册-1–220MHz任意频率SiTime差分扩频晶振

Features•World’s first differential spread spectrum oscillator •Extremely low cycle-cycle jitter• As low as10 ps (typical)•Wide frequency range•1 MHz to 220 MHz•220 MHz to 800 MHz (contact SiTime)•Eight spread selections (31.5 KHz modulation rate)•Center Spread: ±0.25%, ±0.5%, ±1.0%, ±2.0%•Down Spread: -0.5%, -1.0%, -2.0%, -4.0%•For -0.25% and ±0.125% contact SiTime •Low frequency stability (Spread = OFF)•±25 ppm or ±50 ppm •Operating voltage•1.8V or 2.5 or 3.3 V •Operating temperature range:•Industrial, -40°C to 85°C•Extended Commercial, -20°C to 70°C •Small footprint•5.0 x 3.2 x 0.75 mm •7.0 x 5.0 x 0.90 mm •Pb-free and RoHS compliant•Ultra-reliable start up and greater immunity from inter-ferenceBenefits•Services most PC peripherals, networking, and consumer applications•Provides wide range of spread percentage for maximum electromagnetic interference (EMI) reduction•Up to -17 dB reduction on third homonic and -12dB on the fundamental•Fast time to market due to not needing to redesign the PCB for EMI reduction•Factory programmable for ultra-fast lead time •No crystal or load capacitors required •Eliminates crystal qualification time •50%+ board saving space •Completely quartz-freeApplications•PCI-Express •USB 3.0•Fully Buffered DIMM •Blade Server •Router •System Clock•Networking and Computing •Automotive •IndustrialBlock Diagram PinoutPin DescriptionPin Pin Description1 ST/OE/SD Input Standby or Output Enable pin for OUT+ and OUT-.OE:When High or Open : OUT+ and OUT- = activeWhen Low : OUT+ and OUT- = High Impedance stateST:When High or Open : OUT+ and OUT- = activeWhen Low : OUT+ and OUT- = Output is low (weak pull down), oscillation stopsSD: Spread Disable - disables spread spectrumWhen High or Open : Spread Spectrum modulation = activeWhen Low : Spread Spectrum modulation = Off2 NC NA No connect pin, leave it floating.3 GND Power VDD power supply ground. Connect to ground4 OUT+ Output 1 to 220 MHz programmable clock output. For frequencies > 220 MHz contact SiTime5 OUT- Output6 VDD Power Power supplyAbsolute Maximum RatingsAttempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not absolute maximum ratings.Ab solute Maximum TableParameter Min.Max.Unit Storage Temperature -65150 °C VDD -0.5 4 VVin GND - 0.5 VDD + 0.5 VTheta JA ( with copper plane on VDD and GND) 5.0 x 3.2 package 7.0 x 5.0 package when center pad is soldered down7.0 x 5.0 package when center pad is not soldered down – 68 °C/W – 38 °C/W – 90 °C/WTheta JC (with PCB traces of 0.010 inch to all pins) 5.0 x 3.2 package 7.0 x 5.0 package when center pad is soldered down7.0 x 5.0 package when center pad is not soldered down – 45 °C/W – 35 °C/W – 48 °C/WSoldering Temperature (follow standard Pb free soldering guidelines) – 260 °C Number of Program Writes – 1 NA Program Retention over -40 to 125C, Process, VDD (0 to 3.6V) – 1,000+ years Human Body Model (JESD22-A114) 2000 – V Charged Device Model (JESD22-C101) 750 – – Machine Model (JESD22-A115) 200 – –DC Electrical SpecificationsEnvironmental ComplianceParameter Condition/T est MethodMechanical Shock MIL-STD-883F, Method 2002Mechanical Vibration MIL-STD-883F, Method 2007T emperature Cycle MIL-STD-883F, Method 1010-65-150°C (1000 cycle)Solderability MIL-STD-883F, Method 2003Moisture Sensitivity Level MSL1 @ 260°CL VCMOS input, OE or ST pin, 3.3V ± 10% or 2.5V ± 10% or 1.8V ± 5%, -40 to 85°CSymbol Parameter Condition Min.Typ.Max.Unit V IH Input High Voltage 70 – – %Vdd V IL Input Low Voltage – – 30 %Vdd I IH Input High Current OE or ST or SD pin – – 10 uA I IL Input Low Current OE or ST or SD pin -10– – uA T pu Power Up Time Time from minimum power supply voltage to thefirst cycle (Guaranteed no runt pulses)– – 10 ms LVPECL, 3.3V ± 10% or 2.5V ± 10%, -40 to 85°CSymbol Parameter Condition Min.Typ.Max.Unit V DD Supply Voltage 2.97 3.3 3.63 V2.25 2.5 2.75 VI DD Supply Current V DD = 3.3, Excluding Load Termination Current – 75 84 mAV DD = 2.5, Excluding Load Termination Current – 75 84 mAV OH Output High Voltage 50 Ohm termination to V DD - 2.0VSee Figure 2,3. V DD-1.1 – V DD-0.7 VV OL Output Low Voltage V DD-2.0 – V DD-1.4 V V swing Pk-Pk Output Voltage Swing 600 800 1000 mVHCSL, 3.3V ±10% or 2.5V ±10%, -40 to 85°CSymbol Parameter Condition Min.Typ.Max.Unit V DD Supply Voltage 2.97 3.3 3.63 V2.25 2.5 2.75 VI DD Supply Current V DD = 3.3, Excluding Load Termination Current – 73 80 mAV DD = 2.5, Excluding Load Termination Current – 73 80 mAV OH Output High Voltage 50 Ohm termination to GNDSee Figure 4. 0.6 0.75 0.95 VV OL Output Low Voltage 0.0 – 50 mV V swing Pk-Pk Output Voltage Swing 600 750 950 mV LVDS, 3.3V ± 10% or 2.5V ± 10%, -40 to 85°CSymbol Parameter Condition Min.Typ.Max.Unit V DD Supply Voltage 2.97 3.3 3.63 V2.25 2.5 2.75 VI DD Supply Current V DD = 3.3, Excluding Load Termination Current – 75 85 mAV DD = 2.5, Excluding Load Termination Current – 70 77 mAV OD1 Differential Output Voltage Swing Mode = NormalSingle load termination.See Figure 5. 250 350 450 mV∆V OD1 VOD Magnitude Change – – 50 mV V OS1 Offset Voltage – 1.2 – V ∆V OS1 VOS Magnitude Change – – 50 mVV OD2 Differential Output Voltage Swing Mode = HighSingle load termination.See Figure 5. 500 700 900 mV∆V OD2 VOD Magnitude Change – – 50 mV V OS2 Offset Voltage – 1.2 – V ∆V OS2 VOS Magnitude Change – – 50 mVV OD3 Differential Output Voltage Swing Mode = HighDouble load termination.See Figure 6. 250 350 450 mV∆V OD3 VOD Magnitude Change – – 50 mV V OS3 Offset Voltage – 1.2 – V ∆V OS3 VOS Magnitude Change – – 50 mVCML, 3.3V ± 10% or 2.5V ± 10% or 1.8V ± 5%, -40 to 85°CSymbol Parameter Condition Min.Typ.Max.Unit V DD Supply Voltage 2.97 3.3 3.63 V2.25 2.5 2.75 V1.71 1.8 1.89 VI DD Supply Current V DD = 3.3V Excluding LoadTerminationCurrent – 48 51 mAV DD = 2.5V – 48 51 mA V DD = 1.8V – 48 51 mAV OH1 Output High Voltage Swing Mode = NormalSingle Load TerminationSee Figure 7. V DD-0.1 – V DD VV OL1Output Low Voltage V DD-0.55 V DD-0.425 V DD-0.3 V V swing1 Pk-Pk Output Voltage Swing 300 425 550 mVV OH2 Output High Voltage Swing Mode = HighSingle Load TerminationSee Figure 7. V DD-0.1 – V DD VV OL2Output Low Voltage V DD-1.1 V DD-0.85 V DD-0.6 V V swing2 Pk-Pk Output Voltage Swing 600 850 1100 mVV OH3 Output High Voltage Swing Mode = HighDouble Load TerminationSee Figure 8. V DD-0.1 – V DD VV OL3Output Low Voltage V DD-0.55 V DD-0.425 V DD-0.3 V V swing3 Pk-Pk Output Voltage Swing 300 425 550 mVAC Electrical SpecificationsLVPECL, 3.3V ± 10%, -40 to 85°CSymbol Parameter Condition Min.Typ.Max.Unit F out Output Frequency 1.0 – 220 MHzF stab Frequency Stability Inclusive of initial stability,operating temp., rated powersupply voltage change, loadchange -20 to 70°C-25– +25ppm -40 to 85°C-50– +50ppmF age Aging First year @ 25°C – – 1 PPM DC Duty Cycle 45 – 55 % t R/t F Output Rise/Fall Time 20% to 80% 100 150 300 ps T CCJ Cycle-Cycle Jitter F out = 100 MHz, -0.5% down spread – 10 16 psF out = 150 MHz, -0.5% down spread – 8 14 psF out = 200 MHz, -0.5% down spread – 8 14 psLVPECL, 2.5V ± 10%, -40 to 85°CSymbol Parameter Condition Min.Typ.Max.Unit F out Output Frequency 1.0 – 220 MHzF stab Frequency Stability Inclusive of initial stability,operating temp., rated powersupply voltage change, loadchange -20 to 70°C-25– +25ppm -40 to 85°C-50– +50ppmF age Aging First year @ 25°C – – 1 PPM DC Duty Cycle 45 – 55 % t R/t F Output Rise/Fall Time 20% to 80% 100 150 300 ps T CCJ Cycle-Cycle Jitter F out = 100 MHz, -0.5% down spread – 10 16 psF out = 150 MHz, -0.5% down spread – 8 14 psF out = 200 MHz, -0.5% down spread – 8 14 psHCSL, 3.3V ± 10%, -40 to 85°CSymbol Parameter Condition Min.Typ.Max.Unit F out Output Frequency 1.0 – 220 MHzF stab Frequency Stability Inclusive of initial stability,operating temp., rated powersupply voltage change, loadchange -20 to 70°C-25– +25ppm -40 to 85°C-50– +50ppmF age Aging First year @ 25°C – – 1 PPM DC Duty Cycle 45 – 55 % t R/t F Output Rise/Fall Time 20% to 80% 200 280 375 ps T CCJ Cycle-Cycle Jitter F out = 100 MHz, -0.5% down spread – 10 16 psF out = 150 MHz, -0.5% down spread – 10 15 psF out = 200 MHz, -0.5% down spread – 10 15 psHCSL, 2.5V ± 10%, -40 to 85°CSymbol Parameter Condition Min.Typ.Max.Unit F out Output Frequency 1.0 – 220 MHzF stab Frequency Stability Inclusive of initial stability,operating temp., rated powersupply voltage change, loadchange -20 to 70°C-25– +25ppm -40 to 85°C-50– +50ppmF age Aging First year @ 25°C – – 1 PPM DC Duty Cycle 45 – 55 % t R/t F Output Rise/Fall Time 20% to 80% 200 300 400 ps T CCJ Cycle-Cycle Jitter F out = 100 MHz, -0.5% down spread – 9 19 psF out = 150 MHz, -0.5% down spread – 9 17 psF out = 200 MHz, -0.5% down spread – 9 15 psLVDS, 3.3V ± 10%, -40 to 85°CSymbol Parameter Condition Min.Typ.Max.Unit F out Output Frequency 1.0 – 220 MHzF stab Frequency Stability Inclusive of initial stability,operating temp., rated powersupply voltage change, loadchange -20 to 70°C-25– +25ppm -40 to 85°C-50– +50ppmF age Aging First year @ 25°C – – 1 PPM DC Duty Cycle 45 – 55 % t R/t F Output Rise/Fall Time 20% to 80% 100 200 325 ps T CCJ Cycle-Cycle Jitter F out = 100 MHz, -0.5% down spread – 11 19 psF out = 150 MHz, -0.5% down spread – 11 20 psF out = 200 MHz, -0.5% down spread – 11 21 psL VDS, 2.5V ± 10%, -40 to 85°CSymbol Parameter Condition Min.Typ.Max.Unit F out Output Frequency 1.0 – 220 MHzF stab Frequency Stability Inclusive of initial stability,operating temp., rated powersupply voltage change, loadchange -20 to 70°C-25– +25ppm -40 to 85°C-50– +50ppmF age Aging First year @ 25°C – – 1 PPM DC Duty Cycle 45 – 55 % t R/t F Output Rise/Fall Time 20% to 80% 100 260 325 ps T CCJ Cycle-Cycle Jitter F out = 100 MHz, -0.5% down spread – 14 26 psF out = 150 MHz, -0.5% down spread – 14 26 psF out = 200 MHz, -0.5% down spread – 14 27 psCML, 3.3V ± 10%, -40 to 85°CSymbol Parameter Condition Min.Typ.Max.Unit F out Output Frequency 1.0 – 220 MHzF stab Frequency Stability Inclusive of initial stability,operating temp., rated powersupply voltage change, loadchange -20 to 70°C-25– +25ppm -40 to 85°C-50– +50ppmF age Aging First year @ 25°C – – 1 PPM DC Duty Cycle 45 – 55 % t R/t F Output Rise/Fall Time 20% to 80% 150 220 300 ps T CCJ Cycle-Cycle Jitter F out = 100 MHz, -0.5% down spread – 11 20 psF out = 150 MHz, -0.5% down spread – 11 18 psF out = 200 MHz, -0.5% down spread – 10 19 psCML, 2.5V ± 10%, -40 to 85°CSymbol Parameter Condition Min.Typ.Max.Unit F out Output Frequency 1.0 – 220 MHzF stab Frequency Stability Inclusive of initial stability,operating temp., rated powersupply voltage change, loadchange -20 to 70°C-25– +25ppm -40 to 85°C-50– +50ppmF age Aging First year @ 25°C – – 1 PPM DC Duty Cycle 45 – 55 % t R/t F Output Rise/Fall Time 20% to 80% 150 230 300 ps T CCJ Cycle-Cycle Jitter F out = 100 MHz, -0.5% down spread – 13 22 psF out = 150 MHz, -0.5% down spread – 12 19 psF out = 200 MHz, -0.5% down spread – 11 20 psCML, 1.8V ± 5%, -40 to 85°CSymbol ParameterConditionMin. Typ. Max. Unit F out Output Frequency 1.0 – 220 MHz F stabFrequency StabilityInclusive of initial stability, operating temp., rated power supply voltage change, load change-20 to 70°C -25– +25ppm -40 to 85°C-50– +50ppm F age Aging First year @ 25°C – – 1 PPM DC Duty Cycle45 – 55 % t R /t F Output Rise/Fall Time 20% to 80%150 230 300 ps T CCJCycle-Cycle JitterF out = 100 MHz, -0.5% down spread – 13 23 ps F out = 150 MHz, -0.5% down spread – 12 22 ps F out = 200 MHz, -0.5% down spread–1221psTermination DiagramsFigure 1. LVPECL AC Coupled Typical TerminationFigure 2. LVPECL DC Coupled Typical Termination with Termination VoltageVDD = 3.3VR1 = 150 OhmVDD = 2.5VR1 = 120 OhmFigure 3. LVPECL DC Coupled Typical Termination without Termination VoltageFigure 4. HCSL Typical TerminationNote:1. All the tests are done with RS = 20 Ohm (recommended).Figure 5. LVDS Single Load Termination (Load Terminated)VDD = 3.3VR1 = R3 = 133 Ohm R2 = R4 = 82 OhmVDD = 2.5VR1 = R3 = 250 Ohm R2 = R4 = 62.5 OhmFigure 6. LVDS Double Termination (Source + Load Terminated)Figure 7. CML Single Load TerminationFigure 8. CML Double Load TerminationRev . 1.1 Page 11 of 12 Ordering InformationThe Part No. Guide is for reference only. For real-time customization and exact part number, use the SiTime Part Number Generator .Frequency Stability vs. Temperature Range OptionsSignaling Type vs. Swing Select OptionsNote:1.Without Center Pad.Signaling T ype Swing Select Supply Voltage1.8 V2.5 V3.3 VLVPECL-0Normal –High – ––LVPECL-1Normal –High – ––LVDSNormal – High –CMLNormal HighHCSLNormal –High–––Frequency Stability (PPM)T emperature Range Supply Voltage 1.8 V2.5 V3.3 V±25 C (-20 to +70°C) I (-40 to +85°C) ±50C (-20 to +70°C)I (-40 to +85°C)www.sitime china .comPackage Information [2]Dimension (mm) Land Pattern[3] (recommended) (mm)5.0 x 3.2 x 0.75mm7.0 x 5.0 x 0.90mmNotes:2. Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the device.3. A capacitor of value 0.1µF between VDD and GND is recommended.4. The 7050 package with part number designation "-8" has NO center pad.© SiTime Corporation 2013. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liability for any loss, damage or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect or accident, (iii) unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv) improper installation, storage, handling, warehousing or transportation, or (v) being subjected to unusual physical, thermal, or electrical stress.Disclaimer: SiTime makes no warranty of any kind, express or implied, with regard to this material, and specifically disclaims any and all express or implied warranties, either in fact or by operation of law, statutory or otherwise, including the implied warranties of merchantability and fitness for use or a particular purpose, and any implied warranty arising from course of dealing or usage of trade, as well as any common-law duties relating to accuracy or lack of negligence, with respect to this material, any sitime product and any product documentation. products sold by sitme are not suitable or intended to be used in a life support application or component, to operate nuclear facilities, or in other mission critical applications where human life may be involved or at stake. all sales are made conditioned upon compliance with the critical uses policy set forth below.CRITICAL USE EXCLUSION POLICYBUYER AGREES NOT TO USE SITIME'S PRODUCTS FOR ANY APPLICATION OR IN ANY COMPONENTS USED IN LIFE SUPPORT DEVICES OR TO OPERATE NUCLEAR FACILITIES OR FOR USE IN OTHER MISSION-CRITICAL APPLICATIONS OR COMPONENTS WHERE HUMAN LIFE OR PROPERTY MAY BE AT STAKE.SiTime owns all rights, title and interest to the intellectual property related to SiTime's products, including any software, firmware, copyright, patent, or trademark. The sale of SiTime products does not convey or imply any license under patent or other rights. SiTime retains the copyright and trademark rights in all documents, catalogs and plans supplied pursuant to or ancillary to the sale of products or services by SiTime. Unless otherwise agreed to in writing by SiTime, any reproduction, modification, translation, compilation, or representation of this material shall be strictly prohibited.Rev. 1.11 Page 12 of 12 www.sitime 。

SITIME晶振SiT1566温补振荡器规格书(精)

【SITIME中国区样品与大批量现货量产中心 - 深圳扬兴科技有限公司】www.yxc.hk SiT1566 1.2mm2 Micropower, 5 ppm, Low-Jitter 32.768 kHz Super TCXO5°C/sec Temp Ramp Frequency Response 10°C/sec Temp Ramp Frequency Response ~10°C/sec ~5°C/sec [3] [3] 3 Hz Temp Comp Refresh Rate 3 Hz Temp Comp Refresh Rate For temperature ramps >5°C/sec, the frequency accuracy is limited by the update rate of the temperature compensation path (see the 5°C/sec and 10°C/sec plots. Contact Factory for applications that require improved dynamic performance. Note: 3. Measured relative to 32.768 kHz. Rev. 0.7 Page 6 of 8 【SITIME中国区样品与大批量现货量产中心 - 深圳扬兴科技有限公司】www.yxc.hk SiT1566 1.2mm2 Micropower, 5 ppm, Low-Jitter 32.768 kHz Super TCXO– Dimensions (Unit: mm 1.55 x 0.85 mm CSP 1.54 ±0.04 Recommended Land Pattern (Unit: mm 0.84 ±0.04 #4 #3 #3 0.315 ±0.015 #4 #4 #3 #1 #2 #2 #1 #1 #2 Recommend 4-mil (0.1mm stencilthickness Manufacturing Guidelines 1 2 3 4 No Ultrasonic or Megasonic cleaning: Do not subject SiT1566 to an ultrasonic or megasonic cleaning environment. Permanent damage or long term reliability issues may occur. Applying board-level underfill and overmold is acceptable and will not impact the reliability of the device. Reflow profile, per JESD22-A113D. For additional manufacturing guidelines and marking/tape-reel instructions, click on the following link:/component/docman/doc_download/243-manufacturing-notes-for-sitimeoscillators Rev. 0.7 Page 7 of 8 【SITIME中国区样品与大批量现货量产中心 - 深圳扬兴科技有限公司】www.yxc.hk SiT1566 1.2mm2 Micropower, 5 ppm, Low-Jitter 32.768 kHz Super TCXO566AI-JE-DCC-32.768S Part Family “SiT1566” Revision Letter “A”: is the revision Temperature Range “C”: Extended Commercial, -20 to 70ºC “I”: lndustrial, -40 to 85ºC Output Clock Frequency (kHz 32.768 kHz Packaging “S”: 8 mm Tape & Reel, 10ku reel “D”: 8 mm Tape & Reel, 3ku reel “E”: 8 mm Tape & Reel, 1ku reel Samples in cut Tape Package Size “J”: 1.5 mm x 0.8 mm CSP All-Inclusive Over Temp Stability “E”: ±5 ppm LVCMOS Output Revision History Revision 0.1 0.7 Release Date 6/30/15 3/11/16 Change Summary Advanced datasheet initial release Preliminary datasheet initial release © SiTime Corporation 2016. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liability for any loss, damage or defect of a Product which is caused in whole or in part by (i use of any circuitry other than circuitry embodied in a SiTime product, (ii misuse or abuse including static discharge, neglect or accident, (iii unauthorized modification or repairs which have been soldered or altered during assembly and are not capable of being tested by SiTime under its normal test conditions, or (iv improper installation, storage, handling, warehousing or transportation, or (v being subjected to unusual physical, thermal, or electrical stress. Disclaimer: SiTime makes no warranty of any kind, express or implied, with regard to this material, and specifically disclaims any and all express or implied warranties, eitherin fact or by operation of law, statutory or otherwise, including the implied warranties of merchantability and fitness for use or a particular purpose, and any implied warranty arising from course of dealing or usage of trade, as well as any common-law duties relating to accuracy or lack of negligence, with respect to this material, any SiTime product and any product documentation. Products sold by SiTime are not suitable or intended to be used in a life support application or component, to operate nuclear facilities, or in other mission critical applications where human life may be involved or at stake. All sales are made conditioned upon compliance with the critical uses policy set forth below. CRITICAL USE EXCLUSION POLICY BUYER AGREES NOT TO USE SITIME'S PRODUCTS FOR ANY APPLICATION OR IN ANY COMPONENTS USED IN LIFE SUPPORT DEVICES OR TO OPERATE NUCLEAR FACILITIES OR FOR USE IN OTHER MISSION-CRITICAL APPLICATIONS OR COMPONENTS WHERE HUMAN LIFE OR PROPERTY MAY BE AT STAKE. SiTime owns all rights, title and interest to the intellectual property related to SiTime's products, including any software, firmware, copyright, patent, or trademark. The sale of SiTime products does not convey or imply any license under patent or other rights. SiTime retains the copyright and trademark rights in all documents, catalogs and plans supplied pursuant to or ancillary to the sale of products or services by SiTime. Unless otherwise agreed to in writing by SiTime, any reproduction, modification, translation, compilation, or representation of this material shall be strictly prohibited. Rev. 0.7 Page 8 of 8。

飞兆半导体FSFR系列功率开关（FPSTM）半桥LLC谐振变换器设计说明书

应用说明书 AN-4151采用飞兆半导体FSFR系列功率开关（FPS TM）半桥LLC谐振变换器的设计引言不断增加的开关电源功率密度，已经受到了无源器件尺寸的限制。

采取高频运行，可以大大降低无源器件，如变压器和滤波器的尺寸。

但是过高的开关损耗势必成为高频运行的一大障碍。

为了降低开关损耗和容许高频运行，谐振开关技术已经得到了发展。

这些技术采用正弦方式处理电力，开关器件能够实现软换流。

使得开关损耗与噪声大为降低[1-7]。

在各种类型的谐振变换器中，最简单和最普遍的谐振变换器为LC串联谐振变换器，其中整流器-负载网络与LC谐振网络串联，如图1所示[2-4]。

在该电路结构中，LC谐振网络与负载一起形成分压器。

通过改变驱动电压V d的频率，可以改变该谐振网络的阻抗。

输入电压在谐振网络阻抗与反射负载之间进行分压。

由于分压作用，LC串联谐振变换器的DC增益总是小于1。

在轻载条件下，相比谐振网络的阻抗而言，负载阻抗很大。

全部输入电压都被施加到负载上。

这使得轻载下很难调节输出。

在空载时，为了能够调节输出，理论上谐振频率应该为无限大。

+O-图1 半桥LC串联谐振变换器为了打破串联谐振变换器的限制，LLC谐振变换器已经获得提出[8-12]。

LLC谐振变换器是一种改进型的串联谐振变换器，通过在变压器初级绕组放置一个并联电感而得以实现，如图2所示。

采用并联电感可以增加初级绕组的环流，有利于电路运行。

由于这个概念不直观，在该拓扑首次提出时没有受到足够的重视。

然而在开关损耗相比通态损耗占主导比重的高输入电压应用中，却有利于效率的提高。

在大多数实际设计中，该并联电感采用变压器的励磁电感。

LLC谐振变换器的电路图与LC串联谐振变换器的电路图十分相似。

唯一的差别在于：励磁电感的取值不同。

LLC谐振变换器的励磁电感远远大于LC串联谐振变换器的励磁电感（Lr），LLC谐振变换器中的励磁电感为Lr的3-8倍，通常通过增加变压器的气隙来获得。

SITIME硅晶振SiT8002低抖动振荡器规格书

@VDD = 2.5V ±10%, -40 to 85°C
Parameter Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low Operating Current Standby Current Power Up Time
www.yxc.hk
SiT8002
1 to 125 MHz Programmable Oscillator
DC Electrical Specifications
@VDD = 3.3V ±10%, -40 to 85°C
Parameter Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low Operating Current Standby Current Power Up Time
@VDD = 1.8V ±5%, -40 to 85°C
Parameter Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low Operating Current Standby Current Power Up Time
Condition IOH = -7 mA IOL = 7 mA Pin 1 Pin 1 Output frequency = 65 MHz, 15 pF load Output is weakly pulled down, ST = GND Time from minimum power supply voltage
Condition IOH = -9 mA IOL = 9 mA Pin 1 Pin 1 Output frequency = 65 MHz, 15 pF load Output is weakly pulled down, ST = GND Time from minimum power supply voltage

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SiT90051 to 141 MHz EMI Reduction OscillatorFeatures⏹Spread spectrum for EMI reduction▪Wide spread % option▫Center spread: from ±0.125% to ±2%, ±0.125% step size ▫Down spread: -0.25% to -4% with -0.25% step size ▪Spread profile option: Triangular, Hershey-kiss⏹Programmable rise/fall time for EMI reduction: 8 options,0.25 to 40 ns⏹Any frequency between 1 MHz and 141 MHz accurate to 6 decimal places⏹ 100% pin-to-pin drop-in replacement to quartz-based XO’s ⏹ Excellent total frequency stability as low as ±20 ppm ⏹ Operating temperature from -40°C to 85°C.⏹ Low power consumption of 4.0 mA typical at 1.8V⏹ Pin1 modes: Standby, output enable, or spread disable ⏹ Fast startup time of 5 ms ⏹ LVCMOS output⏹Industry-standard packages▪QFN: 2.0 x 1.6, 2.5 x 2.0, 3.2 x 2.5 mm 2▪Contact SiTime for SOT23-5 (2.9 x 2.8 mm 2)⏹RoHS and REACH compliant, Pb-free, Halogen-free and Antimony-freeApplications⏹Surveillance camera ⏹IP camera⏹Industrial motors ⏹Flat panels⏹Multi function printers ⏹PCI expressElectrical SpecificationsTable 1. Electrical CharacteristicsAll Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated. Typical values are at 25°C and 3.3V supply voltage.Table 1. Electrical Characteristics (continued)Table 2. Spread Spectrum % [1,2]Ordering Code Center Spread(%)Down Spread(%)A ±0.125 -0.25B ±0.250 -0.50C ±0.390 -0.78D ±0.515 -1.04E ±0.640 -1.29F ±0.765 -1.55G ±0.905 -1.84H ±1.030 -2.10I ±1.155 -2.36J ±1.280 -2.62K ±1.420 -2.91L ±1.545 -3.18M ±1.670 -3.45N ±1.795 -3.71O ±1.935 -4.01P ±2.060 -4.28Notes:1.In both center spread and down spread modes, modulation rateis employed with a frequency of ~31.25 kHz.2.Contact SiTime for wider spread options Table3. Spread ProfileSpread ProfileTriangularHershey-kissTable 4. Pin DescriptionTop ViewFigure 1. Pin AssignmentsNotes:3.In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option.4.A capacitor of value 0.1 µF or higher between Vdd and GND is required.Table 5. Absolute Maximum LimitsAttempted operation outside the absolute maximum ratings may cause permanent damage to the part.Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.ParameterMin. Max. Unit Storage Temperature -65150 °C Vdd-0.54 V Electrostatic Discharge– 2000 V Soldering Temperature (follow standard Pb free soldering guidelines) – 260 °C Junction Temperature [5]–150°CNote:5.Exceeding this temperature for extended period of time may damage the device.Table 6. Maximum Operating Junction Temperature [6]Max Operating Temperature (ambient)Maximum Operating Junction Temperature70°C 80°C 85°C95°CNote:6.Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.Table 7. Environmental ComplianceParameterCondition/Test MethodMechanical Shock MIL-STD-883F, Method 2002 Mechanical Vibration MIL-STD-883F, Method 2007 Temperature Cycle JESD22, Method A104 SolderabilityMIL-STD-883F, Method 2003 Moisture Sensitivity LevelMSL1 @ 260°C12 34VDDOUTGND OE// NC/SDTiming DiagramsT_start: Time to start from power-offFigure 2. Startup TimingT_resume: Time to resume from STFigure 3. Standby Resume Timing(ST Mode O nly)T_oe: Time to re-enable the clock outputFigure 4. OE Enable Timing (OE Mode Only)T_oe: Time to put the output in High Z modeFigure 5. OE Disable Timing (OE Mode Only)F r e q u e n c yFigure 6. SD Enable Timing (SD Mode Only)F re q u e n c y D e v i a t i o n (%)Figure 7. SD Diable Timing (SD Mode Only)Note:7.SiT9005 has “no runt” pulses and “no glitch” output during startup or resume.Programmable Drive StrengthThe SiT9005 includes a programmable drive strength feature to provide a simple, flexible tool to optimize the clock rise/fall time for specific applications. Benefits from the programmable drive strength feature are:⏹Improves system radiated electromagnetic interference(EMI) by slowing down the clock rise/fall t ime⏹Improves the downstream clock receiver’s (RX) jitter bydecreasing (speeding up) the clock rise/fall t ime.⏹Ability to drive large capacitive loads while maintaining fullswing with sharp edge rates.For more detailed information about rise/fall time control and drive strength selection, see the SiTime Application Notes section: /support/application-notes.EMI Reduction by Slowing Rise/Fall TimeFigure 8 shows the harmonic power reduction as the rise/fall times are increased (slowed down). The rise/fall times are expressed as a ratio of the clock period. For the ratio of 0.05, the signal is very close to a square wave. For the ratio of 0.45, the rise/fall times are very close to near-triangular waveform. These results, for example, show that the 11th clock harmonic can be reduced by 35 dB if the rise/fall edge is increased from5% of the period to 45% of the period.Figure 8. Harmonic EMI reduction as a Functionof Slower Rise/Fall TimeJitter Reduction with Faster Rise/Fall TimePower supply noise can be a source of jitter for the downstream chipset. One way to reduce this jitter is to increase rise/fall time (edge rate) of the input clock. Some chipsets would require faster rise/fall time in order to reduce their sensitivity to this type of jitter. The SiT9005 provides up to 3 additional high drive strength settings for very fast rise/fall time. Refer to the Vdd = 1.8V Rise/Fall Times for Specific C LOAD to determine the proper drive strength.High Output Load CapabilityThe rise/fall time of the input clock varies as a function of the actual capacitive load the clock drives. At any given drive strength, the rise/fall time becomes slower as the output load increases. As an example, for a 3.3V SiT9005 device with default drive strength setting, the typical rise/fall time is 1.1 ns for 15 pF output load. The typical rise/fall time slows down to 2.9 ns when the output load increases to 45 pF. One can choose to speed up the rise/fall time to 1.9 ns by then increasing the drive strength setting on the SiT9005. The SiT9005 can support up to 60 pF or higher in maximum capacitive loads with up to 3 additional drive strength settings. Refer to the Vdd = 1.8V Rise/Fall Times for Specific C LOAD to determine the proper drive strength for the desired combination of output load vs. rise/fall timeSiT9005 Drive Strength SelectionTables Table 1 through Table 12 define the rise/fall time for a given capacitive load and supplyvoltage.Select the table that matches the SiT9005 nominalsupply voltage (1.8V, 2.5V, 2.8V, 3.3V).Select the capacitive load column that matches theapplication requirement (15 pF to 60 pF)Under the capacitive load column, select the desiredrise/fall times.The left-most column represents the part number codefor the corresponding drive strength.Add the drive strength code to the part number forordering purposes.Calculating Maximum FrequencyBased on the rise and fall time data given in Tables Table 1 through Table 12, the maximum frequency the oscillator can operate with guaranteed full swing of the output voltage over temperature as follows:=15 x Trf_20/80Max Frequencywhere Trf_20/80 is the typical rise/fall time at 20% to 80% Vdd Example 1Calculate f MAX for the following condition:⏹Vdd = 3.3V (Table 12)⏹Capacitive Load: 30 pF⏹Desired Tr/f time = 1.6ns (rise/fall time part number code = Z) Part number for the above example:Drive strength code is inserted here. Default setting is “-”SiT9005AI Z14-33EB-105.12345Rise/Fall Time (20% to 80%) vs C LOAD TablesTable 8. Vdd = 1.8V Rise/Fall Times for Specific C LOAD Table 9. Vdd = 2.5V Rise/Fall Times for Specific C LOADRise/Fall Time Typ (ns)Drive Strength \ C LOAD 5 pF 15 pF 30 pF 45 pF 60 pF L 6.16 11.61 22.00 31.27 39.91A 3.19 6.35 11.00 16.01 21.52R 2.11 4.31 7.65 10.77 14.47B 1.65 3.23 5.79 8.18 11.08T 0.93 1.91 3.32 4.66 6.48E 0.78 1.66 2.94 4.09 5.74U 0.70 1.48 2.64 3.68 5.09F or "‐": default 0.65 1.30 2.40 3.35 4.56Rise/Fall Time Typ (ns)Drive Strength \ C LOAD 5 pF 15 pF 30 pF 45 pF 60 pF L 4.13 8.25 12.82 21.45 27.79A 2.11 4.27 7.64 11.20 14.49R 1.45 2.81 5.16 7.65 9.88B 1.09 2.20 3.88 5.86 7.57T 0.62 1.28 2.27 3.51 4.45E or "‐": default 0.54 1.00 2.01 3.10 4.01U 0.43 0.96 1.81 2.79 3.65F 0.34 0.88 1.64 2.54 3.32Table 10. Vdd = 2.8V Rise/Fall Timesfor Specific C LOADRise/Fall Time Typ (ns)Drive Strength \ C LOAD 5 pF 15 pF 30 pF 45 pF 60 pF L 3.77 7.54 12.28 19.57 25.27A 1.94 3.90 7.03 10.24 13.34R 1.29 2.57 4.72 7.01 9.06B 0.97 2.00 3.54 5.43 6.93T 0.55 1.12 2.08 3.22 4.08E or "‐": default 0.44 1.00 1.83 2.82 3.67U 0.34 0.88 1.64 2.52 3.30F 0.29 0.81 1.48 2.29 2.99 Table 11. Vdd = 3.0V Rise/Fall Timesfor Specific C LOADRise/Fall Time Typ (ns)Drive Strength \ C LOAD 5 pF 15 pF 30 pF 45 pF 60 pF L 3.60 7.21 11.97 18.74 24.30A 1.84 3.71 6.72 9.86 12.68R 1.22 2.46 4.54 6.76 8.62B 0.89 1.92 3.39 5.20 6.64T or "‐": default 0.51 1.00 1.97 3.07 3.90E 0.38 0.92 1.72 2.71 3.51U 0.30 0.83 1.55 2.40 3.13F 0.27 0.76 1.39 2.16 2.85Table 12. Vdd = 3.3V Rise/Fall Timesfor Specific C LOADRise/Fall Time Typ (ns)Drive Strength \ C LOAD 5 pF 15 pF 30 pF 45 pF 60 pF L 3.39 6.88 11.63 17.56 23.59A 1.74 3.50 6.38 8.98 12.19R 1.16 2.33 4.29 6.04 8.34B 0.81 1.82 3.22 4.52 6.33T or "‐": default 0.46 1.00 1.86 2.60 3.84E 0.33 0.87 1.64 2.30 3.35U 0.28 0.79 1.46 2.05 2.93F 0.25 0.72 1.31 1.83 2.61Dimensions and PatternsNotes:8.Top marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of thedevice.9.A capacitor of value 0.1 µF or higher between Vdd and GND is required.Ordering InformationThe Part No. Guide is for reference only.To customize and build an exact part number, use the SiTime Part Number Generator.Frequency1.000000 to 141.000000 MHz Part Family“SiT9005”Revision Letter “A” is the revision Temperature RangeSupply Voltage“18” for 1.8V ±10%“25” for 2.5V ±10%“28” for 2.8V ±10%“33” for 3.3V ±10%Feature Pin“E” for Output Enable “S” for Standby “N” for No Connect “D” for Spread Disablel Frequency Stability “1” for ±20 ppm “2” for ±25 ppm “3” for ±50 ppm Package Size[10]SiT9005AI -71-18EA25.000625D“30” for 3.0V ±10%Packing Method“D”: 8 mm Tape & Reel, 3ku reel “E”: 8 mm Tape & Reel, 1ku reel Blank for Bulk “XX” for 2.5V -10% to 3.3V +10%Output Drive Strength“–” Default (datasheet limits)See Tables 7 to 11 for rise/fall times “7” 2.0 x 1.6 mm “1” 2.5 x 2.0 mm “2” 3.2 x 2.5 mm “L”“A”“R”“B”“T”“E”“U”“F”“C” Commercial -20ºC to 70ºC “I” Industrial -40ºC to 85ºC Spread PercentageCenter:Down:±0.125,-0.25±0.250,-0.50±0.390,-0.78±0.515,-1.04±0.640,-1.29±0.765,-1.55±0.905,-1.84±1.030,-2.10±1.155,-2.36±1.280,-2.62±1.420,-2.91±1.545,-3.18±1.670,-3.45±1.795,-3.71±1.935,-4.01±2.060,-4.28Spread Type and Profile“-” Center spread & Triangular (Default) “H” Center spread & Hershey Kiss “D” Down spread & Triangular “G” Down spread & Hershey Kissfor for for for for for for for for for for for for for for for ”A”“B”“C”“D”“E”“F”“G”“H”“I”“J”“K”“L”“M”“N”“O”“P”Note:10.Contact SiTime for SOT23 (2.9 x 2.8 mm 2) packageSiT9005 1 to 141 MHz EMI Reduction OscillatorTable 13. Revision HistoryRevision Release Date Change Summary1.0 09/25/2017 Final releaseSiTime Corporation, 5451 Patrick Henry Drive, Santa Clara, CA 95054, USA | Phone: +1-408-328-4400 | Fax: +1-408-328-4439© SiTime Corporation 2016-2017. The information contained herein is subject to change at any time without notice. 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