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NiPd bond pads for copper wirebonding

Nickel–palladium bond pads for copper wire bondingHorst Clauberg a,*,Petra Backus b ,Bob Chylak aa Kulicke and Soffa Ind.Inc.,1005Virginia Drive,Fort Washington,PA 19034,USA bAtotech Deutschland GmbH,Erasmusstraße 20,10553Berlin,Germanya r t i c l e i n f o Article history:Received 2March 2010Received in revised form 9May 2010Available online xxxxa b s t r a c tThe semiconductor packaging industry is undergoing a step-change transition from gold to copper wire bonding brought on by a quadrupling of gold cost over the last 8years.The transition has been exception-ally rapid over the last 3years and virtually all companies in the industry now have signiﬁcant copper wire bonding production.Among the challenges to copper wire bonding is the damage to bond pads that had been engineered for wire bonding with the softer gold wire.This paper presents an extensive eval-uation of electroless NiPd and NiPdAu bond pads that offer a much more robust alternative to the stan-dard Al pad ﬁnish.These NiPd(Au)bond are shown to outperform Al in virtually all respects:bond strength,bond parameter window,lack of pad damage and reliability.Ó2010Elsevier Ltd.All rights reserved.1.IntroductionThe past 3years have seen a very rapid transition from gold to copper wire bonding,mainly driven by the large cost savings of copper in light of skyrocketing gold prices.At current gold prices ($1200per troy oz),it is estimated that the wire bonding cost sav-ings is 75%for a typical 300I/O package bonded with 25l m wire [1].These cost savings have driven the industry to solving multiple technical challenges caused by copper’s sensitivity to oxidation,corrosion and greater hardness.Along with cost savings for copper,also come the advantages of higher electrical and thermal conductivity.Technical improvements,know-how and manufacturing infra-structure are improving at a breathtaking speed.The current status of copper wire bonding from a technical and marketing point of view have been recently presented [1,2].A review of the technical literature for copper wire bonding has also been published [3].Among the technical challenges in copper wire bonding are excessive deformation of the bond pad aluminum (‘‘Al splash”)and damage to sensitive structures under the pads caused by the greater hardness of copper [2,4,5].This paper presents recent studies that demonstrate the advantages of NiPd and NiPdAu (‘‘NiPd(Au)”for short)bond pad structures (Fig.1)over the more standard Al bond pads with respect to pad damage and reliability.2.Bond pad metallization 2.1.NiPd and NiPdAu pad structuresAluminum bond pads have been the standard in the wire bond-ing industry for decades.It is inexpensive and,thanks to a thin,frangible passivating oxide layer,easily wire bondable.Its hardness is well matched to that of gold wire (Fig.2)[6,7],but it is less well suited for copper wire bonding.One of the most signiﬁcant draw-backs of aluminum pads for gold wire is Kirkendall voiding that re-sults from extensive intermetallic formation [8].The wire bonding industry has spent great effort to minimize Kirkendall voiding by engineering the bonding process,the bond pads and,most signiﬁ-cantly,the gold wire bonding alloys.NiPd(Au)bond pads also offer an advantage in this respect and lack of Kirkendall voiding is one of the reason why some companies have already adopted them for gold wire bonding [9–11].Not only is pure copper about twice as hard as pure gold [6],copper is also more susceptible to work hardening and the defor-mation associated with wire bonding can increase its hardness by an another 50%[12,13].In addition to this work hardening,cop-per wire bonding also requires approximately 20%more ultrasonic energy,exacerbating the problem of aluminum pad damage and cracking of fragile dielectrics under the pad [2,1].Nickel offers an attractive alternative to aluminum,since it is several times harder than aluminum and also harder than copper (Fig.2).Inexpensive electroless plating processes have been well developed and have now been re-optimized for plating bond pads on integrated circuits [14,15].An excellent overview of the status of Ni plating for wire bonding applications has just been published [16].Ni itself is actually not wire bondable due to a hard,infrangible0026-2714/$-see front matter Ó2010Elsevier Ltd.All rights reserved.doi:10.1016/j.microrel.2010.05.001*Corresponding author.E-mail address:hclauberg@ (H.Clauberg).Microelectronics Reliability xxx (2010)xxx–xxxContents lists available at ScienceDirectMicroelectronics Reliabilityjournal homepage:www.elsevi e r.c o m /l o c a t e /m i c r o r elsurface oxide layer.To provide a wire bondable surface,a thin layer of another metal needs to be applied to the surface.On many sub-strates,this layer is gold at a thickness of 0.3–0.5l m.While provid-ing an excellent bondable surface,it is necessarily somewhat expensive.Electroless Pd is a more cost-effective solution that is easily wire bondable with both gold and copper.Diffusion of Ni,Cu or Au into Pd is very slow,which provides highly stable me-tal–metal interfaces.Mostly for cost considerations,NiPd(Au)sur-face ﬁnishes have already seen accelerated acceptance for substrates in the marketplace.This technology is now well estab-lished,although still being ﬁne-tuned.As shown in Fig.1,NiPd(Au)pad metallizations can be applied either to existing Al pads or directly to the Cu conductors in the semiconductor die.NiPd(Au)on Al pads would be used for devices that are being converted from Au to Cu wire bonding,especially in cases where the existing pad structure is too fragile to withstand the additional stresses of Cu wire bonding.NiPd(Au)directly on Cu conductors would likely be the preferred choice for devices that are designed directly for Ni-based bond pads.Given the efﬁcient electroless plating processes,these bond pads can actually be more cost-effective than Al bond pads.Since electroless plating pro-cesses selectively deposit on the metal,either pad structure can be created without the need for photoresist masks.The pad structures consists of 1–3l m of electroless Ni,fol-lowed by 0.1–0.3l m electroless Pd.Both thicknesses are chosen to ensure complete and uniform coverage of all bond pads.As would be expected,thicker Ni provides additional mechanical pro-tection for underlying structures.The Pd thickness needs to be suf-ﬁcient to avoid Ni diffusion to the surface.The optional immersion Au layer is only about 0.02l m thick.2.2.Electroless plating of bond padsFor this study the NiPd(Au)plating was applied to existing Al pads.However,as mentioned above,NiPd(Au)pads can also be ap-plied to Cu conductors in the semiconductor die.The only differ-ence between the two processes is the pre-treatment of the surfaces before the electroless nickel/palladium plating.2.2.1.Pre-treatment of aluminum bond padsImmersion zincation is the industry-standard process in which the thin oxide layer on Al is ﬁrst removed and then replaced with a thin layer of zinc.This zinc layer provides the surface protection and the necessary roughness characteristics for the subsequent electroless metal deposition.In preparation for the zincation,any residual surface passiva-tions and Al oxides are ﬁrst removed by an acid cleaning and alka-line etching process.This exposes the Al metal and increases the pad roughness for improved mechanical and chemical reactivity for zincation.The etching system is speciﬁcally formulated for homogeneous and linear aluminum surface removal.Uniform and controlled surface removal in the cleaning and etching process ensures a maximum remaining pad thickness.Any unnecessary surface removal would reduce the bond pad thickness and could potentially cause reliability drawbacks,like pad deformation or damage of underlying structures.The devices in this study were prepared using an acidic zinca-tion process,rather than the more traditional alkaline,cyanide-based test environmental regulations and restrictions on the use of hazardous components (ROHS,WEEE)as well as cus-tomer-speciﬁc requirements are driving the zincation process to-wards cyanide-free,ﬁne-grain layer formation and more robust process control.Acidic zincation was developed in order to be envi-ronmentally friendly and simplify the handling.Additionally the acidic process conditions minimize the attack of the polyimide passivation layer relative to the alkaline process conditions.Mechanism for formation of a zincate immersion layer:2Al 0þ3Zn 2þ$2Al3þþ3Zn 02.2.2.Pre-treatment of copper metallizationPre-treatment of copper pads also involves cleaning,etching and activation,but the details are different.The cleaning step im-proves the pad surface tension and increases the chemical activity for subsequent process steps.Cleaning is followed by a mild sur-face etch to remove any residual copper oxide.Any remaining oxide would weaken the adhesion of Ni to Cu and thus would neg-atively inﬂuence the bonding performance.Finally the activation process deposits a thin palladium layer on the surface.It acts as the surface catalyst for the subsequent electroless nickel deposition.2.2.3.Electroless platingTypical nickel layers are 1–3l m thick and are the main struc-tural element of the pad stack.This layer provides the protection for fragile structures below the pad.The amount of phosphorous that is co-deposited must be carefully controlled to manage the stresses that typically occur in electroless plating processes.Mid-phosphorous processes (7–9.5%P)generate tensile stresses,while high phosphorous (10–11%P)produces compressive stress in the layer.The optimal combination of process conditions and thickness of the individual metal layers enables an almost stress free bond pad metallization.Such stress management is especially important to reduce the warpage of thin wafers.Palladium,with or without an additional very thin immersion gold layer,replaces the more traditional and much morecostlyFig.1.NiPd(Au)pad stacks:0.03l m Au (optional),0.1–0.3l m Pd,1–3l m Ni.Pre-treatment is zincation for Al bond pads or Pd for Cu devicemetallization.Fig.2.Vickers hardness of the metals of the bond pad stacks and bonding wires [5,6].These values are for the pure,annealed metals and would differ somewhat depending on speciﬁc alloy and annealing state.2H.Clauberg et al./Microelectronics Reliability xxx (2010)xxx–xxxthick,electrolytic goldﬁnish.Being a relatively hard,noble metal, the Pd layer is corrosion-resistant and mechanically strong.3.Experimental3.1.MaterialsNiPd and NiPdAu layers(Table1)were plated onto1l m thick Al pads(Al–1%Si–0.5%Cu)of test wafers using the Atotech Xeno-lyteÒprocess outlined above.An identical test wafer without any NiPd(Au)served as a reference.All devices were cleaned with Ar gas in a March plasma cleaner for5min before use.3.2.Cu wire bondingDevices were bonded on50l m pitch pads with20l m Heraeus Maxsoft copper wire at165°C.The Cu bonding process was per-formed using a K&S Max l m Ultra wire bonder with a Microenvi-ronment Copper Kit.Forming gas(5%/95%H2/N2)protected the free-air ball during formation.The bonding tool was a K&S CuPRA-plus capillary with1.25mil chamfer diameter(CD)and60°inner chamfer angle(ICA).3.3.High temperature storage testA subset of the wire bonded samples(A,B andC in Table1) along with an Al reference were bake tested unmolded at175°C up to1000h.To minimize oxidation of the copper wire,the baking was carried out under a nitrogen atmosphere.At each interval, samples were shear and pull tested using a Dage4000tester.Pull tests were conducted at top-of-loop.4.Copper wire bonding results4.1.Screening studyBonding parameters wereﬁrst optimized for the Al reference device and then applied without modiﬁcation to the eight combi-nations of NiPd(Au)pads listed in Table1.These optimized bond-ing parameters on a K&S Max l m Ultra wire bonder are:0.30mil/ ms impact velocity,14g force,80mA ultrasonic energy,70%pre-impact(pre-bleed)ultrasonic energy,12ms bond time.The bond-ing occurred without any non-sticks on pad and top-of-loop wire pull tests resulted in wire breaks above the ball in all cases,includ-ing the reference device.The shear test revealed theﬁrst substantial advantage of the NiPd(Au)pads.The shear-per-area strength on the NiPd(Au)pads was about5g/mil2(or more than50%)higher than for the bonds to Al.As seen in Fig.3,the shear strength of all the NiPd(Au)de-vices was approximately the same.No trend could be found be-tween the shear strength or its standard deviation and the metal stack conﬁguration.The shear failure mode was also completely different for the bonds to NiPd(Au)and Al.Since Cu is so much stronger than Al, the shear failure on Al is either at the Cu–Al interface or within the Al.Fig.4a shows this failure mode.It should be noted that as-bonded,no failure at the Al–Si interface was seen in the refer-ence samples.Such pad peeling can at times be a serious problem in Cu-to-Al ball bonding and requires very careful process optimization.In contrast,on NiPd(Au)bond pads,the tool shears through most of the Cu ball,leaving a thin layer of Cu behind as in Fig.4b.This failure mode was seen for all bonds on all of the NiP-d(Au)devices.Clearly the Cu ball itself is weaker than the Cu–Pd bond.This means that the shear test actually measures the strength of the copper ball and the bond-to-bond variation in the shear data is as much if not more a reﬂection of differences in the work hardening of the Cu ball than variation in the strength of the bond.ck of pad damageGreat resistance to pad damage is the main advantage of NiPd(Au)pad surfaceﬁnishes.Deformation(‘‘splash”)of the Al bond pad as seen in Fig.5c is a serious concern in Cu wire bonding and cannot be eliminated.The amount of Al splash is directly cor-related to the shear strength of the bond.Since it could cause shorts between adjacent bond pads,the target ball diameter for a copper wire bonding process is often reduced relative to the corre-sponding gold wire process to account for this splash.In addition, the copper wire bonding process must be carefully optimized so as to not completely remove all the aluminum under portions of the Cu ball.NiPd(Au)pads are completely resistant to such pad splash as can be seen in the bonded ball of Fig.5a.Removal of the Cu ball using nitric acid reveals that the bond pad is essentially unaltered by the bonding process(Fig.5b).Table1Sample description and bonding results for0.8mil Cu wire.Sample Ni(l m)Pd(l m)Au(l m)XY Avg(l m)Ball Z(l m)Shear SHR/area(g/mil2) Al–ref1l m,Al,reference die39.48.115.07.9A30.30.0339.29.224.613.2B30.3039.59.425.913.6C30.10.0339.19.324.313.1D10.1039.38.824.513.0E10.10.0339.58.925.713.5F10.30.0339.38.425.913.8G30.1039.29.226.013.9H10.3039.38.425.013.3Fig.3.As-bonded shear/area for NiPd(Au)samples A–H(Table1)and the referenceAl sample.H.Clauberg et al./Microelectronics Reliability xxx(2010)xxx–xxx34.3.Ultrasonic power bonding windowSince ultrasonic energy is the main factor responsible for both bond formation and pad damage in Cu-on-Al wire bonding,the ef-fect of varying this bond energy was more closely examined.Fig.6shows the results of an ultrasonic power sensitivity study for sam-ple A (3/0.3/0.03l m Ni/Pd/Au)and the Al reference device.A sim-ilar study was performed on sample F (1/0.3/0.03l m Ni/Pd/Au)with essentially identical results.Ultrasonic energy was incre-mented in steps of 5mA while keeping all other bonding parame-ters ﬁxed at the level used in the screening study.This type of experiments is typically used to establish the bonding window and measures the relative robustness of the bonding process.The diameter of the copper balls responds very similarly to the ultrasonic energy on both Al and Ni–Pd–Au pads.However,as mentioned previously,Al splash adds signiﬁcantly to the effective ball diameter when bonding to Al.To avoid the risk of shorting to adjacent pads,the Al splash,not the actual bonded ball diame-ter,deﬁnes the upper limit for the ultrasonic energy.In this exper-iment,the splash exceeds the ball diameter by approximately 4l m,a value that is representative for many real-life applications.Setting an upper spec limit of 40l m for this 50l m pitch process,the splash limits the ultrasonic energy to below 85mA on the Al pads.In contrast,since there is no splash and no pad damage,ultra-sonic energies as high as 115mA can be used on the NiPdAu pad before the ball exceeds the upper spec limit.Even at 115mA the bond pads remained completely undamaged.The lower limit of the bonding window is normally deﬁned by the ultrasonic energy that results in shear/area at the lower spec limit.This limit is usually set to 5.5g/mil 2.On the Al pads,this low-er ultrasonic limit is found to be 70mA.The useable ultrasonic en-ergy window on Al therefore extends only from 70to 85mA.On the NiPd(Au)pads,shear/area is far above the shear/area spec for all ultrasonic levels.Instead,the lower limit of the bond window is set by the occurrence of NSOP (non-stick on pad).For both samples A and F,a single NSOP out of 120wires occurred at 65mA ultrasonic energy.No NSOP occurred at higher ultrasonic levels.An ultrasonic energy of 70mA can therefore be set as the lower limit of the bonding window.The ultrasonic bond window for NiPd(Au)is therefore 70–115mA,three times as large as on Al pads.The behavior of the NiPd(Au)pads at the lower limit of ultra-sonic energy is actually somewhat surprising.As can be seen by the range bars in Fig.6b,even when ultrasonic levels are low en-ough for the occurrence of NSOP,the minimum shear values are quite high.The lower shear values typically correlate with asmal-Fig.4.Shear failure mode after bonding for (a)the reference Al pad sample and (b)sample B (3l m/0.3l m Ni/Pd,noAu).Fig.5.Electron micrographs of Cu ball bonds on (a)sample A and (c)Al pad,both bonded with 85mA ultrasonic energy,(b)shows the bond pad in (a)after the copper ball was removed with nitricacid.Fig.6.Ultrasonic power sensitivity of (a)ball diameter and (b)shear/area.NiPdAu sample A (diamonds),Al reference (triangles)and Al splash (squares).4H.Clauberg et al./Microelectronics Reliability xxx (2010)xxx–xxxler amount of copper remaining on the pads.Essentially the ball is ﬁrst sheared with failure in the copper,but then the ball breaks off the pad.Since the shear tester measures the maximum in the shear–displacement curve,the values for balls that break off early are actually not much lower than those where most of the copper remains on the pad.This observation suggests that the amount of copper remaining may be a more useful quality measure than shear strength.4.4.ReliabilitySamples A,B and C were chosen for a high temperature storage test at 175°C up to 1000h in a nitrogen atmosphere.All three had 3l m of Ni,but provided tests for the effect of 0.1l m vs.0.3l m Pd and the presence and absence of the immersion Au layer.The three samples behaved essentially identically in the bake test (Fig.7).The shear strength increased slightly over the ﬁrst 48h,but then remained unchanged for the remainder of the test.The failuremode was always shear through the copper.Top-of-loop pull tests resulted in wire breaks for all bake intervals.A separate 175°C bake test with 1mil Cu wire to 5000h was also passed with simi-larly excellent results.The Al reference samples failed this same reliability test.Although the shear strengths increased to eventually equal those of the NiPd(Au)devices,at 48h and all subsequent intervals,the Al reference sample had 10–30%peels and craters during the pull tests and many shear tests also resulted in failure at the Al–Si interface.The shear strengths at 1000h dropped because a few bonds failed with very low strength while others remained strong.Cross-sections (Fig.8)of the devices after 1000h at 175°C re-veal only minimal changes at the Cu–Pd and Pd–Ni interface.Over the period of the bake test,the Pd diffuses less than 0.5l m into the Cu.There is no noticeable diffusion layer between the nickel and palladium.Neither the Cu–Pd nor the Pd–Ni interface show any voids at all.The same is true for a sample from a similar study baked for 5000h at 175°C (Fig.8b)These cross-sections are in agreement with a previous studies [17,18]and attest to the excep-tional stability of these metal interfaces.5.ConclusionsNiPd and NiPdAu pad metallizations have been shown to be an excellent bonding surface for copper wire.They outperformed a standard Al pad with respect to bond window,shear strength,pad damage and reliability.Although not directly proven here,the lack of deformation of the pad also suggests that underlying structures would be much better protected with a Ni-based bond pad.In this study,neither the different Ni and Pd thicknesses nor the presence or absence of the immersion Au layer caused any dif-ference in the bond quality measures or high temperature storage test.No voids formed at the interface even after 5000h at 175°C.AcknowledgmentsThe authors would like to thank Alan Slopey and Son Nguyen of Kulicke &Soffa for their dedicated efforts in wire bonding and cross-sectioning/SEM,respectively,and Sophia Vietrich at Atotech for her help with electroless plating throughout this study.Special thanks are also extended to Tom Thieme,formerly of Atotech,for his efforts to further this collaboration.Deep appreciation is ex-tended to Kulicke &Soffa colleagues Gary Gillotti,Shai Friedman,Jon Brunner and Frank Keller for their fruitful discussions.References[1]Chylak B.How R&D has enabled dramatic growth in copper wire bondingproduction.IC Packaging Technology Expo,Tokyo;January 2010.[2]Chylak B.Developments in ﬁne pitch copper wire bonding production.In:Proceedings of the 11th Electronics Packaging Technology Conference (EPTC);2009.p.1–6.[3]Zhong ZW.Wire bonding using copper wire.Microelectron Int 2009;26:10–6.[4]Wei TC,Daud AR.Cratering on thermosonic copper ball wire bonding.J MaterEng Perform 2002;11(3):283–7.[5]Heinen G,Stierman RJ,Edwards D.Wire bonds over active circuits.In:Proceedings of the 44th electronic component and technology conference (ECTC);1994.[6]>.Vickers/Brinell hardness for pure metals;January 2010.[7]Gale WF,Totemeier TC,editors.Smithells metals referencebook.Oxford:Elsevier,Butterworth-Heinemann;2004.[8]Harman G.Wire bonding in microelectronics.3rd ed.New York:McGraw Hill;2010.pp.131–82.[9]Micron Technology,Inc.,Micron wire-bonding technology.Technote TN-29-24.</pdf/technotes/nand/tn2924.pdf>;2006.[10]Hashmonai A,Menache A,Thieme T.Nickel palladium-based pads for higherreliability in au wire process.In:42th International symposium on microelectronics (IMAPS 2009),San Jose;November2009.Fig.7.Shear/area progression during a high temperature storage test at 175°C.A:NiPdAu (3/0.3/0.03l m),B:NiPd (3/0.3l m),C:(3/0.1/0.03lm).Fig.8.Cross-sections after high temperature storage at 175°C.(a),(b)sample C at low and high magniﬁcation after 1000h,(c)similar sample after 5000h.H.Clauberg et al./Microelectronics Reliability xxx (2010)xxx–xxx 5[11]Sasangka WA,Tan AC.High temperature performance study of gold wirebonding on palladium bonding pad.In:8th electronics packaging technology conference(EPTC);2006.p.330–6.[12]E Phyu Phyu Theint Saraswati,Stephan D,Goh HM,Pasamanero E,CalpitoDRM,Wulff FW,Breach CD.High temperature storage(hts)performance of copper ball bonding wires.In:Proceedings of the7th electronic packaging technology conference(EPTC).Singapore;2005.[13]Wulff FW,Breach C,Stephan D,Saraswati K Dittmer,Garnier M.Furthercharacterization of intermetallic growth in copper and gold wire bonds on aluminum metallization.In:Semi technology symposium(SEMICON).Singapore;2005.[14]Chylak B,Ling J,Clauberg H,Thieme T.Next generation nickel-based bond padsenable copper wire bonding.ECS Trans2009;18(1):777–85.[15]Johal K,Lamprecht S,Roberts H.Electroless nickel/electroless palladium/immersion gold plating process for gold-and aluminum-wire bonding designed for high-temperature applications.In:SMTA9th annual pan paciﬁc microelectronics symposium;2004.[16]Ling J,England L.Ni-based platings used in electronics packaging.In:HarmanG,editor.Wire bonding in microelectronics.New York:McGraw Hill;2010.p.200–23.[17]Retchav P,Stoukatch S,Swinnen B.Mechanical reliability of Au and Cu wirebonds to Al,Ni–Au and Ni–Pd–Au capped Cu bond pads.Microelectron Reliab 2006;46:1315–25.[18]England L,Jiang T.Reliability of copper wire bonding to al metallization.In:IEEE electronic component technology conference(ECTC);2007.p.1604.6H.Clauberg et al./Microelectronics Reliability xxx(2010)xxx–xxx。

韦尔半导体封装工艺介绍

➢存放条件：零下5°保存，常温下需回温24小时；
Raw Material in Assembly(封装原材料)
【Epoxy】银浆
➢成分为环氧树脂填充金属粉末（Ag）；
➢有三个作用：将Die固定在Die Pad上；散热作用，导电作用；
➢-50°以下存放，使用之前回温24小时；
Typical Assembly Process Flow
BGA采用的是Substrate；
Raw Material in Assembly(封装原材料)
【Gold Wire】焊接金线
➢实现芯片和外部引线框架的电性和物理连接；
➢金线采用的是99.99%的高纯度金； ➢同时，出于成本考虑，目前有采用铜
线和铝线工艺的。优点是成本降低，同时工艺难度加大，良率降低； ➢线径范围；0.6mil ~2.0mil；
W/B四要素：压力（Force）、超声（USG Power）、时间（Time）、温度（Temperature）；
FOL– Wire Bonding 引线焊接
陶瓷的Capillary
内穿金线，并且在EFO的作用下，高温烧球；
金线在Cap施加的一定压力和超声的作用下，形成Bond Ball；
金线在Cap施加的一定压力作用下，形成 Wedge；
※利用高纯度的金线（Au）、铜线（Cu）或铝线（Al）把 Pad 和 Lead通过焊接的方法连接起来。Pad是芯片上电路的外接点，Lead是 Lead Frame上的连接点。 W/B是封装工艺中最为关键的一部工艺。
FOL– Wire Bonding 引线焊接
Key Words：
Capillary：陶瓷劈刀。W/B工艺中最核心的一个Bonding Tool，内部为空心，中间穿上金线，并分别在芯片的Pad和Lead Frame的Lead上形成第一和第二焊点；

锡须-3

含有甲基磺酸錫(MSA)-霧錫鍍層晶粒結構仍有錫鬚之顧慮選擇性電鍍 NiPdAu之顧慮，適用於電路板焊墊孔環與導線架之電鍍傳統霧錫鍍層長出針狀錫鬚(半年) NiPdAu鍍層無錫鬚(半年) 圖19 霧錫鍍層與NiPdAu鍍層之抗錫鬚能力比較Sourcing: 圖20用於導線架之連續選擇性電鍍 Cu/Ni，Ni/Pd/Au5. 國外連接器廠錫鬚問題的測試方案日本電子資訊技術產業協會（JEITA）日前宣佈，已與美國和歐洲的業界團體就聯合確立查明“錫鬚”產生機理的標準試驗方法達成了協定。

根據此協定，三方將制定有關錫鬚試驗方法的標準規格，並於2004年以前向國際電氣標準會議（IEC）提交草案。

此次達成協議的三方包括JEITA、全美電子製造商協會（NEMI）和歐洲代表性機構之一英國Soldertec公司。

全美電子製造商協會（NEMI）、IPC 和JEDEC等業界團體針對錫鬚試驗條件之統一有其諸多共識，近期2006年5月30日由IBM公司George T. Galyon 擔任主席，邀集各業界團體召開重要一場研討會。

各錫鬚試驗標準將於近期公開，會中許多內容將於後期再續。

目前JEITA和iNEMI、Soldertec等三方已經認可的錫晶鬚試驗條件包括如下3個：（1）高溫高濕試驗（溫度為+60℃，濕度為93±2～3%）、（2）冷熱衝擊試驗（溫度在-55℃或-40℃～85℃之間進行變化。

不過，升溫方式和高溫或低溫下的溫度保持時間將於日後再行探討）、（3）室溫下放置試驗（放置在20℃～25℃或15℃～35℃等室溫條件下）。

在2004年已向IEC提交草案對這3個條件有關的其他細節條件進行探討。

根據過去的常識很難判斷連接器上產生的錫鬚，也就是界定錫鬚產生之條件。

一般來說，電子設備在產品出廠前要在高溫高濕（+85℃，85%）環境下進行負荷試驗。

然而在室溫（+25℃±5℃）卻比高溫高濕環境更容易產生錫鬚，因此用原來的試驗方法很難推估有沒有因錫鬚而導致的故障分析。

为什么要使用电镀NiPdAu(镍钯金)

錫鬚
電偶腐蝕
只可打铝线接合
優
表現
差
打金线接合可靠性的比较
在相同打线接合的条件下(用第二焊点拉力测试 2nd bond pull test)，ENEPIG 显现出跟电镀镍金相约的打金线接合可靠性。
印刷線路板技術科技专刊
可靠性测试 1 现状
测试环境镀之后
2 在打线接合后把样本放加速老化打线接合在 150oC 烤箱烘烤 4 小时
至今，当半导体工业多年来从缩小线宽来致力于增进装置的性能时，很少有涉及这样的想法，也就是在一个电子系统中，装置间应该通过包含这个系统的封装来传递信息。大量的 I/O 需求及讯号传送质量已成为半导体工业重要考虑的因素，无论在 IC 内部的连接或把装置封装在线路版上，为了达到可靠的连接，封装过程的要求及线路版最终表面处理技术同样重要。
结论 – 使用 ENEPIG 的好处
ENEPIG 最重要的优点是同时间有优良的锡焊可靠性及打线接合可靠性，优点细列举如下:
1. 防止“黑镍问题”的发生–没有置换金攻击镍的表面做成晶粒边界腐蚀现象 2. 化学镀钯会作为阻挡层，不会有铜迁移至金层的问题出现而引起焊锡性焊锡差 3. 化学镀钯层会完全溶解在焊料之中，在合金界面上不会有高磷层的出现。同时当化学镀钯溶解后会露出一
为什么要使用化学电镍钯金?
September 2008 2008年9月
本文同步发表于 PCB007 网站
印刷線路板技術科技专刊
为什么要使用化学电镍钯金?
前言
电子产品一直趋向体积细小及轻巧，同时包含更多功能而又有更快速的运作效率。为了达到以上要求，电子封装工业便发展出多样化及先进的封装技术及方法，使之能在同一块线路版上增加集成电路(IC)的密度，数量及种类。

半导体元器件引线框架封装之分层研究

半导体元器件引线框架封装之分层研究福建福顺半导体制造有限公司陈力本文主要对半导体元器件引线框架封装工艺及封装材料对元器件分层的影响进行研究与说明。

文章通过分析如何改善封装材料、改善封装工艺技术防止元器件内部分层。

引言：半导体引线框架封装为整个半导体元器件产业链的主要后段加工制程之一。

主要目的是为保护表面布满集成电路的半导体硅芯片免受外界机械或化学因素腐蚀，并采用引线框架作为导通介质，其引线框架的材质一般为铜材或铁材。

现行的半导体封装工艺技术中，元器件内部的分层是重大的质量缺陷。

引线框架封装塑封体为非密封型，暴露于空气中容易吸收空气中的湿气。

当塑封体经过回流焊或波峰焊的高温时，塑封体内部的蒸汽压力会增加，在特定情况下，内部的压力会造成封装体内部分层。

严重的分层现象致使电性功能的失效。

依据JEDEC的可靠性实验为判断半导体封装工艺的国际标准，在模拟各种环境状况下如高压、高温、高湿、高低温等条件，加速元器件的老化及破坏，进而推算是否符合元器件的使用寿命要求。

1 如下分层判定标准依据JEDEC标准(JEDEC 020-E)JEDEC 020-E MSL3：前处理过程，烘烤24小时（125℃）+ 恒温恒湿40小时（60℃ 60%RH MSL3）+ IR*3次（260℃）要求。

2 分层实验检测设备简介通过Scanning Acoustic Tomograph（SAT）超音波断层扫描设备，可以判定元器件内部是否产生了分层。

试验设备为日立扫描式超声波图像装置。

3 半导体封装原材料组成主要原材料组成内容：晶圆、引线框架、焊线、塑封料、焊料。

（1）晶圆：半导体集成电路制作光刻处理后的硅晶片。

在硅晶片上加工制作成各种电路元件结构，而成为有特定电性功能之IC 产品。

晶圆的原始材料是硅。

（2）引线框架：主要材料为铜，会在上面进行镀银、 NiPdAu 等材料。

提供电路连接和Die的固定作用。

（3）焊线：早期金线一般采用的是99.99%的高纯度金；目前封装行业基本均采用铜线、银合金、铝线工艺。

锡须-2

圖9 錫層厚度與錫鬚成長長度比較錫鬚形成的機構簡易說明如下圖圖10錫鬚形成的機構簡易說明圖(1)銅和錫之間的不均勻的介金屬層（Cu6Sn5）產生(2) 熱負荷產生的擠壓驅動力(3) 機械應力負荷產生的擠壓驅動力(4) 搖動與震動荷產生的擠壓驅動力(5) 錫原子自身突破晶界自由能的向外爬錫效應(6)氧化錫層存在不均勻弱點缺口俄亥俄州立大學提出錫原子自身突破晶界不定位的向外爬錫效應(Dislocation Loop Climbing)，爬錫高度與溫度及應力相關，如圖11中來自底部的應力與側向阻檔應力形成斜側剪力將錫推出晶界。

運用兩階段擴展理論，當σ<σj時錫鬚無法生成，而σ>σj時錫鬚突破晶界不定位的向外爬出。

h = k(σ-σj)nh ：爬錫高度σ：來自底部的應力σj：來自側向阻檔應力與剛性k & n ：來自環境溫度與濕度圖11不定位的向外爬錫效應Tyco Electronic近期研究發現介金屬層（Cu6Sn5）厚度與曝露時間的均方根成線性正比關係，兩組位於圖12(下圖)紅色基線內高斜率處與藍色基線內低斜率處得知介金屬層（Cu6Sn5）厚度與曝露環境溫度有關，其次錫中有鎳層打底時介金屬層（Cu6Sn5）厚度受到明顯抑制，紅色基線內高斜率處內兩組資料顯示微量鉛存在有降低介金屬層（Cu6Sn5）厚度效果。

資料來源︰Tyco Electronic 2005 Forum Presentation paper.圖12 介金屬層（Cu6Sn5）厚度與聚焦離子束顯微技術觀察由掃瞄式電子顯微鏡錫鬚成長的觀察，初始針狀突起經柱狀，成長一定長度後由於剛性弱轉成環形成長(間隔四個月)錫鬚成長的機構初始針狀突柱狀增高剛性弱轉環狀初始針狀突起(首次) 繼續柱狀成長(間隔75天)柱狀成長(間隔60天) 柱狀轉成環形成長(間隔120天)錫鬚成長的統計，長度在10μm以下可忽略，數量與位置，長度與密度可記錄錫鬚成長的長度圖13掃瞄式電子顯微鏡錫鬚成長的過程觀察針對錫鬚風險立法規範，近期錫鬚工業標準要求提案，2005年意法半導體建議無鉛產品儲存兩年時，長度在50μm以上錫鬚是不被允許存在，在25μm以上錫鬚是不被允許超過1個，目前意法半導體內部已推動6。

镍基焊盘

下一代镍基焊盘成就铜引线键合工艺作者：Bob Chylak、Jamin Ling、Horst Clauberg，Kulicke and Soffa; Tom Thieme，Atotech Deutschland GmbH金引线键合工艺能在电子行业占据绝对优势地位长达20多年之久，其重要原因就在于它所具备的高可靠性和高性能。

而另一方面，其它类型的引线键合工艺，如铜或铝等在消费类产品或分立半导体产品等多引线、低成本领域中的应用却更为广泛。

由于金价已升至历史高位，铜以其密度低、刚度高、成本低、导电性能好、导热能力强以及在进行铝焊盘金属化时具有极佳的（金属间化合物）可靠性等优点已重新赢得业界的广泛关注。

目前业界对细节距铜引线键合工艺已有了基本的认识，基础条件已得到逐步的改进与完善。

因为铜容易氧化，因此在键合之前需要采用一套特殊的铜键合装置来营造一种惰性或还原气氛，这样才能通过熔融的方法形成焊球。

目前这类铜键合装置已经相当成熟，由金键合向铜键合工艺的转移已是水到渠成的事情。

铜的弹性模数要高于金，这一特点也使其能够轻易地满足超精细引线应用对引线又长又细的要求。

铜的导电性能和导热性能都很好，而且铜-铝金属间化合物的可靠性也极为卓异，这些优点进一步增加了业界对铜引线键合工艺关注的热度。

然而，铜的高刚度特性也会为键合工艺带来一定的加工难度。

为了获得满意的键合完整性，还要求材料具有较高的键合力来承受其较高的加工硬度。

如果在键合时采用超声能量，则可能会在原本已正常施加的键合力上额外增加一定的剪切力。

这一剪切力会穿过键合焊盘金属化层传送到其下方的既脆又极易断裂的介质材料上，从而导致焊盘剥落或键合失效。

在沿超声波方向进行键合期间，铜所具有的高硬度特性还可能会将较软的铝层抹掉，即通常所说的“铝飞溅”。

为了减少焊盘损伤和铝飞溅的影响，大量的工作都集中在键合参数的优化上，如超声波能量和键合力等。

目前这方面的研究已取得一定的成效。

集成电路焊线(WB)过程中不粘异常问题探讨

集成电路焊线(W/B)过程中不粘异常问题探讨由于铜丝的特殊性，键合过程中不粘现象较为严重，在铜丝键合过程中现不粘，应从以下方面解决：A、要保证拆封的铜丝无氧化、沾污，拆封后的铜丝要在48 小时内用完；B、夹具表面平整光滑，载体无松动；C、保证烧球时气体保护良好；D、装片平整，胶量充足，固化焊接温度均匀、牢固。

E、劈刀选用合理；F、设备参数调整合适。

铜丝产品对压焊夹用的选用要求非常严格，首先夹具制作材料要选用得当，同时夹具表面光滑，要保证载体和管脚无松动，否则将直接影响产品焊接过程中烧球不良，不粘等一系列焊线问题。

对于框架的第二焊点是铜丝键合质量的一个挑战，首先，铜丝氧化可能导致焊接点和引线框架之间界面间强度减弱，而且由于氧化作用焊接点容易脆裂，即容易产生焊点脱落或接力强度度；其次，铜丝键合在第二焊点需设置更高的键合参数，从而在控制焊接形貌上存在难度，并且需要调整引线框架(引线端)的设计以能够经受更高的键合参数。

因此要达到：(1) 框架表面光滑、镀层良好。

如Ag 预镀表面框架的银层应控制在0.03~0.06mm;(2) 管脚共面性良好，不充许有扭曲、翘曲不良现象。

管脚表面粗糙和共面性差的框架拉力无法保证且容易出现不粘和切线造成的烧球不良，压焊过程中容易不粘及出现尾部过短的现象。

(3) 铜丝对于Ag 预镀表面框架键合具有好的焊接性能，合理的设置焊接参数即可达到质量要求，而对于NipdAu 预镀表面框架，则需要更长的键合时间和大的待机功率来提高第二键合期间的引线稳定性。

3、劈刀的选用铜丝选用的劈刀与金线选用的劈刀差别不大，但铜丝劈刀端部要求表面粗糙些，这有利于增加超声焊接时的背部表面张力和端部表面的焊接力。

同时还要注意以下劈刀形状差异：(1) 铜丝劈刀T 面要稍大一点，太小第二压点(2nd)容易切断造成拉力不够或不均匀；(2) 铜丝劈刀CD 可基本保持不变，太大或太小都容易出现不粘等现象；(3) 铜丝劈刀H(孔径)比铜丝直径大8pim 即可，太小容易在颈部拉断；(4) 铜丝劈刀CA 可适当减小角度值，大了易造成线弧不均匀，但太小线弧颈部容易拉断。

一种基于Flip-chip连接的超薄封装件及其制作工艺[发明专利]

专利名称：一种基于Flip-chip连接的超薄封装件及其制作工艺专利类型：发明专利
发明人：肖国庆
申请号：CN202011244501.6
申请日：20201110
公开号：CN112349674A
公开日：
20210209
专利内容由知识产权出版社提供
摘要：本发明提供了一种基于Flip‑chip连接的超薄封装件及其制作工艺，封装件包括：包括塑封体、芯片、多个金属凸点、镀银层、镀NiPdAu层、铜倒角连接层以及引线框架；镀银层为多段式层结构，且形成相互独立间隔的层段；芯片的电气面植有金属凸点；芯片通过金属凸点电气接合于镀银层上；塑封体能够将金属凸点、芯片、镀银层、镀NiPdAu层和铜倒角连接层填充包围；金属凸点与引线框架通过导线连通；使其金属凸点、镀银层、铜倒角连接层与镀NiPdAu层构成电路的电源和信号通道。

可进行产品制作流程，无需过多加工框架载体，缩短设计周期，降低成本；同时降低了塑封料压力，增加了塑封料与金属框架的接合面积，封装可靠性大幅提升。

申请人：江西芯世达微电子有限公司
地址：330000 江西省南昌市临空经济区嘉和一路28号
国籍：CN
代理机构：南昌金轩知识产权代理有限公司
代理人：孙文伟
更多信息请下载全文后查看。

半导体封装工艺介绍

Lead Frame 引线框架
Die Pad 芯片焊盘 Gold Wire
金线
Epoxy 银浆
Mold Compound 环氧树脂
Sino-i Technology Ltd.
ITSM / ITIL
Raw Material in Assembly(封装原材料)
【Wafer】晶圆
……
Copyright © Sino-i Technology Limited All rights reserved
Sino-i Technology Ltd.
ITSM / ITIL
FOL– Front of Line前段工艺
Wafer
2nd Optical 第二道光检
Die Attach 芯片粘接
Back
Grinding 磨片
Wafer Wash 晶圆清洗
Epoxy Cure 银浆固化
EOL
Wafer Mount 晶圆安装
【Gold Wire】焊接金线
➢实现芯片和外部引线框架的电性和物理连接；
➢金线采用的是99.99%的高纯度金； ➢同时，出于成本考虑，目前有采用铜
线和铝线工艺的。优点是成本降低，同时工艺难度加大，良率降低； ➢线径决定可传导的电流；0.8mil， 1.0mil，1.3mils，1.5mils和2.0mils ；
Copyright © Sino-i Technology Limited All rights reserved
陶瓷封装
金属封装
Sino-i Technology Ltd.
ITSM / ITIL
IC Package （IC的封装形式）
• 按与PCB板的连接方式划分为：

半导体封装流程

LF In
Solder Wire
Heater
Spanking
2. Spanker moves downwards and press onto the molten solder to make a rectangular
solder pattern
collet
Die Bonding
3. Bond arm transfers the afer】
封装的材料
料盒及框架的展示：
封装的材料
塑封料【 Mold Compound 】
主要成分为：环氧树脂及各种添加剂（固化剂，改性剂，脱模剂，染色剂，阻燃剂等）；主要功能为：在熔融状态下将Die和Lead Frame包裹起来，提供物理和电气保护，防止外界干扰；存放条件：0—5°保存，常温下需回温24小时；
17
工艺流程
Die Attach【芯片粘接】
Before Die Attach
After Die Attach
工艺流程
Wire Bonding 【引线焊接】
目的：Lead Frame 上的Chip 与LF之间用Al Wire
定义：主要根据钎料的熔点温度来区分的，一般熔点在450℃一下的焊料叫做软焊料；把熔点在450℃以上的焊料叫做硬焊料。
主用焊料：Sn 5% Pb92.5%Ag2.5% 熔点：287℃—294℃之间物理特性：
良好的导热和导电性能；低的导通电阻 Rds(on) 熔点高；工作温度高；热膨胀系数和高强度焊接强度高耐振动；疲劳寿命时间长耐冷热循环变形的能力强
工艺流程
Die Saw 【晶圆切割】
目的：通过Saw Blade将整片Wafer切割成一个个独立的Dice，

半导体封装工艺介绍 LN

• 按封装外型可分为： SOT 、QFN 、SOIC、TSSOP、QFP、BGA、CSP等；
封装形式和工艺逐步高级和复杂
• 决定封装形式的两个关键因素: ➢ 封装效率。芯片面积/封装面积，尽量接近1:1； ➢ 引脚数。引脚数越多，越高级，但是工艺难度也相应增加；
其中，CSP由于采用了Flip Chip技术和裸片封装，达到了芯片面积/封装面积=1:1，为目前最高级的技术；
2020/6/12
IC Package （IC的封装形式）
• 按封装材料划分为：
塑料封装
陶瓷封装
金属封装主要用于军工或航天技术，无商业化产品；
陶瓷封装优于金属封装，也用于军事产品，占少量商业化市场；
塑料封装用于消费电子，因为其成本低，工艺简单，可靠性高而占有绝大部分的市场份额；
2020/6/12
➢指芯片（Die）和不同类型的框架（L/F）和塑封料（EMC）形成的不同外形的封装体。
➢IC Package种类很多，可以按以下标准分类：
• 按封装材料划分为：金属封装、陶瓷封装、塑料封装
• 按照和PCB板连接方式分为： PTH封装和SMT封装
• 按照封装外型可分为： SOT、SOIC、TSSOP、QFN、QFP、BGA、CSP等；
BGA采用的是Substrate；
2020/6/12
Raw Material in Assembly(封装原材料)
【Gold Wire】焊接金线
➢实现芯片和外部引线框架的电性和物理连接；
➢金线采用的是99.99%的高纯度金； ➢同时，出于成本考虑，目前有采用铜
线和铝线工艺的。优点是成本降低，同时工艺难度加大，良率降低； ➢线径决定可传导的电流；0.8mil， 1.0mil，1.3mils，1.5mils和2.0mils；

电子元器件含银、含铜信息披露以及硫化试验反馈表模版

電子元器件含银、含铜信息披露
以及硫化试验反馈
1. 材料含银、含铜信息披露
2. 硫化试验要求
说明：如果材料含铜、银，需要进行硫磺熏蒸试验。

如果不含铜、银，则不需要试验。

对于电阻、磁珠、接点开关类材料按照我司硫化失效标准开展，其他含银、含铜材料按照硫化熏蒸试验开展。

2.1 我司已有硫化试验标准要求
按我司标准执行 2.2 硫磺熏蒸试验要求
1）硫磺熏蒸试验环境要求：将30g 升华硫置于40L 玻璃器皿底部，试验样本置于玻璃器皿托架上，密闭玻璃器皿，通过温箱加热进行试验。

2）硫磺熏蒸试验条件：
试验温度：105℃（+5/-0℃）试验时间：720h
测试要求：如果器件需要使用回流焊，则实验前需要进行3次回流焊预处理，然后在开展硫磺熏蒸实验。

测试时间点为48h 、96h 、168h 、360h 、720h
测试内容：检测是否存在腐蚀迹象；测量引脚之间漏电情况，测试器件功能、性能（若能测试）。

样本数量：12pcs
试验判据：样品功能、性能满足规格书要求 3）硫磺熏蒸试验结果：
试验数据：
Silver and。

PPF框架在半导体工业中的应用

PPF框架在半导体工业中的应用李庆生【摘要】随着半导体工业绿色封装的不断兴起,无铅化(Pb-free)也越来越成为业界的共识.为了彻底贯彻于2006年7月1日正式生效的欧盟RoHS指令,全球的电子OEM生产商,特别是那些目标客户是欧美和日本的生产商,必须具备完全的绿色产品生产能力.在国内集成电路生产领域,有的生产商尝试利用纯锡(Sn)来代替锡铅(SnPb)合金;还有一部分采用镍钯金(NiPdAu)以及希望利用锡铋合金(SnBi)或锡铜合金(SnCu)来替锡铅(SnPb)合金.文章主要介绍在封装过程中的绿色材料替换方法以及由此带来的挑战和风险.重点阐述了基于镍钯金(NiPdAu)PPF框架(Pre-plated leadframes)在半导体工业应用中的优势和特点.【期刊名称】《电子与封装》【年(卷),期】2010(010)003【总页数】5页(P36-39,43)【关键词】RollS指令;PPF框架;绿色封装;半导体工业【作者】李庆生【作者单位】铜陵三佳山田科技有限公司技术部,安徽,铜陵,244000【正文语种】中文【中图分类】TN305.941 引言2003年1月27日，欧盟议会和欧盟理事会通过了2002/95/EC指令，即“在电子电气设备中限制使用某些有害物质指令”（The Restriction of the use of Certain Hazardous Substances in Electrical and Electronic Equipment），简称RoHS指令。

基本内容是：从2006年7月1日起，在新投放市场的电子电气设备产品中，限制使用铅、汞、镉、六价铬、多溴联苯（PBB）和多溴二苯醚（PBDE）等六种有害物质。

RoHS指令发布以后，从2003年2月13日起成为欧盟范围内的正式法律； 2006年7月1日以后，欧盟市场上将正式禁止六类物质含量超标的产品进行销售。

PPF框架的开发是为了适应无铅化的工艺流程而开发的一种新型的封装用材料，主要目的是避免在电路打线和装配过程中使用含铅焊料。

SY69753LHG TR;SY69753LHG;SY69753LHI;SY69753LHI TR;中文规格书,Datasheet资料

SY69753L3.3V, 125Mbps, 155Mbps Clockand Data RecoveryUse lower-power SY69753AL for new designs Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • General DescriptionThe SY69753L is a complete Clock Recovery and DataRetiming integrated circuit for OC-3/STS-3 applicationsat 155Mbps NRZ. The device is ideally suited forSONET/SDH/ATM applications and other high-speeddata transmission systems.Clock recovery and data retiming is performed bysynchronizing the on-chip VCO directly to the incomingdata stream. The VCO center frequency is controlled bythe reference clock frequency and the selected divideratio. On-chip clock generation is performed through theuse of a frequency multiplier PLL with a byte rate sourceas reference.The SY69753L also includes a link fault detection circuit.Datasheets and support documentation can be found onMicrel’s web site at: .Features• 3.3V power supply•SONET/SDH/ATM compatible•Clock and data recovery for 125Mbps/155Mbps NRZdata stream•Two on-chip PLLs: one for clock generation andanother for clock recovery•Selectable reference frequencies•Differential PECL high-speed serial I/O•Line receiver input: no external buffering needed•Link fault indication•100k ECL compatible I/O•Industrial temperature range (–40°C to +85°C)•Complies with Bellcore, ITU/CCITT and ANSIspecifications for OC-3 applications•Available in 32-pin EPAD-TQFPApplications•Ethernet media converter(m)•SONET/SDH/ATM OC-3•Proprietary architecture at 135Mbps to 180MbpsOrdering Information(1)Part Number PackageType OperatingRangePackageMarkingLeadFinishSY69753LHI H32-1Industrial SY69753LHI Sn-Pb SY69753LHITR(2)H32-1Industrial SY69753LHI Sn-PbSY69753LHG(3)H32-1Industrial SY69753LHG withPb-Free bar-line indicator NiPdAu Pb-FreeSY69753LHGTR(2, 3)H32-1Industrial SY69753LHG withPb-Free bar-line indicator NiPdAu Pb-FreeNotes:1. Contact factory for die availability. Dice are guaranteed at T A = 25°C, DC Electricals only.2. Tape and Reel.3. Recommended for new designs.Pin Configuration32-Pin EPAD-TQFP (H32-1)Pin DescriptionInputsPin Number Pin Name Type Pin Name2 3RDINPRDINNDifferentialPECLSerial Data Input: These built-in line receiver inputs are connected to the differentialreceive serial data stream. An internal receive PLL recovers the embedded clock(RCLK) and data (RDOUT) information.5REFCLK TTL Input Reference Clock: This input is used as the reference for the internal frequencysynthesizer and the "training" frequency for the receiver PLL to keep it centered in theabsence of data coming in on the RDIN inputs.26CD PECLInput Carrier Detect: This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH, the input data stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be internally forced to a constant LOW, the data outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW and the clock recovery PLL forced to look onto the clock frequency generated from REFCLK.32 25DIVSEL1DIVSEL2TTL Input Divider Select: These inputs select the ratio between the output clock frequency(RCLK/TCLK) and the REFCLK input frequency as shown in the “Reference FrequencySelection” table.16CLKSEL TTL Input Clock Select: This input is used to select either the recovered clock of the receiver PLL(CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to theTCLK outputs.OutputsPin Number Pin Name Type Pin Name31LFIN TTLOutput Link Fault Indicator: This output indicates the status of the input data stream RDIN. Active HIGH signal is indicating when the internal clock recovery PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the Receive PLL (1000ppm) and will be alternating if not. LFIN is an asynchronous output.23 24RDOUTNRDOUTPDifferentialPECLReceive Data Output: These ECL 100K outputs represent the recovered data from theinput data stream (RDIN). This recovered data is specified against the rising edge ofRCLK.20 21RCLKNRCLKPDifferentialPECLClock Output: These ECL 100K outputs represent the recovered clock used to samplethe recovered data (RDOUT).18 17TCLKPTCLKNDifferentialPECLClock Output: These ECL 100K outputs represent either the recovered clock (CLKSEL= HIGH) used to sample the recovered data (RDOUT) or the transmit clock of thefrequency synthesizer (CLKSEL = LOW).9 10PLLSPPLLSNClock Synthesis PLL Loop Filter: External loop filter pins for the clock synthesis PLL.14 15PLLRNPLLRPClock Recovery PLL Loop Filter: External loop filter pins for the receiver PLL.Power and GroundPin Number Pin Name Type Pin Name27, 28VCC Power Supply.(1)29, 30VCCA Analog Power Supply Voltage.(1) 19, 22VCCO Output Supply Voltage.(1)12, 13GND Ground.1, 4, 6, 7, 8NC No connect.11GNDA Analog Ground.Note:1.VCC, VCCA, VCCO must be the same value.Absolute Maximum Ratings(1)Supply Voltage (V CC)......................................-0.5V to +5.0V Input Voltage (V IN)..............................................-0.5V to V CC Output Current (I OUT)Continuous...........................................................±50mA Surge..................................................................±100mA Lead Temperature (soldering, 20sec.).....................+260°C Storage Temperature (T s)..........................-65°C to +150°C Operating Ratings(2)Input Voltage (V CC)..............................+3.15V to +3.45V Ambient Temperature (T A).....................–40°C to +85°C Junction Temperature (T J)....................................+125°C Package Thermal Resistance(3)EPAD-TQFP (θJA)Still-air.......................................................28°C/W500lfpm.....................................................20°C/W EPAD-TQFP (θJC).............................................4°C/WDC Electrical CharacteristicsT A = –40°C to +85°C, unless otherwise noted.Symbol Parameter Condition Min Typ Max Units V CC Power Supply Voltage 3.15 3.3 3.45V I CC Power Supply Current170230mAPECL 100K DC Electrical CharacteristicsV CC = V CCO = V CCA = 3.3V ±5%; T A = –40°C to +85°C, unless otherwise noted.Symbol Parameter Condition Min Typ Max Units V IH Input HIGH Voltage V CC-1.165V CC-0.880V V IL Input LOW Voltage V CC-1.810V CC-1.475V V OH Output HIGH Voltage50Ω to V CC-2V V CC-1.075V CC-0.830V V OL Output LOW Voltage50Ω to V CC-2V V CC-1.860V CC-1.570V I IL Input LOW Current V IN = V IL (Min)0.5µATTL DC Electrical CharacteristicsV CC = V CCO = V CCA = 3.3V ±5%; T A = –40°C to +85°C, unless otherwise noted.Symbol Parameter Condition Min Typ Max Units V IH Input HIGH Voltage 2.0V CC V V IL Input LOW Voltage0.8V V OH Output HIGH Voltage I OH = -0.4mA 2.0V V OL Output LOW Voltage I OL = 4mA0.5VI IH Input HIGH Current V IN = 2.7V, V CC = Max.V IN = V CC, V CC = Max.-125+100µAµAI IL Input LOW Voltage V IN = 0.5V, V CC = Max.-300µA I OS Output Short Circuit Current V OUT = 0V, (max., 1 sec.)-15-100mA Notes:1.Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is notimplied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.2.The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.3.Numbers valid with proper thermal design of PCB and exposed pad soldered to island on PCB. Refer to Figure on page 13.AC Electrical CharacteristicsV CC = V CCO = V CCA = 3.3V ±5%; T A = –40°C to +85°C, unless otherwise noted.Symbol Parameter Condition Min Typ Max Units f VCO VCO Center Frequency f REFCLK x Byte Rate8001250MHzNominal5%Δf VCO VCO Center FrequencyTolerancet ACQ Acquisition Lock Time50Ω to V CC-2V15µs t CPWH REFCLK Pulse Width HIGH50Ω to V CC-2V4ns t CPWL REFCLK Pulse Width LOW V IN = V IL (Min)4ns t DV Data Valid1/(2xf RCLK) -200ps t DH Data Hold1/(2xf RCLK) -200ps t ir REFCLK Input Rise Time0.52ns t ODC Output Duty Cycle (RCLK/TCLK)4555% ofUI t RSKEW Recovered Clock Skew-200+200ps t r, t f ECL Output Rise/Fall Time50Ω to V CC-2100400ps (20% to 80%)Timing WaveformsFunctional BlockFunctional DescriptionClock RecoveryClock Recovery, as shown in the block diagram, generates a clock that is at the same frequency as the incoming data bit rate at the Serial Data input. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern.The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency detector. Output pulses from the detector indicate the required direction of phase correction. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock.Frequency stability, without incoming data, is guaranteed by an alternate reference input (REFCLK) that the PLL locks onto when data is lost. If the Frequency of the incoming signal varies by greater than approximately 1000ppm with respect to the synthesizer frequency, the PLL will be declared out of lock, and the PLL will lock to the reference clock.The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. This transfer function yields a 30µs data stream of continuous 1's or 0's for random incoming NRZ data.The total loop dynamic of the clock recovery PLL provides jitter tolerance which is better than the specified tolerance in GR-253-CORE.Lock DetectThe SY69753L contains a link fault indication circuit, which monitors the integrity of the serial data inputs. If the received serial data fails the frequency test, then the PLL will be forced to lock to the local reference clock. This will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions. If the recovered clock frequency deviates from the local reference clock frequency by more than approximately 1000ppm, the PLL will be declared out of lock. The lock detect circuit will poll the input data stream in an attempt to reacquire lock to data. If the recovered clock frequency is determined to be within approximately 1000ppm, the PLL will be declared in lock and the lock detect output will go active.PerformanceThe SY69753L PLL complies with the jitter specifications proposed for SONET/SDH equipment defined by the Bellcore Specifications: GR-253-CORE, Issue 2, December 1995 and ITU-T Recommendations: G.958 document, when used with differential inputs and outputs.Input Jitter ToleranceInput jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1dB optical/electrical power penalty. SONET input jitter tolerance requirement condition is the input jitter amplitude thatcauses an equivalent of 1dB power penalty.OC/STS-N Levelf0(Hz)f1(Hz)f2(Hz)f3(Hz)ft(Hz)310303006.565Figure 1. Input Jitter ToleranceJitter TransferJitter transfer function is defined as the ratio of jitter on the output OC-N/STS-N signal to the jitter applied on the input OC-N/STS-N signal versus frequency. Jitter transfer requirements are shown in Figure 2.Jitter GenerationThe jitter of the serial clock and serial data outputs shall not exceed .01 U.I. rms when a serial data input with no jitter is presented to the serial data inputs.OC/STS-N Levelfc (kHz)P (dB)31300.1Figure 2. Jitter TransferLoop Filter Components (1)R1 = 350ΩC1 = 1.5µF (X7R Dielectric)R2 = 680ΩC2 = 1.0µF (X7R Dielectric)Note:1.Suggested values. Values may vary for different applications.Reference Frequency SelectionDIVSEL1DIVSEL2f RCLK /f REFCLK008011010161120Application ExampleNote:C3, C4 are optional.C1 = 1.5µFC2 = 1.0µFR1 = 350ΩR2 = 680ΩR3 through R10 = 5kΩR12 = 12kΩR13 = 130ΩBill of MaterialsItem Part Number Manufacturer Description Qty. C1ECU-V1H104KBW Panasonic(1) 1.5µF Ceramic Capacitor, Size 1206, X7R Dielectric,Loop Filter, Critical1C2ECU-V1H104KBW Panasonic(1) 1.0µF Ceramic Capacitor, Size 1206, X7R Dielectric,Loop Filter, Critical1C3, C4ECU-V1H104KBW Panasonic(1)0.47µF Ceramic Capacitor, Size 1206, X7R Dielectric,Loop Filter, Optional2 C5ECS-T1ED226R Panasonic(1)22µF Tantalum Electrolytic Capacitor, Size D1 C6ECU-V1H104KBW Panasonic(1)0.1µF Ceramic Capacitor, Size 1206, X7R DielectricPower Supply Decoupling1 C7, C8, C9, C10ECS-T1EC685R Panasonic(1) 6.8µF Tantalum Electrolytic Capacitor, Size C4 C19ECJ-3YB1E105K Panasonic(1)0.1µF Ceramic Capacitor, Size 1206, X7R DielectricVEEA Decoupling1C11, C13ECU-V1H104KBW Panasonic(1)0.1µF Ceramic Capacitor, Size 1206, X7R DielectricVCCO/VCC Decoupling1C15, C17ECU-V1H104KBW Panasonic(1)0.1µF Ceramic Capacitor, Size 1206, X7R DielectricVCCA/VEEA Decoupling1C20ECU-V1H104KBW Panasonic(1)0.1µF Ceramic Capacitor, Size 1206, X7R DielectricVEEA Decoupling1C12, C14ECU-V1H103KBW Panasonic(1)0.01µF Ceramic Capacitor, Size 1206, X7R DielectricVCCO/VCC Decoupling1C16, C18ECU-V1H103KBW Panasonic(1)0.01µF Ceramic Capacitor, Size 1206, X7R DielectricVCCA/VEEA Decoupling1C21ECU-V1H103KBW Panasonic(1)0.01µF Ceramic Capacitor, Size 1206, X7R DielectricVEEA Decoupling1 D11N4148Diode1 D2P300-ND/P301-ND Panasonic(1)T-1 3/4, Red LED1J1, J2, J3, J4, J5, J6, J7, J8, J9,J10, J11, J12142-0701-851JohnsonComponents(2)Gold Plated, Jack, SMA, PCB Mount12L1, L2, L3BLM21A102F Murata(3)Ferrite Beads, Power Noise Suppression3 Q1NTE123A NTE(4)2N2222A Buffer/Driver Transistor, NPN1 R1350Ω Resistor, 2%, Size 1206, Loop Filter Component,Critical1R2680Ω Resistor, 2%, Size 1206, Loop Filter Component,Critical1R3, R4, R5, R6,R7, R8, R9, R105kΩ Pull-up Resistor, 2%, Size 12068 R111kΩ Pull-down Resistor, 2%, Size 12061 R1212kΩ Resistor, 2%, Size 12061 R13130Ω Pull-up Resistor, 2%, Size 12061 SW1206-7CTS(5)SPST, Gold Finish, Sealed Dip Switch1 Notes:1. Panasonic: .2. Johnson Components: .3. Murata: .4.NTE: .5.CTS: .分销商库存信息:MICRELSY69753LHG TR SY69753LHG SY69753LHI SY69753LHI TR。