电子设计自动化基础- 7综合基础知识

Specifying Combinational Path Delay
For purely combinational delays that are not bounded by a clock period
cell ( OR2_3 ) { Cell name area : 8.000 ; Cell Area pin ( Y ) { direction : output; timing ( ) { related_pin : "A" ; timing_sense : positive_unate ; rise_propagation (drive_3_table_1) { values ("0.2616, 0.2608, 0.2831,..) } rise_transition (drive_3_table_2) { values ("0.0223, 0.0254, ...) . . . . function : "(A | B)"; max_capacitance : 1.14810 ; min_capacitance : 0.00220 ; } pin ( A ) { direction : input; capacitance : 0.012000; . . . .
The transition time of a net is the time required for its driving pin to change logic values.

Design Compiler calculates the transition time for each net by multiplying the drive resistance of the driving pin by the sum of the capacitive loads connected to the driving pin.
Setting Design Rule Constraints
the most commonly specified design rule constraints:

Transition time Fanout load Capacitance
Setting Transition Time Constraints
Setting Capacitance Constraints
The transition time constraints do not provide a direct way to control the actual capacitance of nets.

The set_max_capacitance command sets a maximum capacitance for the nets attached to the named ports or to all the nets in a design by setting the max_capacitance attribute on the specified objects.
unmapped my_chip.db
scripts
mapped my_chip.db my_chip.edif
constraints.tcl
TRANSLATION
OPTIMIZATION + MAPPING
工艺库
Example of a cell description in .lib Format
set_output_delay
TO_BE_SYNTHESIZED D
U3
Clk
Clock (50 MHz)
Q
S
B
EXTERNAL CIRCUIT
Setup Requirement: 7.0 ns
create_clock -period 20 [get_ports Clk]
set_dont_touch_network [get_clocks Clk] set_output_delay -max 7.0 -clock Clk [get_ports B]
Setting Fanout Load Constraints
The maximum fanout load for a net is the maximum number of loads the net can drive.

The fanout load value does not represent capacitance; it representsthe weighted numerical contribution to the total fanout load.
Virtual Clock:


Clock Network Delay
Clock Network Delay


By default, Design Compiler assumes that clock networks have no delay (ideal clocks). Use the set_clock_skew command to specify timing information about the clock network delay(either estimated or actual delay) Use the -propagated option: specify that you want Design Compiler to calculate clock network delay by propagating times through the clock network.
模块综合过程
GTECH target_library
gtech.db
core_slow.db
my_chip.v(hd)
read_vhdl HDL source read_verilog analyze/ elaborate
DC_MEMORY Y=A+B MY_CHIP compile
DC_MEMORY MY_CHIP source

Use the -plus_uncertainty ( -minus_uncertainty) options: to add some margin of error into the system to account for variances in the clock network resulting from layout.
t
A Y=A|B B Y
Pin A -> Pin Y nominal delays (look-up table)
Pin Y functionality Design Rules for Output Pin Electrical Characteristics of Input Pins
设计目标
定义时钟
User MUST Define: Clock Source (port or pin) Clock Period User may also define: Duty Cycle Offset/Skew Clock Name
TO_BE_SYNTHESIZED
Clk Period Clk
Cell
REGFILE U4 (.D0 (INV0), .D1 (INV1), .CLK (CLK) ); endmodule
设计目标
Design
TOP Port
A B C D A B C D
Cell
Net
U4
U1
AIN BIN CIN DIN Q0
BUS0
BUS1
U2 INV U3 INV
INV0
同步设计（Synchronous Design）
TO_BE_SYNTHESIZED
D Q FF1 QB M N D Q FF2 QB X D Q FF3 QB S T D Q FF4 QB
Clk
What information must you provide to constrain all the register-to-register paths in your design?
Design module TOP (A,B,C,D,CLK,OUT1); input A, B, C, D, CLK; output [1:0] OUT1; Port wire INV1,INV0,bus1,bus0;
Clock
Net
ENCODER U1 (.AIN (A), . . . .Q1 (bus1)); Reference INV U2 (.A (BUS0), .Z( INV0)), U3 (.A( BUS1), .Z( INV1)); Pin
D0
Q[1:0]
OUT[1:0]
INV1 D1 CLK REGFILE
Pin
Q1
Clock
CLK
CLK
ENCODER
Reference and Design
Designs: {TOP, ENCODER, REGFILE} References: {ENCODER, REGFILE , INV} Cells: {U1, U2, U3, U4}
综合基本知识
李晓明
内容
模块综合过程 关键约束介绍 约束文件实例 DC图形界面
综合的过程
Synthesis = Translation + Optimization + Mapping
residue = 16’h0000; if (high_bits == 2’b10) residue = state_table[index]; else state_table[index] = 16’h0000;