LED灯移位显示,ise开发环境Verilog编程流水灯

DDPP课程设计
八位LED可控移位显示设计与实现
本设计基于Xilinx ISE Design Suite 13.2软件开发平台和其综合工具进行八位LED可控移位显示数字电路的功能设计，在FPGA BSSYS2开发板上来完成设计的测试和实现。

I、总体RTL SCHEMATIC
端口说明：
CLK_IN：50MHZ时钟输入
C：控制左右移，0为
LED[0]-LED[7]，1反之。

S：选择移动频率，共四档。

RST：重置
LED：点亮LED灯
II、源程序
module led_shiftingdisplay(LED,CLK_IN,RST,S,C);
input CLK_IN,RST,C;
input [1:0] S;
output [7:0] LED;
reg [25:0] cn;
reg CLK;
reg [7:0] LED;
wire CLK_OUT;
wire CLK2_OUT;
wire CLK3_OUT;
wire CLK4_OUT;
initial
begin
cn=0;
end
always @(posedge CLK_IN)
begin
if(cn==49999999)
begin cn<=0; end
else cn<=cn+26'd1;
end
assign CLK_OUT=cn[25]; //1HZ
assign CLK2_OUT=cn[24]; //2HZ
assign CLK3_OUT=cn[21]; //16HZ
assign CLK4_OUT=cn[20]; //32HZ
always @(S,CLK_OUT,CLK2_OUT,CLK3_OUT,CLK4_OUT) begin
case(S)
2'd0:CLK<=CLK_OUT;
2'd1:CLK<=CLK2_OUT;
2'd2:CLK<=CLK3_OUT;
2'd3:CLK<=CLK4_OUT;
endcase
end
initial begin LED=8'b00000000;end
always @(posedge CLK)
begin
if(C) //C==1,left shifting if(RST) LED<=8'b00000001;
else if(LED==8'b00000000)
LED<=8'b00000001;
else LED<=LED<<1;
else //C==1,right shifting if(RST) LED<=8'b10000000;
else if(LED==8'b00000000)
LED<=8'b10000000;
else LED<=LED>>1;
end
endmodule
III、用户约束文件led_shiftingdisplay.v
NET "C" LOC = N3;
NET "CLK_IN" LOC = B8;
NET "LED[0]" LOC = M5;
NET "LED[1]" LOC = M11;
NET "LED[2]" LOC = P7;
NET "LED[3]" LOC = P6;
NET "LED[4]" LOC = N5;
NET "LED[5]" LOC = N4;
NET "LED[6]" LOC = P4;
NET "LED[7]" LOC = G1;
NET "RST" LOC = A7;
NET "S[0]" LOC = P11;
NET "S[1]" LOC = L3;
# PlanAhead Generated IO constraints
NET "C" IOSTANDARD = LVCMOS33;
NET "CLK_IN" IOSTANDARD = LVCMOS33; NET "LED[0]" IOSTANDARD = LVCMOS33; NET "LED[1]" IOSTANDARD = LVCMOS33; NET "LED[2]" IOSTANDARD = LVCMOS33; NET "LED[3]" IOSTANDARD = LVCMOS33; NET "LED[4]" IOSTANDARD = LVCMOS33; NET "LED[5]" IOSTANDARD = LVCMOS33; NET "LED[6]" IOSTANDARD = LVCMOS33; NET "LED[7]" IOSTANDARD = LVCMOS33; NET "RST" IOSTANDARD = LVCMOS33; NET "S[0]" IOSTANDARD = LVCMOS33; NET "S[1]" IOSTANDARD = LVCMOS33;
IV、程序仿真
测试文件led_shiftingdisplay.v
module test_ledshiftingdisplay;
reg CLK_IN;
reg RST;
reg [1:0] S;
reg C;
wire [7:0] LED;
led_shiftingdisplay uut (
.LED(LED),
.CLK_IN(CLK_IN),
.RST(RST),
.S(S),
.C(C)
);
parameter PERIOD = 20;
initial
begin
CLK_IN = 1'b0;
#10;
forever
#(PERIOD/2) CLK_IN = ~CLK_IN;
end
initial begin
RST = 0;
S = 3;
C = 1;
end
endmodule
仿真波形：
各个信号仿真波形正常，唯有LED[7:0]均为高阻态（除最低位外），仿真不成功，不得其解。