eda数字钟程序及波形仿真图
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部件一：60进制程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CLOCK60 IS
PORT( CLK: IN STD_LOGIC; ---时钟信号NRESET: IN STD_LOGIC; ---复位端
LOAD: IN STD_LOGIC; ---置数端
D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); ---输入端
CI:IN STD_LOGIC; ---始能端
CO: OUT STD_LOGIC; ---进位脉冲
QH: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
QL: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
END CLOCK60;
ARCHITECTURE ARTCLOCK60 OF CLOCK60 IS
BEGIN
CO<='1'WHEN(QH="0101" AND QL="1001" AND CI='1')ELSE'0';----进位输出PROCESS(CLK,NRESET)
BEGIN
IF(NRESET='0')THEN -----异步复位
QH<="0000";
QL<="0000";
ELSIF(CLK'EVENT AND CLK='1')THEN------同步置数
IF(LOAD='1')THEN
QH<=D(7 DOWNTO 4);
QL<=D(3 DOWNTO 0);
ELSIF(CI='1')THEN
IF(QL=9)THEN
QL<="0000";
IF(QH=5)THEN
QH<="0000";
ELSE
QH<=QH+1;
END IF;
ELSE
QL<=QL+1;
END IF;
END IF;
END IF;
END PROCESS;
END ARTCLOCK60;
60进制波形图如下：
部件二：24进制程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CLOCK24 IS
PORT( CLK: IN STD_LOGIC; ---时钟信号NRESET: IN STD_LOGIC; ---复位端
LOAD: IN STD_LOGIC; ---置数端
D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); ---输入端
CI:IN STD_LOGIC; ---始能端
CO: OUT STD_LOGIC; ---进位脉冲
QH: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
QL: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
END CLOCK24;
ARCHITECTURE ARTCLOCK24 OF CLOCK24 IS
BEGIN
CO<='1'WHEN(QH="0101" AND QL="1001" AND CI='1')ELSE'0';----进位输出PROCESS(CLK,NRESET)
BEGIN
IF(NRESET='0')THEN -----异步复位
QH<="0000";
QL<="0000";
ELSIF(CLK'EVENT AND CLK='1')THEN------同步置数
IF(LOAD='1')THEN
QH<=D(7 DOWNTO 4);
QL<=D(3 DOWNTO 0);
ELSIF(CI='1')THEN
IF(QL=9 or (QH=2 AND QL=3))THEN
QL<="0000";
IF(QH=2)THEN
QH<="0000";
ELSE
QH<=QH+1;
END IF;
ELSE
QL<=QL+1;
END IF;
END IF;
END IF;
END PROCESS;
END ARTCLOCK24;
24进制的波形图如下：
数字钟的全部程序如下：
LIBRARY IEEE; ---秒信号USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CLOCK60s IS
PORT( CLK: IN STD_LOGIC; ---时钟信号NRESET: IN STD_LOGIC; ---复位端
LOAD: IN STD_LOGIC; ---置数端
D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); ---输入端
CI:IN STD_LOGIC; ---始能端
CO: OUT STD_LOGIC; ---进位脉冲
QH: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
QL: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
END CLOCK60s;
ARCHITECTURE ARTCLOCK60s OF CLOCK60s IS
BEGIN
CO<='1'WHEN(QH="0101" AND QL="1001" AND CI='1')ELSE'0'; --进位输出PROCESS(CLK,NRESET)
BEGIN
IF(NRESET='0')THEN ---异步复位
QH<="0000";
QL<="0000";
ELSIF(CLK'EVENT AND CLK='1')THEN --同步置数
IF(LOAD='1')THEN
QH<=D(7 DOWNTO 4);
QL<=D(3 DOWNTO 0);
ELSIF(CI='1')THEN
IF(QL=9)THEN
QL<="0000";