简易倍频放大电路课程设计

课程设计报告

电路与电子技术课程设计

简易倍频发大电路的设计与制作学生姓名

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二〇一三年六月

课程设计任务书

简易倍频放大电路的设计与制作

内容摘要：倍频放大电路实际上就是将输入信号频率成整数倍（2

倍、3倍……n倍）增加的电路。它主要用于甚高频无线电发射机或其它电子设增加的电路。随着现代通信技术的日益发展，倍频技术应用的领域也越来越广。实现倍频主要有三种方法：傅里叶法，锁相环法，参量法.传统倍频电路利用R C微分电路和施密特触发与非门分别检出脉冲的上升沿和下降沿，然后经过一个输入端或门叠加输出。电路能够完成信号的倍频工作，但实现起来比较繁琐，电路工作稳定性差。

为克服上述电路设计方法的缺陷，便于电路调试，我设计了一种全数字型倍频电路。在此电路中，输入脉冲由A点输入，由时钟C LK上升沿打入D触发器1，D触发器1输出信号B，B信号在下一个时钟的上升沿被打入下一级D触发器2，D触发器2输出信号C，再将B、C信号异或，即可得到脉冲宽度为一个时钟周期的倍频信号。采用这种方法实现的电路输出信号的脉冲宽度可由输入时钟周期的大小随意调节，唯一的要求是时钟的频率要大于两倍的输入信号的频率。

关键词：倍频电路数字型时钟CLK D触发器

Design and manufacture of a kind of simple Multiple

frequency amplifier

Abstract：Frequency amplifier circuit is actually the frequency of the input signal into integer (2 times, 3 times， N times) increased circuit. It is mainly used for VHF radio transmitter or other electronic equipment to increase the circuit. With the development of modern communication technology, the application of frequency doubling technology becomes more and more wide. Realization of frequency has mainly three kinds of methods: Fourier method, PLL, parametric method. The traditional frequency multiplier circuit using RC differential circuit and Schmidt trigger NAND

gate were rising and falling edge of pulse, and then through an input or output. The circuit can complete the work of the signal of frequency multiplication, it is more tedious, circuit stability.

In order to overcome the defect in the circuit design method, and let it be convenient for circuit debugging, I design a digital frequency multiplier circuit. In this circuit, Inputting the input pulse by the A point, along into the D flip-flop 1 by the leading-edge clock CLK, D flip-flop 2 output signal B, signal B rise on the next clock edge into the next level of D 2 triggers, D flip-flop 2 output signal C, then signal B and signal C would be obtained by XOR, pulse width of frequency doubling signal clock cycle a. The pulse width circuit output signal of realization of this method can be freely adjusted the size of input clock cycle, the only requirement is the input clock frequency must be greater than two times the frequency.

Keywords：clock multiplier amplifier circuit clock CLK D flip-flop digital

目录

前言 (5)

1倍频的3种方法 (5)

1.1傅里叶法 (5)

1.2锁相环法 (6)

1.3参量法 (7)

2 钟控D触发器 (8)

2.1电路组成和工作原理 (9)

2.2功能描述 (9)

3主要芯片介绍 (11)

3.1 74LS375简介 (11)

3.1.1引出端符号： (11)

3.1.2外接管腿： (11)

3.1.3逻辑图如下 (12)

3.1.4功能表： (12)

3.1.5推荐工作条件 (12)

3.1.6静态特性（TA为工作环境温度范围） (12)

4电路原理 (13)

4.1传统倍频电路的缺陷 (13)

4.2全新数字型倍频电路 (14)

5电路的组装和调试 (15)

5.1电路的组装 (15)

5.2整机的布线存在 (15)

6结束语 (16)

附录： (18)

附录1设计需要的仪器和元件 (18)

附录2实物图 (18)

参考文献： (19)