学习使用Cadence设计原理图共29页
第二章Cadence的原理图设计
第二章 Cadence的原理图设计2.1Design Entry CIS软件概述Cadence软件系统有两套电路原理图的设计工具，一套是Design Entry HDL，另一套就是我们马上要开始学习的Design Entry CIS。
其中Design Entry HDL 是Cadence公司原本的原理图设计软件，可以用于芯片电路和板级电路的设计，其长处在于可以把芯片的电路原理图和板级电路原理图结合在一起，进行综合设计；而Design Entry CIS主要用于常规的板级电路设计，Design Entry CIS原本是OrCAD公司的产品，OrCAD公司后来被Cadence公司收购，于是Design Entry CIS也就成了Cadence公司的另一套电路原理图设计软件。
Design Entry CIS原理图设计软件的特点是直观、易学、易用，在业界有很高的知名度，利用Design Entry CIS原理图设计软件可以进行简单的（只有单张图纸构成的）电路原理图设计，也可以进行（由多张图纸拼接而成的）平坦式电路原理图设计，还可以进行（多张图纸按一定层次关系构成的）层次式电路原理图设计。
在本章中，我们首先学习简单的电路原理图设计，然后再学习较为复杂的平坦式和层次式电路原理图设计。
我们将围绕一块非常简单的STC系列单片机下载电路板，学习简单电路原理图的设计，同时在此过程中，还将学习到USB转UART串行口、STC系列单片机下载电路等方面的知识。
接着，我们将围绕一块ARM-7核心实验板，进行平坦式和层次式电路原理图的设计，而该核心板是配套于ARM-7实验箱。
在此过程中我们还将学习到嵌入式技术等方面的知识。
2.2初识Design Entry CIS一．启动Design Entry CIS我们在电脑上点击“开始→所有程序→Cadence SPB 16.2→Design Entry CIS”，如下图所示：图2-1 启动Design Entry CIS这时将弹出如下对话框：图2-2 选择工作内容在这里我们选择“OrCAD Capture CIS”一项，点击“OK”按钮后，就实际启动了Design Entry CIS，出现如下界面：图2-3 OrCAD Capture CIS软件界面与大多数软件一样，OrCAD Capture CIS软件也是以项目方式管理我们的设计文件的。
cadence学习笔记1--原理图的创建、查看等系列操作（持续更新）
cadence学习笔记1--原理图的创建、查看等系列操作（持续更新）1、亲手操作教程内容2、OrCAD Capture CIS进行原理图设计3、Cadece PCB Editor 进行PCB布局布线4、光绘文件（Artwork）制作，如何生成Gerber文件OrCAD Capture CIS与OrCAD Capture的区别元件的管理非常方便一、原理图的创建、重命名、删除1、cadence原理图的创建第一种方法：首先先选中原理图文件，然后点击菜单栏上的Design--New Schematic Page输入原理图名称第二种方法：先选中原理图文件，然后右键单击，选择New Page输入原理图名称2、删除原理图文件第一种方法：首先选择你要删除的原理图文件，然后点击菜单栏上的Edit---Delete,点击Delete之后，就会弹出下面的对话框。
点击确定之后，原理图2就删除了。
第二种方法:首先选择你要删除的原理图文件，然后鼠标右键点击Delete，如下图所示弹出如下所示,点击确定，原理图即删除。
3、cadence原理图的重命名第一种方法：选择需要更改原理图文件名的文件，然后点击菜单栏中的Design---Rename在弹出的对话框中，输入名称，点击OK即可。
第二种方法：选择需要更改原理图文件名的文件，然后右键点击Rename弹出对话框，在弹出的对话框中，输入名称，点击OK即可。
二、原理图的放大、缩小方法一: 直接按下快捷---i /o方法二：选择需要放大、缩小的原理图，然后选择菜单栏上的View---Zoom----In 放大Out 缩小方法三：按住键盘上的CTRL键，鼠标上的滑轮，向前滑动，原理图放大；向后滑动，原理图缩小。
如果原理图放的很大，可以移动滚动条进行原理图的上下左右的滚动。
也可以利用快捷键进行滚动条的移动，按住CTRL+PAGEUP，原理图向左移动；按住CTRL+PAGEDOWN，原理图向右移动；按住PAGEUP，原理图向上移动；按住PAGEDOWN，原理图向下移动。
Cadence学习笔记1__原理图
cadence学习笔记1__原理图打开Design Entry CIS或OrCAD Capture CIS组件，选择OrCAD Capture CIS（不要选择OrCAD Capture，因为少了一些东西），如果勾选了左下角的“Use as default”复选框，下次就不用选择了，如果要使用其他的部分，就在打开后点击File→Change Product，会弹出一个“Cadence Product Choices”窗口：元器件库File→New→Library新建一个库，如下图，显示了路径和默认库名library1.olb，右击选择Save As可以改变路径和库名，右击新建一个元件，可以选择New Part或者是New Part From Speadsheet，是两种不同的方式，先介绍New Part的操作。
右击选择New Part后，弹出下面的对话框，在Name中填入元件名，还可以指定PCB Footprint，下面Parts per Pkg表示这个元件有几部分，1表示普通的元件，如果元件是两部分组成的分裂元件就写2，这里先操作1，点击ok。
中间的虚线框是这个元件的区域，右边会有一个工具栏，画直线、方框、圆、曲线，也可以输入一些字符，或者点放置一组引脚，放置结束后鼠标右击选择End Mode或按键盘左上角Esc键使命令结束，放置一组引脚的时候，还可以设置引脚的类型，比如输入、输出、双向、电源等等，这个没有区分电源和地，电源和地都是power型的，现在输入下面的几个数字，线型都是默认的Passive，引脚间距Pin Spacing设为1，点击ok，放置好后成为下面的样子，有些部分不需要显示，双击空白处弹出一个属性对话框，虚框里面的数字是PinName，虚框外面的数字是PinNumber，如果可视属性改成False就不显示了。
如果想改变其中一个引脚的引脚名、引脚编号、引脚类型，选中该引脚，右击选择Edit Properties，或者双击该引脚，如下图：画直线的时候，这里默认是按照栅格点为最小单位的，可以改变这种限制，画出任意长度任意角度的线，在工具栏Options Grid Display中，不要勾选Pointer snap to grid就可以了，记得画完想要的任意直线后，再将这里勾选，这是一个好习惯，可以让画出的线更规则整齐。
Cadence 手册详细图解 英文版
Cadence IC Design ManualFor EE5518ZHENG Huan QunLin Long YangRevised onMay 2017Department of Electrical & Computer EngineeringNational University of SingaporeContents1 INTRODUCTION (4)1.1 Overview of Design Flow (4)1.2 Getting Started with Cadence (6)1.3 Using Online Help (8)1.4 Exit Cadence (8)2 SCHEMATIC ENTRY (9)2.1 Creating a New Design Library (9)2.2 Creating a Schematic Cellview (10)2.3 Adding Components to Schematic (11)2.4 Adding Pins to Schematic (12)2.5 Adding Wires to Schematic (13)2.6 Saving Your Design (14)3 SYMBOL AND TEST CIRCUIT CREATION (15)3.1 Creating Symbol (15)3.2 Editing Symbol (16)3.3 Building Test Bench (18)4 SIMULATING YOUR CIRCUIT (21)4.1 Start the Simulation Environment (21)4.2 Selecting Project Directory (21)4.3 Setup Model Library (22)4.4 Choosing the Desired Analysis (22)4.5 Setup Variables (23)4.6 Saving Simulation Data (24)4.7 Saving Output for Plotting (24)4.8 Viewing the Netlists (25)4.9 Running the Simulation (25)5 PHYSICAL LAYOUT (28)5.1 Layout vs Symbol of CMOS Devices (28)5.2 Starting Layout Editor (29)5.3 Vias (31)5.4 Changing the Grid (33)5.5 Inserting and Editing Instances (34)5.6 Drawing Shapes / Paths (35)5.7 Creating Pins (36)6 DESIGN VERIFICATION: DRC AND LVS (38)6.1 Performing DRC (38)6.2 Performing LVS (40)6.3 Performing PEX (41)7 POST‐LAYOUT SIMULATION (45)7.1 Simulation the Extracted Cell View (45)8 CONCLUSION (46)1INTRODUCTIONThis manual describes how to use Cadence IC design tools. It covers the whole design cycle, from the front-end to the back-end, i.e., from the pre-layout design to the post-layout design.The manual aims to provide a guide for fresh users. Following the manual, users can start doing analog IC design even though the users don’t have any knowledge of the tools.An inverter is used to illustrate the whole cycle of analog IC design, and Cadence Generic 45nm (cg45nm) kit is the technology library used for implementing the inverter. The method stated in the manual can be applied to other type of analog circuit design.1.1Overview of Design FlowFigure 1 shows a typical analog IC design flow.The design flow starts from schematic entry with the Cadence schematic capture tool –Schematic Editor. Devices or cells from the cg45nm or other libraries are used to build your circuit. Your design is hierarchical; therefore higher level schematics also incorporate cells which you have already developed. The schematics which you enter at this stage therefore typically consist of a number of base library cells and also lower level cells designed yourself.These are described in Sections 2 and 3 of the manual.When you have finished designing a particular circuit, you need to simulate it to ensure that it works as expected. It would be unlikely that your circuit works as expected at the first time so you have to repeat the cycle to improve the circuit, as shown in Figure 1, until the circuit works satisfactorily. This must be done for each sub-circuit of your design and then for the top level design. How to simulate and view the performance of simulation results are presented in Sections 4 of the manual.When the performance of the circuit is satisfactory, it is ready to start the physical design or layout of the circuit. The layout starts with the cell or device placement. Once the cells have been placed, routing can be carried out. Routing connects the cells/device of the design.After finishing placement and routing, the layout has to go through the Design Rule Check (DRC) with rule decks provided by PDK provider, to ensure that there is no design rule violation in the layout. The layout has to be rectified accordingly to the rules’ requirement till it passes DRC.Upon a successful DRC, it is Layout-versus-Schematic (LVS) check, to assure that all connections in the layout are correct. The layout has to be amended accordingly to the schematic If LVS doesn’t pass. DRC has to be done whenever layout is changed. The process is repeated until the LVS passes.Figure 1. Analog IC Design FlowThe next step is parasitic extraction (PEX) to get the extracted view of the circuit, which is used for post–layout simulation. The extracted view includes the parasitic effects in both the instances/devices and the required wiring interconnects of the circuit.Following DRC, LVS and PEX, it is post-layout simulation. The post-layout simulation is essential to make sure that the circuit with the extra parasitic parameters functions well and still meet the design specifications. If the performance of the post-layout simulation is not acceptable, back to the stage of schematic entry to check the circuit. Basically, re-design the circuit is necessary. Repeat the whole flow until the results of the post-layout simulation meet the design specifications.If everything is satisfactory, the next stage is GDSII Generation. It generates a file which depicts the low level geometry of layout. GDSII format is industry standard format suitable fora semiconductor company to fabricate and manufacture the chip of layout. This is briefed inthe last section of the manual.1.2Getting Started with CadenceUpon logging into your account, you will be brought to the Linux Desktop Environment.Right click on the desktop and click Open Terminal to open a “window” on the desktop. This window is the Linux command line prompt at which you can run Linux commands. After running a Linux command, this window also shows the output of the command.The following steps show how to start Cadence with cg45nm kit.A.Create a working directory - project (it can be any name as you like) with thecommand:mkdir projectwhere mkdir is Linux command and the project is the directory name;B.Enter the working directory with the command:cd projectwhere the cd is the Linux command;C.Type the followings commands to do the environment setup for using Cadence Generic45nm PDK.cp /app11/cg45nm/USERS/cds.lib .cp /app11/cg45nm/USERS/assura_tech.lib .cp /app11/cg45nm/USERS/pvtech.lib .D.Start cadence in the working directory – project with the following command:virtuoso &where virtuoso is the command to start Cadence IC design tool.Now, Cadence tools are successfully started. Keeps only the Command Input Window (CIW) which is shown in Figure 2.Figure 2. CIW WindowDo not close this CIW and try to keep it in view whenever you are using Cadence. Error messages and output from some of the tools are always sent to the CIW. If something doesn't appear to be working, always check the CIW for error messages. In addition, the CIW allows the user great control over Cadence by interpreting skill commands which are typed into it.E.In the CIW, select Tools Library Manager. The Library Manager pop up as inFigure 3. The Library Manager is where you create, add, copy, delete and organizeyour libraries and cell views.Figure 3. Library Manager WindowYou can see that the library gpdk045 appears in the Library column of the librarymanager.Now, you have started Cadence tool and loaded the cg45nm kit successfully. There are some documents in /app11/cg45nm/ gpdk045_v4_0/docs, and you can always refer to these documents for the information such as devices, device models, DRC rules and others related to cg45nm kit.Next time, you need only to repeat the steps B and D, for launching Cadence virtuoso and doing your project.1.3Using Online HelpCadence provides a comprehensive online manuals for all Cadence tools. You can launch the online help by typing the following command at the Linux prompt.cdnshelpThis invokes the online software manuals. Alternately, there is a help menu on each Cadence window. Manual which is related to that window related will pop-up once clicking on the help button.1.4Exit CadenceTo exit Cadence, just click on the cross sign X or File Exit in CIW. It is necessary to exit Cadence when it is not in use. Your library file would be locked or cannot edited next time if Cadence was not exited properly.2SCHEMATIC ENTRYNow that Cadence is running, you are almost ready to start entering schematics. However, you must first create a library which will be used to store all the parts of your design. Then, schematic can be created in the library.2.1Creating a New Design LibraryA.In the Library Manager window, select File→New→Library. New Library formpops up as shown in Figure 4.B.In the New Library form referring to Figure 4, key in your design library name(example: test) in the field of Name, and then click Ok.C.Click Ok in the pop-up window - the Technology File for New Library, referring toFigure 5.D.Choose gpdk045 in the Attach Library to Technology Library form, referring toFigure 6, and then click Ok.Figure 4. New Library FormFigure 5. Technology File for New Library FormFigure 6. Attach Library to Technology File FormA new library, named test, should appear in your Library Manager window.2.2 Creating a Schematic CellviewA.In Library Manager, select the Library where you would like to create a schematic. Then,select File→New→Cell View.B.Set up the New File form as Figure 7Figure 7. Create CellViewC.Click OK when done. A blank schematic window for the "inv" (your cell name)schematic appears.Explore the functions available by putting your mouse over the toolbar and fixed menu icons.In addition, note that some of the menu selections have alphabets listed to the right of them. These are bind-key or shortcut-key definitions which are very useful in the long run.Test them out during the schematic drawing in subsequent steps.2.3Adding Components to SchematicFigure 8 shows the schematic which you are going to patch, and the property of each component is listed in Table 1.Figure 8. Inverter CircuitTabel 1. Component Properties of Figure 8: Inverter CircuitComponents Library Name Cell Name PropertiesPMOS gpdk045 pmos1v l:45nm w:120nm (default size)NMOS gpdk045 nmos1v l:45nm w:120nm (default size)Here is the example on how to add component instances by placing cell views from libraries. Type “i” bind-key or select Create Instance in the schematic window or click on the menu bar to display Add Instance form. Then in the Add Instance window, select gpdk045as Library, choose the NMOS transistor by selecting nmos1v in Cell and also choose symbol as View, as shown in Figure 9.Figure 9. Add Instance FormSimilarly, add the pmos1v into the schematic. As an example, here we just keep all theparameters as default.If you place a component with the wrong parameter values, select the component and type “q” bindkey or use the Edit→Properties→Objects command to change the parameters. Use the Edit→Move command or type “m” if you place components in the wrong location.2.4Adding Pins to SchematicYou must place I/O pins in your schematic to identify the inputs and the outputs. A pin can be an input, output or an input-output (bi-directional) pin.Type “p” or select Add →Pin from inv Schematic Window or click the Pin fixed menuicon in the schematic window. The Add Pin form appears as Figure 10.Figure 10. Add Pin FormClick Hide and move you cursor to the Schematic Window. Place pins at the correct places and click right mouse key to rotate the pin if necessary.Add pins according to Table 2, paying attention to the direction.Table 2. Pin Names and Direction of invPin Names DirectionVin InputVout OutputVDD, GND Input-OutputCaution: Do not use the add component form to place schematic pins.2.5 Adding Wires to SchematicAdd wires to connect the components and pins in the design.A.Type “w” or select Add →Wire (narrow) in Schematic Window or click (narrow)fixed menu icon.B.In the schematic window, click on a pin of one of your components as the first pointfor your wiring. A diamond shape appears over the starting point of this wire.C.Follow the prompts at the bottom of the design window and click left mouse key onthe destination point for your wire.D.Continue wiring the schematic. When done wiring, press Esc with your cursor in theschematic window to cancel wiring.2.6Saving Your DesignCheck the design to ensure that it is correct and save the design.A.Click the Check and Save icon in the schematic window.B.Observe the CIW output area, for the information of the check and save action.3SYMBOL AND TEST CIRCUIT CREATIONSymbols are useful when creating designs as it is impractical to show every transistor on the top level schematic. Instead, the symbols of cells are created in order to instantiate them in the higher level schematics and make them more readable (i.e. hierarchical designs). Create a symbol for your design so you can place it in a test circuit for simulation.3.1Creating SymbolA.In the inv schematic window, select Create → Cellview → From Cellview. CellviewFrom Cellview pops up as shown in Figure 11.Figure 11. Cellview From Cellview FormB.Click OK in the Cellview From Cellview form. The Symbol Generation Options formappears as Figure 12. Enter the information listed in Table 3 for the symbol.Table 3: Pin SpectificationsLeft Pins : VinRight Pins : VoutTop Pins: VDDBottom Pins: GNDFigure 12. Symbol Generation Options FormC.Click OK in the Symbol Generation Options form. A window with a symbol createdautomatically by the tools pops up, referring to Figure 13.Figure 13. Symbol Generated AutomaticallyD.Observe the CIW output pane and note the messages stating Adding ‘CDFinformation ...’.3.2Editing SymbolYou can modify the symbol to have a more meaningful shape for easy recognition.A.Move your cursor over the symbol, until the entire green rectangle is highlighted. Clickleft to select it.B.Click Delete icon in the symbol window to delete the green rectangle.C.Select Create→Shape→Polygon. Follow the prompts at the bottom of the symbol, anddraw the triangle shown in Figure 14.D.Type “m” or click Move icon in the symbol window, move the pins to the finaldestination.E.Select [@partName], and use Edit→Properties→Object to change it to inverter asshown in Figure 14.Figure 14. Edit Object Properties FormF.Save your edited symbol view. The final symbol is shown in Figure 15.Figure 15. Symbol of inv3.3Building Test BenchTo test the inverter that you have just built, you need to create a test bench. This test bench will also be used during the post-layout simulation.Creating an inv_test schematic cellview with the below information, following the steps listed in Section 2 – SCHEMATIC ENTRY. The test bench is as shown in Figure 17.Library Name : testCell Name : inv_testView Name : schematicLibrary Name Cell Name Propertiestest inv_testanalogLib Vdc VDDanalogLib vpulse Referring to Figure 16analogLib gnd GNDanalogLib cap 1f FFigure 16. Vpulse FormFigure 17. Test Bench – inv_test for inv CircuitNote:There are wire names Vin and Vout in Figure 17. These can be created by clicking on Create Wire Name on the inv_test schematic window. Key in Vin Vout in the Names field of the Add Wire Name form, and then click Hide. Moving your mouse to the schematic window, click the wire where you want it to be named in the same sequence as typing the names in the Names field.4SIMULATING YOUR CIRCUITBefore starting the simulation, make sure that the schematic (inv_test) is open, then perform the following steps.4.1Start the Simulation EnvironmentIn your schematic window, select Launch →ADE L. The Analog Design Environment (ADE) window appears as shown in Figure 18.Figure 18. ADE Window4.2Selecting Project DirectoryIn the ADE window, select Setup→Simulator/ Directory/ Host. A Choosing Simulator form appears as Figure 19. In the Project Directory blank, type in /var/tmp/(desired folder name) to save your simulation files in the /var/tmp directory on the local server. Click OK to confirm.Figure 19. Choosing Simulator/Directory/Host FormAs each user account has a limited quota, this helps to conserve memory space in your account and prevents you from exceeding your account quota. However, note that contents in this folder is deleted periodically every 30 days automatically.4.3Setup Model LibraryIn the ADE window, select Setup Model Libraries. The Model Library setup form appears. Double click the column of section, and then click the down arrow to choose tt which is typical N and P model parameters. The model library setup for the inv_test circuit is shown in Figure 20. Click ok on the setup form to finish the settings.The information of models can be found in/app11/cg45nm/gpdk045_v4_0/docs/gpdk045_pdk_referenceManual.pdf.Figure 20. Model Library Setup for inv_test4.4Choosing the Desired AnalysisIn the ADE window, click the Choose Analyses icon . The Choosing Analyses form appears. Cadence ADE is able to run several types of simulations consecutively. You are then able to view the signals from different simulations at the same time. In this example, we will do transient analysis, so we shall setup transient analyses through the ADE as Figure 21.Figure 21. Setup for Transient Analyses4.5Setup VariablesThere is a variable, VDD, in the inv_test circuit. We need to set a value to it before starting simulation.In the ADE window, click Variables. Enter the name as the variable name VDD, then set the valueas 1.1, and finally click Ok. Please take note that 1.1v is the nominal voltage for this technology.Figure 22. Editing Design Variables4.6Saving Simulation DataThe simulation environment is configured to save all node voltages in the design by default. In larger designs, where saving all of the data requires too much disk space, you can select a specific set of node to save. Following steps show you how to select terminals to save.A.In the ADE window, select Outputs→Save All.B.The Keep Options form appears. Do not modify the form at this time. However, if youneed to save less data, under the first option “Select signals to output”, Click “selected”.4.7Saving Output for PlottingSelect the signals that you would like to observe.A.Select Outputs→To Be Plotted→Select On Design.B.Note that if you click on wires / nets, voltage signals are selected. If you click onconnection nodes, currents flowing through that note and into the component are saved.C.Follow the prompts at the bottom of the schematic window. Click on the output wireslabeled with Vout and Vin (select the wire that you want to monitor).D.Press Esc with your cursor in the schematic window when finished.Now you have set up the simulation environment which as shown in Figure 23. You can save the simulation state. This saves all the information such as the Model Path, outputs, analyses, environment options, and variables so that you do not need to set these parameters the next time again.Figure 23. ADE window with completed settingsIn the ADE window, select Session→Save State. Tick Cellview and then click OK. You can recall your settings by selecting Session→Load State.4.8Viewing the NetlistsSometimes, you need to view the netlist of your circuit or design. You can do so through the ADE, select Simulation→Netlist→Create / Display / Recreate.If there are any errors encountered during this step, check the messages in the CIW and retrace your steps to see that all data was entered properly.4.9Running the SimulationSelect Simulation→Netlist and Run to start the simulation or click on the Run Simulation icon in the Simulation Window. After the simulation is done, a waveform window will pop up showing the simulation results as Figure 24.Click on the waveform window to separate Vin and Vout.You can create a horizontal or vertical marker by clicking Marker on the waveform window. For example, creating a horizontal marker on Figure 24 with put Y Postion at 0.5*VDD=550mV, and then zoom in. The waveform window will look like Figure 25. Delays of the inverter could be found from the reading on the marker.Figure 24. Output of SimulationFigure 25. Waveform with Marker.Explore the icons on the toolbar as well as the various items on the menu. Try to add markers as that is something that will be used often during your simulations. You can also update the titles and labels on your plot to make them easy to read or more meaningful, if necessary.*Quick Tip : Shortcuts “a” and “b” to place a delta marker where you observe the difference between two points. What does shortcuts “v” and “h” do?There are many other functions available in the calculator tool, explore and play around with them.By now, you have finished pre-layout simulation (schematic level simulation). Next, you need to draw the layout of the inverter circuit and then do post-layout simulation to check your circuitperformance.5 PHYSICAL LAYOUTBy now, you should know how to create and simulate your circuit. Once the performance of your design is satisfactory, the next step in the process of making an integrated circuit chip is to create a layout. What is a layout? A layout is basically a drawing of the masks from which your design will be fabricated. Therefore, layout is just as critical as specifying the parameters of your devices.Before we get into the layout, first you need to understand the design rules for layout. Design rules give guidelines for generating layouts. They dictate spaces between wells, sizes of contacts, minimum spacing between a poly and a metal, and many other similar rules.Design rules are essential to any successful layout design, since they account for the various allowances that need to be given during actual fabrication and to account for the sizes and the steps involved in generating masks for the final layout. Note that the layout is very much process dependent, since every process has a certain fixed number of available masks for layout and fabrication.You may find more details on the Design Rules Manual (DRM):/app11/cg45nm/gpdk045_v_4_0/docs/gpdk045_drc.pdf5.1 Layout vs Symbol of CMOS DevicesIn this section, we look at only three devices: nmos1v and pmos1v. Check the process document, you can find the information for other devices.Figure 26 shows the nmos1v device. From layout view, you can see that the terminal B is the black background of the layout window.Figure 26. Layout vs Symbol of NMOSFigure 27 shows the pmos1v device, which looks similar to NMOS device but with P type implant (orange-stripe layer) and N-well (purple surrounding layer). G D SBFigure 27. Layout vs Symbol of PMOS5.2Starting Layout EditorNow we are going to create a new layout in the cell “inv” in “test” library.A.In Library Manager, select File→New→Cellview ... A Create New File form pops up.B.Select "test" as Library Name; enter "inv" as Cell Name, "layout" as View Name.C.Choose Open with Layout XL, and then click OK.Figure 28. Create Cellview – LayoutUseful layerselectionfeatureFigure 29. Layout WindowCell "inv" with "layout" view in library "test" will be created. It is opened up automatically, followed by inv schematic window, as shown in Figure 29. The layout editor contains two main sub-windows, namely the Layers sub-window on the left and Layout Editing window on the right. Notice the Layers sub-window on the left side of the layout view. This sub-window displays the fabrication layers defined in the technology. You can find the cross sectional profile in the process documents.Each layer is represented by a different color and pattern for easier differentiation. The black background on the right can be interpreted as the p-substrate of the wafer.To hide a layer, use the middle scroll button to click on a layer. To disable a layer from use, use the right mouse button.You might notice that some layer names appear more than once in the Layers sub-window. For example, Metal1 appears two times: one as Metal1 drawing, the other as Metal1 pin. Metal1 drawing is a layer with drawing purpose, and such layers with drawing purposes will be fabricated in the mask. The pin layers are symbolic layers and serve to indicate position of I/O pins and define net names. Such layers are not part of the mask layout and will not be fabricated.5.3ViasVias are used to connect between layers, much like those used in PCB design.There are different types of vias for different layer pairs. Normally a via is only for connecting two successive layers, e.g., Metal 1 and Metal 2. In case there is a metal jump between more than two layers, via stacking is required.In the layout window, click Create→Via or type “o” to bring up the via menu. Place the vias on the layout editing window, you can observe the layers that are involved in each type of via. Experiment with the different modes and configurations in the via menu to create arrays and stacks of vias as well. For example,A.Click on Create→Via, the Create Via window pops up as figure 30 shows.B.Choose M1_PO under Via Definition, and click on the layout window to place it andthen press Esc button to stop the placing. You can change the number of Rows and Columns on the Create Via form.C.To view the layers of M1_PO, click to select it first and then press Shift + f key. Observethe via appears different.D.To check the layers used in via M1_PO, select it and then click Edit→Hierarchy→Flatten as shown in figure 31. Click OK on the pop-up form shown in Figure 32.E.Now, you can separate the layers and check layers’ property to find out the layers’ name.Via M1_PO connects layers Metal 1 and Poly as shown in Figure 33.Try to explore different options (Rows, Columns, Stack, etc.) under via menu by yourself, this will be very helpful for layout drawing.Figure 30. Create Via windowsFigure 31. Edit ViaFigure 32. Flatten FormFigure 33. Via M1_POThe M1_PSUB and M1_NWELL contacts are substrate and n-well contacts that are used to connect the bulks of the NMOS and PMOS respectively. For the inverter circuit used in this manual, the bulks of the NMOS and PMOS need to be connected to ground (GND) and VDD respectively.5.4Changing the GridIn Figure 29, the black window on the right is the layout editing window. The position of the cursor in layout editing window is indicated by the coordinate showed on the top right corner of the window after X: and Y:. The unit here is "µm". Move your cursor around the editing window and see the X: Y: values change with step size 0.1. Change the step size to 0.005 as that is the minimum step size for this technology.From Layout Editing window pull down menu, select Options →Display... change "X Snap Spacing" and "Y Snap Spacing" to 0.005 then click on "OK". Now move the cursor around the editing window again, you will see the X: Y: values change with step size 0.005.There are raw grid and fine grid (as small dots) on the window background. If you cannot clearly see the raw grids, from pull down menu select Window →Zoom out by 2In addition to pull down menu and bind key "z", "Zoom Out" is also listed in the picture tool bar to the left of the window. Find it and try it out.Also you may use up, down, left, and right arrows to move around the design window. You will need to use "Zoom in" and "Zoom out" and those arrows many times throughout your design process. So it's not a bad idea to practice them a little bit now.To save and close the cell view, from Virtuoso Editing window, Select Design →Save.。
cadence版图使用说明
目录目录 (1)设计环境介绍 (2)工作站常用命令 (2)运行Cadence (6)运行Layout (10)运行schematic的编辑 (15)生成schematic symbol (18)运行Artist的仿真环境 (20)设计示例的简单介绍 (21)设计环境介绍典型的全定制Full-Custom模拟集成电路设计环境1. 集成的设计环境－Cadence Design Framework II是众多Cadence 工具集成在一起的统一的界面，通过这个架构,不用繁琐的数据格式转换，就可以方便的从一个工具转到另一个工具。
其中包括很多软件，如：原理图编辑工具-Composer布局编辑工具-Candence virtuoso布局验证编辑工具-Diva, Dracula2. 电路网表或原理图编辑环境－Text editor / schematic editor3. 电路模拟软件－spice操作系统环境和硬件平台1.SUN工作站；UNIX系统2.运行Linux的PC3.作为终端的PC工作站常用命令一、在terminal窗口键入的基本命令：1. ls：列出目录下所有文件。
2. clear：清除terminal窗口里的内容。
3. pwd：显示目前工作的目录。
4. cd：改变当前目录。
5. rm：刪除文件。
6. cp：复制文件。
7. mv：移动文件。
8. mkdir：建立目录。
9. rmdir：刪除目录。
10. find：寻找文件。
11. passwd：改变当前用户密码。
12. finger：显示当前用户信息。
二、基本操作和命令的使用介绍：1.从PC登录工作站，一般使用exeed或Xmanager。
login ：___________(输入username)password：___________(输入密码)2.登出步骤：点击exit3.在线命令说明（以下的example% 表示系统的提示符）example% man [command-name]4. 改变当前目录example% cd [name]Example：example% cd dir1 改变目录位置，至dir1目录下。
Cadence学习笔记1__原理图
新建元件时选择Heterogeneous，A部分和上面的一样画法，但是按键盘上的ctrl+N切换到B部分时，B部分是空白的，需要再画一次。
不管是Homogeneous还是Heterogeneous，点击工具栏ViewPakage，可以将A和B同时显示出来，如下图：
保存后，一个元件就画好了，画原理图时直接调用即可。
如果是由两部分组成的分裂元件，要在新建元件时在Parts per Pkg写2，这里分为Homogeneous和Heterogeneous两种。Homogeneous是只要画出A部分，B部分会默认的和A部分完全一样，Heterogeneous是画好A部分后，B部分仍然是空白的，需要再画。如果一个芯片包含了2个功能完全相同的部分，像下图中NE5532中的两个运放，就需要用到Homogeneous了，这里先选Homogeneous，点击ok。
元器件
FileNewLibrary新建一个库，如下图，显示了路径和默认库名library1.olb，右击选择Save As可以改变路径和库名，右击新建一个元件，可以选择New Part或者是NewPart From Speadsheet，是两种不同的方式，先介绍New Part的操作。
右击选择New Part后，弹出下面的对话框，在Name中填入元件名，还可以指定PCBFootprint，下面Parts per Pkg表示这个元件有几部分，1表示普通的元件，如果元件是两部分组成的分裂元件就写2，这里先操作1，点击ok。
点击左侧工具栏make图标 ，所有的横线和竖线都变成粉红色的，这就生成了一个表格，鼠标右击选择Tag Pin Name，在引脚名这一列点一下，会在这一列最上面出现“Name”，同样的，右击选择TagPin Number，在引脚编号这一列点一下，会在这一列最上面出现“Num”，如果放错了，比如说该放Name的地方放成了Num，可以在放Num之后再点一次，Num就消失了，产生的结果如上图右。
cadence原理图设计实例教程
器件放置
• 也可以按下步骤放置uA741：
➢ 执行P1ace/Part命令 ➢ 在 Part中输“ *741* ” ， ➢ 点击Part Search, ➢ 点击Begin Search, ➢ 在Library 库中寻找到
uA741/opamp.olb ➢ 单击“OK” ➢ 执行前面的步骤，单击
“OK”，放置器件，断开放 置
放置电容符号
➢ 执行P1ace/Part命令 ➢ 在 “Libraries”列表框中选
择“ANALOG” ➢ 在 “Part”列表框中选择
“ C” ➢ 单击“OK” ➢ 将电阻C移至合适位置，
（按键盘中的R键，器件旋 转）按鼠标左键放置 ➢ 按ESC键（或鼠标右键点 end mode）结束绘制元器
器件封装调用
在Link Footprint to Component 栏内点OK,对于没有 定义的管脚封装图,出现MAXECO提示说明,确定
器件封装调用
在Link Footprint to Component 栏内点OK,对于没有定义的管脚封 装图, 点Link existing footprint to component来查找连接封装。
Place net name
放置分页图纸间的接口
原理图绘制
(二) 原理图绘制
以声控开关为例（电源是直流12V，负载为发光二极管）见下 图:
放置集成块运放uA741
• 执行P1ace/Part命令 • 在 “Libraries”列表
框中选择“OPAMP” 库 • 在 “Part”列表框中 选择“uA741” • 单击“OK” • 将集成块移至合适位 置，按鼠标左键 • 按ESC键或鼠标右键点 end mode以结束绘 制元器件状态
Cadence原理图绘制流程
第一章设计流程传统的硬件系统设计流程如图1－1所示，由于系统速率较低，整个系统基本工作在集中参数模型下，因此各个设计阶段之间的影响很小。
设计人员只需要了解本阶段的基本知识及设计方法即可。
但是随着工艺水平的不断提高，系统速率快速的提升，系统的实际行为和理想模型之间的差距越来越大，各设计阶段之间的影响也越来越显著。
为了保证设计的正确性，设计流程也因此有所变动，如图1－2所示，主要体现在增加了系统的前仿真和后仿真。
通过两次仿真的结果来预测系统在分布参数的情况下是否能够工作正常，减少失败的可能性。
细化并调整以上原理图设计阶段的流程，并结合我们的实际情况，原理图设计阶段应该包括如下几个过程：1、 阅读相关资料和器件手册在这个阶段应该阅读的资料包括，系统的详细设计、数据流分析、各器件手册、器件成本等。
2、 选择器件并开始建库在这个阶段应该基本完成从主器件到各种辅助器件的选择工作，并根据选择结果申请建库。
3、 确认器件资料并完成详细设计框图为保证器件的选择符合系统的要求，在这一阶段需要完成各部分电路具体连接方式的设计框图，同时再次确认器件的相关参数符合系统的要求，并能够和其他器件正确配合。
4、 编写相关文档这些文档可以包括：器件选择原因、可替换器件列表、器件间的连接框图、相关设计的来源（参考设计、曾验证过的设计等），参数选择说明，高速连接线及其它信息说明。
5、 完成EPLD 内部逻辑设计，并充分考虑可扩展性。
在编写相关文档的的同时需要完成EPLD内部逻辑的设计，确定器件容量及连接方式可行。
6、使用Concept-HDL绘制原理图7、检查原理图及相关文档确保其一致性。
以上流程中并未包括前仿真的相关内容，在设计中可以根据实际情况，有选择的对部分重要连线作相关仿真，也可以根据I/O的阻抗，上升下降沿变化规律等信息简单分析判断。
此流程中的各部分具体要求、注意事项、相关经验和技巧有待进一步完善。
第二章Concept-HDL的使用运行Concept-HDL后将会出现类似如下界面。
Cadence软件使用教程 ppt课件
Allegro PCB Router 自动布线工具，对于有复杂设计规则的高密度电路板处理能力很强， 可以在Allegro PCB Editor中用自动布线命令调出来。这个布线工 具名气很大，对于简单的电路板，布线很美观，布通率很高。
Cadence软件使用教程
Cadence软件使用教程
1、利用OrCAD Capture CIS进行原理图设计 2、利用Cadence PCB Editor进行PCB布局布线 3、光绘文件(Artwork)制作，如何生成Gerber文件
Cadence软件使用教程
Cadence软件使用教程
1、系统的原理图工程文件 2、系统的PCB图工程文件 3、原件库、封装库文件 4、板上芯片的datasheet 5、给PCB厂商的Gerber文件（Artwork） 6、DSP6713程序的C语言源代码
Padstack Designer 创建及修改焊盘padstacks Allegro在创建零件封装时，焊盘需要单独设计，必须使用这个工具先创建焊盘。 DB Doctor 用于检查设计数据中的错误，在设计的每一个阶段执行，可以部分修复数据错误。 在生成光绘文件前必须进行DBDoctor检查。
Cadence软件使用教程
Cadence软件使用教程
Cadence软件使用教程
Cadence软件使用教程
Cadence软件使用教程
Cadence软件使用教程
Cadence软件使用教程
如何使用Cadence进行原理图设计20150418
目录第I篇 (4)第一章设计流程 (4)1.1Capture 设计流程 (4)1.2 Capture 工作界面 (6)1.3 Capture 常用文档类型 (7)第二章设置原理图设计环境 (8)2.1 新项目建立 (8)2.2 系统属性设置 (10)2.3 页面参数设置 (17)2.4 建立标题栏 (20)第三章元件的建立 (24)3.1绘制元件 (24)第四章原理图的绘制 (34)4.1.新建project (34)4.2 拼接式电路图的绘制 (36)4.3 全局封装和值的指定 (38)第五章设计后续处理 (44)5.1 电气规则设置与检查 (44)5.2 自动零件编序 (56)5.3 网络表的产生 (59)5.4 元件清单输出 (64)第II篇 (68)第六章焊盘制作 (68)做热风焊盘时老是提示错误：ERROR - Could Not Generate Shape (68)Allegro从.brd文件中导出器件封装 (70)第七章元器件封装制作 (74)Allegro 16.3 怎样使用自己制作的封装库呢？ (74)第八章建立PCB板 (75)allegro导出DXF 文件 (75)Allegro中如何导入DXF文件 (78)画板框 (81)设板层 (86)设置PCB footprint的路径 (89)导入网表 (89)第九章设置设计规则 (93)PCB常用显示说明 (93)将某对象添加到某subclass中 (93)Allegro如何设置原点 (93)示例1：将outline的左下角的坐标设为原点 (93)光模块走线基本规则 (95)如何设置布线默认过孔Via（Cadence16.0及以上版本） (95)allegro16.2建立差分对，设置差分规则，差分走线 (98)添加subclass (104)allegro 如何隐藏飞线 (105)第十章布局（基础篇） (106)按原理图方式进行摆放元件 (106)第十一章 (106)布线 (106)布线基础 (106)布线基础（1）：布线的基本原则 (106)布线基础（2）: 布线的基本顺序 (107)布线基础（3）: 布线层 (108)布线基础（4）：重要信号的布线 (110)布线基础（5）：拓扑结构 (114)allegro中泪滴(teardrop）的添加与删除（一） (114)allegro中泪滴(teardrop）的添加与删除（二） (114)allegro中泪滴(teardrop）的添加与删除（三） (115)第十二章后处理——发PCB制板长前的准备工作 (116)Database Check (116)Tools\Updata DRC (117)设置NC Parameters (117)放置DRILL CHART表格 (119)出Artwork (121)出Artwork前的准备工作 (125)文件分类打包 (127)1.PCB_Process_Instruction (127)2.PCB PANEL DRAWING (129)3.GERBER FOR PCB (129)4.SURFACE_MOUNT_DIAGRAM (129)5.GERBER FOR SMT (131)6. Drawing (131)7.SCH (131)附件1：《CADENCE or CAD CAPTURE快捷键》 (131)附件2：《基础知识问答》 (133)1、什么是FANOUT布线 (133)2、如何在Allegro中测量距离 (133)附件3 (135)第I篇第一章设计流程1.1Capture 设计流程Capture设计流程从新建设计项目开始，设置原理图设计环境，新建元器件、绘制原理图和设计后续处理。
cadence的原理图库设计PPT学习教案
为了仿真
第9页/共41页
在Logical Pin”对话框弹出同时也会出现一个表 单。设 计者在 输入“p in” 之前，要根据供应商提供元件的“da tashee t”中“ pin name”的形式进行“Edit”选项的设置
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那么在这里： Bit:是基于位的形式 Slot:是基于槽的形式 Group:是基于组的形式。基于哪种形 式要根 据“Dat asheet ”的形 式来决 定。如 要输入 矢量， 请选择 ：BN-B; BN;BN- B。如 要输入 标量， 请选择 ：BN-S; BN;BN- S
下面以一个简单器件的创建过程来演示一下一个元件库的创建流程。同 时，介绍一下“Part Developer”的基本使用。
启 动PROJECT MANAGER， 建 立 一 个 新 工 程（PROJECT）（或者直接 从开始选择library explorer启动。）
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在工程（project）的主界面选择 Tools/Library Tools/Part Developer
GO ON
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封装定义结束后，要给元件在原理图中一个表示符号（Symbol） ：选择“Part Developer”中的“Symbols”，右键选择“NEW”。
第21页/共41页
在对话框中高亮的三个选项中，经常使用的为前两项。选择您所 需要的形式进行下一步，这里选择“Number 2”：
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在Logical Pin对话框中输入pin name之前。一定要在 “pin”选项种选择正确的类型。（ 按所选 用元件 的说明 ）
GO ON
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cadence软件基本原理图设计指导培训
9、INDUCTOR（电感） 10、MEMORY（存储器） 11、MICROPROCESSOR（微处理器） 12、OPTICAL_TRANSMITTER_MODULE（光传
输模块） 13、OPTOISOLATOR（光电耦合器） 14、POWER（电源模块） 15、RELAY（继电器） 16、RESISTOR（电阻）
二、原理图设计的基本流程
方案设计
器件选型
申请原理图库
初始化设置
创建proБайду номын сангаасect
库映射及调用
原理图设计
原理图check
原理图评审
pcb设计
pcb设计申请 毛坯图确认
申请毛坯
一、Cadence软件介绍 二、原理图设计基本流程 三、典型project的目录结构 四、原理图库相关 五、原理图设计相关（before/after） 六、原理图设计技巧及常见问题解决
17、SPECIAL_IC（专用器件） 18、SWITCH（开关） 19、TP_JP（测试点和跳针） 20、TRANSFORMER（变压器） 21、TRANSISTOR（晶体管） 22、OTHERS（其它）
原理图库所包含的信息
1、PARTCODE－－物料号 2、PARTVALUE－－器件型号 3、 JEDEC_TYPE－－器件封装 4、 $LOCATION－－器件位号 5、 GROUP －－器件分组属性 6、 DESCRIPTION－－器件描述（封装类型/器件
联系我们：
技术支持： 李军华 87691070 贾建收 87693634 廖 骞 87693634
器件库相关： 潘红英 87691070
原理图设计
原理图设计的初始设置 原理图设计的基本命令及操作 设计层次化原理图 原理图设计注意事项 原理图打印
cadence教程 ppt课件
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cadence教程
CADENCE
➢ 市场需求以及工艺技术的发展使得设计 复杂度提高，为满足这样的需求，我们 必须掌握最强大的 EDA 工具
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cadence教程
CADENCE
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1.5~1.8 1.2~1.5 1.2~1.5 0.9~1.2 0.6~0.9 0.5-0.6
1200 1400 1600 2000 2500 3000
500 600 700 900 1200 1500
400 450 560 790 1120 1580
340 385 430 520 620 750
800 850 900 1000 1100 1300
6.2M 10M 18M 39M 84M 180M
6 显示文件（display.drf）
18
cadence教程
CADENCE
❖ 系统启动 1 前端启动命令
命令
规模
功能
icde
s
icds
s
icms
m
icca
xl
基本数字模拟设 计输入
icde 加数字设计 环境
前端模拟、混合、 微波设计
第二章Cadence的原理图设计
第二章 Cadence的原理图设计2.1Design Entry CIS软件概述Cadence软件系统有两套电路原理图的设计工具，一套是Design Entry HDL，另一套就是我们马上要开始学习的Design Entry CIS。
其中Design Entry HDL 是Cadence公司原本的原理图设计软件，可以用于芯片电路和板级电路的设计，其长处在于可以把芯片的电路原理图和板级电路原理图结合在一起，进行综合设计；而Design Entry CIS主要用于常规的板级电路设计，Design Entry CIS原本是OrCAD公司的产品，OrCAD公司后来被Cadence公司收购，于是Design Entry CIS也就成了Cadence公司的另一套电路原理图设计软件。
Design Entry CIS原理图设计软件的特点是直观、易学、易用，在业界有很高的知名度，利用Design Entry CIS原理图设计软件可以进行简单的（只有单张图纸构成的）电路原理图设计，也可以进行（由多张图纸拼接而成的）平坦式电路原理图设计，还可以进行（多张图纸按一定层次关系构成的）层次式电路原理图设计。
在本章中，我们首先学习简单的电路原理图设计，然后再学习较为复杂的平坦式和层次式电路原理图设计。
我们将围绕一块非常简单的STC系列单片机下载电路板，学习简单电路原理图的设计，同时在此过程中，还将学习到USB转UART串行口、STC系列单片机下载电路等方面的知识。
接着，我们将围绕一块ARM-7核心实验板，进行平坦式和层次式电路原理图的设计，而该核心板是配套于ARM-7实验箱。
在此过程中我们还将学习到嵌入式技术等方面的知识。
2.2初识Design Entry CIS一．启动Design Entry CIS我们在电脑上点击“开始→所有程序→Cadence SPB 16.2→Design Entry CIS”，如下图所示：图2-1 启动Design Entry CIS这时将弹出如下对话框：图2-2 选择工作内容在这里我们选择“OrCAD Capture CIS”一项，点击“OK”按钮后，就实际启动了Design Entry CIS，出现如下界面：图2-3 OrCAD Capture CIS软件界面与大多数软件一样，OrCAD Capture CIS软件也是以项目方式管理我们的设计文件的。
cadence原理图设计实例教程
器件封装调用
以这样的方式,直到把所有没有定义的管脚封装图在Link Footprint to Component 栏,点Link existing footprint to component查找出来
印制版设计
二、零件布局
调入网络表后，零件将随着纲路档案的载入而散 布在编辑区里，紧接着，依下列步骤进行自动零 件布置： 1． 定义板框。首先切换到Global Layer层 （按0键），然后按钮，进入放置物件状态，再以 画框的方式，直接在编辑区里画板框。 2、 板框定义完成后，启动 Auto>Place>Board命令，程式即迅速布置零 件。见下图
出现“Display Properties”窗口 • 在“Value”栏填入“10K” • 单击“OK”
其余元件属性参数修改
• 将R2的1k修改为1m • 将R3的1k修改为1m • 将R4的1k修改为82k • 将R5的1k修改为2k • 将C1的1n修改为0.1u • 将C2的1n修改为220u • Vi的VOFF值设定为6v • Vi的VAMPL值设定为30mv • Vi的FREQ值设定为2kHz • V1的0Vdc更改为12Vdc
如果要进行精细的打印或分板层输出的话，则启动Options> Post Process命令，然后在随即出现的表格中，选择所要打印的板层，再点击 鼠标右键，在弹出菜单中选取其中的Plot to Print Manager命令，即可 打印您选中的板层。
电路系统
计算机辅助设计
准确、高效地设计电路
器件放置
• 也可以按下步骤放置uA741：
➢ 执行P1ace/Part命令 ➢ 在 Part中输“ *741* ” ， ➢ 点击Part Search, ➢ 点击Begin Search, ➢ 在Library 库中寻找到
第二章Cadence的原理图设计
第二章 Cadence的原理图设计2.1Design Entry CIS软件概述Cadence软件系统有两套电路原理图的设计工具，一套是Design Entry HDL，另一套就是我们马上要开始学习的Design Entry CIS。
其中Design Entry HDL 是Cadence公司原本的原理图设计软件，可以用于芯片电路和板级电路的设计，其长处在于可以把芯片的电路原理图和板级电路原理图结合在一起，进行综合设计；而Design Entry CIS主要用于常规的板级电路设计，Design Entry CIS原本是OrCAD公司的产品，OrCAD公司后来被Cadence公司收购，于是Design Entry CIS也就成了Cadence公司的另一套电路原理图设计软件。
Design Entry CIS原理图设计软件的特点是直观、易学、易用，在业界有很高的知名度，利用Design Entry CIS原理图设计软件可以进行简单的（只有单张图纸构成的）电路原理图设计，也可以进行（由多张图纸拼接而成的）平坦式电路原理图设计，还可以进行（多张图纸按一定层次关系构成的）层次式电路原理图设计。
在本章中，我们首先学习简单的电路原理图设计，然后再学习较为复杂的平坦式和层次式电路原理图设计。
我们将围绕一块非常简单的STC系列单片机下载电路板，学习简单电路原理图的设计，同时在此过程中，还将学习到USB转UART串行口、STC系列单片机下载电路等方面的知识。
接着，我们将围绕一块ARM-7核心实验板，进行平坦式和层次式电路原理图的设计，而该核心板是配套于ARM-7实验箱。
在此过程中我们还将学习到嵌入式技术等方面的知识。
2.2初识Design Entry CIS一．启动Design Entry CIS我们在电脑上点击“开始→所有程序→Cadence SPB 16.2→Design Entry CIS”，如下图所示：图2-1 启动Design Entry CIS这时将弹出如下对话框：图2-2 选择工作内容在这里我们选择“OrCAD Capture CIS”一项，点击“OK”按钮后，就实际启动了Design Entry CIS，出现如下界面：图2-3 OrCAD Capture CIS软件界面与大多数软件一样，OrCAD Capture CIS软件也是以项目方式管理我们的设计文件的。
学习笔记-candence16.6-原理图部分
学习笔记-candence16.6-原理图部分Candence16.6学习笔记⽬录⼀、原理图设计部分1.针对原理图界⾯的操作2.对原理图进⾏编辑3.对制作原件的编辑4.⽣成⽹表5.⽣成清单和打印设置⼀、针对原理图界⾯的操作1.Design entry CIS:进⾏板级设计时⽤来画原理图的。
2.PCB Editor:cadence进⾏布局布线的软件。
3.Cadence product choices-----OrCAD capture CIS4.进⾏原理图页⾯个性化设置（整体设置）Options-->design template..（即原理图页⾯模板）4.1. 进⾏原理图页⾯个性化设置（单页设置）Options-->schematic page propertise..5. .drn⽂件是建⽴的⼯程的数据库⽂件，包括电路原理图（schematic）、元件库（design cache）、输出⽂件（outputs）。
6.⼯具栏的显⽰、隐藏和⾃定义View-->toolbar7.更改原理图背景颜⾊Option-->Preferences..8.原理图的放⼤、缩⼩①快捷键i、o。
②View-->zoom-->in/out③按住ctrl，滚动⿏标。
⼆、对原理图进⾏编辑1.旋转元器件：快捷键R2.画线：places -->wire快捷键W3.任意⾓度画线：画线时按住shift4.⽹络节点：junction5.删除⽹络节点：按住“s”键，⿏标左键单击节点，此时出现⼀个⽅框，这时按“delete”键，即可删除。
6.浏览命令 browse整体浏览：选中.drn⽂件 Edit-->browse-->parts/nets...... 点击原件标号可以直接定位到该原件。
三、对制作原件的编辑1.批量放置管脚：place--pin array2.批量修改管教：选中需要修改的管脚---右键---editproperties..3.查看元件的属性：options-->part propertise..Options-->edit part propertise..(可以改写footprint)4.查看⼀个package ⾥的⼏个部分：View--packageView--package propertisesCtrl+B:package 的上⼀级Ctrl+N:package 的下⼀级相同的不同的5.画线时任意起点和终点画线：options--->prefences..-->grid display---取消pointer snap to grid6.按组编号：Tool-->annotate..四、⽣成⽹表1.Tools---creat Netlist---PCB Editor⽣成清单和打印设置TOOLS---Bill OF materials1.针对allegro原理图界⾯的操作1）allegro的5种应⽤模式（application mode)1.general edit 普通模式2.Placement edit 排零件模式。