7-TLC0820模数转换器应用实验

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实验7 AD转换0809应用实验

一、实验内容利用实验仪上的0809做A/ D转换实验，〖ZH(〗实验仪上的W1电位器提供模拟量输入。

编制程序，将模拟量转换成数字量，通过发光二极管L1-L8显示。

二、实验说明A/ D转换器大致分有三类：一是双积分A/ D转换器，优点是精度高，抗干扰性好，价格便宜，但速度慢；二是逐次逼近式A/ D转换器，精度、速度、价格适中；三是并行A/ D转换器，速度快，价格也昂贵。

实验用ADC0809属第二类，是8位A/ D转换器。

每采集一次一般需100μs。

由于ADC0809 A/ D转换器转换结束后会自动产生EOC信号(高电平有效)，取反后将其与8031的INT0相连，可以用中断方式读取A/ D转换结果。

三、实验步骤①把A/D区0809的0通道IN0用插针接至W1的中心抽头V01插孔(0-5V)。

②0809的CLK插孔与分频输出端T4相连。

③将W2的输入VIN接+12V插孔，+12V插孔再连到外置电源的+12上(电源内置时，该线已连好)。

调节W2，使V REF 端为+5V。

④将A/D区的VREF 连到W2的输出VREF 端。

⑤EXIC1上插上74LS02芯片，将有关线路按图连好。

⑥将A/D区D0-D7用排线与BUS1区XD0-XD7相连。

⑦将BUS3区P3.0用连到数码管显示区DA TA插孔。

⑧将BUS3区P3.1用连到数码管显示区CLK插孔。

⑨单脉冲发生/SP插孔连到数码管显示区CLR插孔。

⑩仿真实验系统在"P....."状态下。

⑾以连续方式从起始地址06D0运行程序，在数码管上显示当前采集的电压值转换后的数字量，调节W1数码管显示将随着电压变化而相应变化，典型值为0-00H，2.5V-80H，5V-FFH。

#include<reg51.h>#include<absacc.h>#define ad0809 XBYTE[0x9000]//sbit eoc=P3^3;sbit clk=P3^1;sbit sdata=P3^0;void HC164_Send(unsigned char displaysag); void display(unsigned char d);extern void delay(unsigned int n);void delay(unsigned int n);void main(void){unsigned char *add;unsigned char d,adcdata;float adc;add=& ad0809;while(1){*add=0x00;//while(eoc==0);delay(1);d=*add;adc=(float)d*5/255+0.05;adcdata=adc*10;display(adcdata);delay(30000);}}void delay(unsigned int n){while(n--);}。

实验6 数模转换

实验6 数模转换(DAC)实验一、实验目的1.掌握数模转换芯片TLC7528的原理及使用方法；2.掌握ICETEK-DM6437-A板扩展的DAC模块的原理和具体实现方式；3.掌握数模转换的程序设计。

二、实验设备1.PC 兼容机；2.WIN7 操作系统；3.Code Composer Studio v5；4.ICETEK-DM6437-A实验箱(如选择脱离实验箱测试，则配备ICETEK-XDS100v2+仿真器和ICETEK-DM6437-A，+5V电源)；5.标准USB A口转Mini口电缆一条；6.示波器一台(20M或以上)。

三、实验原理1. 数模（D/A）转换数模（D/A）转换：将数字信号转换为相应的模拟信号。

实现数模转换的电子器件称为数模转换器件(DAC)。

数模转换用途：数模转换可以帮助计算机更好地与受控对象进行接口，按照受控对象的特点来控制它们。

可以应用于电脑控制电子乐曲(实现各种音高音色)、照明(均匀缓慢变化)、温度调节(逐渐升温和降温)、电机控制等。

举例来说：通过我们前面实验的学习，我们了解了DM6437控制发光二极管，可以实现其点亮或者熄灭，对于发光二极管这种设备来说，点亮/熄灭正好对应计算机的数字量输出，因此可以不需要DAC器件辅助，也能完成。

当我们需要调节发光二极管的亮度时，就会遇到一些困难，发光二极管无法实现半开半闭的中间状态，于是我们让计算机以很快的频率输出开和关，实现类似于中间状态的半明半暗的效果，由于LED这种器件可以适合于高速的开关操作，所以这种效果还是可以接受的，人眼分辨不了非常高速的闪烁，但仍然会造成一定困扰，比如发光二极管台灯闪烁的速率相对较低时会使眼睛在不知不觉中出现视疲劳，因此市场上还出现了提供更高频率的“护眼”台灯。

如果使用DAC器件，能控制流过发光二极管的电流稳定(而不是时开时断)，这样产生的照明效果将也是稳定的，不会闪烁。

2. AD转换芯片-TLC7528TLC7528可以将收到的8位数字信号转换成相应的模拟输出，每次转换最高速率是0.1微秒，可以支持两路模拟量输出。

单片机并行AD转换

TLC0820 芯片接法
单片机电路
2.1 AD 转换器的选择
本实验要求使用 8 位模数转换器 TLC0820，故其电路接法唯一，具体参考芯片说明书。
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#include<iom128v.h> #include<macros.h> #include"AD.h" voidwrite_com(uchar com) { qitaport&= ~BIT(4); qitaport&= ~BIT(5); shujuport = com; qitaport = BIT(6); delay(1); qitaport&= ~BIT(6); } voidwrite_data(uchar data) { qitaport = BIT(4); qitaport&=~ BIT(5); shujuport = data; qitaport |= BIT(6); delay(1); qitaport&= ~BIT(6); } voidLCD_init() { init(); write_com(0X38); delay(1); write_com(0X01); delay(1); write_com(0X0C); delay(1); write_com(0X06); delay(1); write_com(0X80+0x40); delay(1); }

模数转换ADC0820

ADC08208-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionGeneral DescriptionBy using a half-flash conversion technique,the 8-bit ADC0820CMOS A/D offers a 1.5µs conversion time and dissipates only 75mW of power.The half-flash technique consists of 32comparators,a most significant 4-bit ADC and a least significant 4-bit ADC.The input to the ADC0820is tracked and held by the input sampling circuitry eliminating the need for an external sample-and-hold for signals moving at less than 100mV/µs.For ease of interface to microprocessors,the ADC0820has been designed to appear as a memory location or I/O port without the need for external interfacing logic.Key Specificationsj Resolution 8Bitsj Conversion Time 2.5µs Max (RD Mode)1.5µs Max (WR-RD Mode)j Low Power 75mW Maxj Total UnadjustedError±1⁄2LSB and ±1LSBFeaturesn Built-in track-and-hold function n No missing codes n No external clocking n Single supply —5V DCn Easy interface to all microprocessors,or operates stand-alonen Latched TRI-STATE outputn Logic inputs and outputs meet both MOS and T 2L voltage level specificationsn Operates ratiometrically or with any reference value equal to or less than V CCn0V to 5V analog input voltage range with single 5V supplyn No zero or full-scale adjust required n Overflow output available for cascading n 0.3"standard width 20-pin DIPn 20-pin molded chip carrier package n 20-pin small outline packagen20-pin shrink small outline package (SSOP)Connection and Functional DiagramsDual-In-Line,Small Outline and SSOP PackagesMolded Chip CarrierPackage00550101Top View00550133March 2004ADC08208-Bit High Speed µP Compatible A/D Converter with Track/Hold Function©2004National Semiconductor Corporation Connection and Functional Diagrams(Continued)Ordering InformationPart NumberTotal PackageTemperature Unadjusted ErrorRangeADC0820BCV V20A —Molded Chip Carrier0˚C to +70˚C ADC0820BCWM ±1⁄2LSBM20B —Wide Body Small Outline 0˚C to +70˚C ADC0820BCN N20A —Molded DIP 0˚C to +70˚C ADC0820CCJ ±1LSBJ20A —Cerdip−40˚C to +85˚C ADC0820CCWM M20B —Wide Body Small Outline 0˚C to +70˚C ADC0820CIWM M20B —Wide Body Small Outline −40˚C to +85˚C ADC0820CCNN20A —Molded DIP0˚C to +70˚C00550102FIGURE 1.A D C 0820 2Absolute Maximum Ratings(Notes1,2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage(V CC)10V Logic Control Inputs−0.2V to V CC+0.2V Voltage at Other Inputs and Output−0.2V to V CC+0.2V Storage Temperature Range−65˚C to+150˚C Package Dissipation at T A=25˚C875mW Input Current at Any Pin(Note5)1mA Package Input Current(Note5)4mA ESD Susceptability(Note9)900V Lead Temp.(Soldering,10sec.)Dual-In-Line Package(plastic)260˚CDual-In-Line Package(ceramic)300˚C Surface Mount PackageVapor Phase(60sec.)215˚C Infrared(15sec.)220˚COperating Ratings(Notes1,2) Temperature Range T MIN≤T A≤T MAX ADC0820CCJ−40˚C≤T A≤+85˚C ADC0820CIWM−40˚C≤T A≤+85˚C ADC0820BCN,ADC0820CCN0˚C≤T A≤70˚C ADC0820BCV0˚C≤T A≤70˚C ADC0820BCWM,ADC0820CCWM0˚C≤T A≤70˚C V CC Range 4.5V to8VConverter CharacteristicsThe following specifications apply for RD mode(pin7=0),V CC=5V,V REF(+)=5V,and V REF(−)=GND unless otherwise specified. Boldface limits apply from T MIN to T MAX;all other limits T A=T j=25˚C.Parameter Conditions ADC0820BCN,ADC0820CCN LimitUnitsADC0820CCJ ADC0820BCV,ADC0820BCWMADC0820CCWM,ADC0820CIWMTyp Tested Design Typ Tested Design(Note6)Limit Limit(Note6)Limit Limit(Note7)(Note8)(Note7)(Note8) Resolution888Bits Total Unadjusted ADC0820BCN,BCWM±1⁄2±1⁄2LSB Error ADC0820CCJ±1LSB (Note3)ADC0820CCN,CCWM,CIWM±1±1LSB ADC0820CCMSA±1±1LSB Minimum Reference 2.3 1.00 2.3 1.2kΩResistanceMaximumReference2.36 2.3 5.36kΩResistanceMaximum V REF(+)V CC V CC V CC V Input VoltageMinimum V REF(−)GND GND GND V Input VoltageMinimum V REF(+)V REF(−)V REF(−)V REF(−)V Input VoltageMaximum V REF(−)V REF(+)V REF(+)V REF(+)V Input VoltageMaximum V IN Input V CC+0.1V CC+0.1V CC+0.1V VoltageMinimum V IN Input GND−0.1GND−0.1GND−0.1V VoltageMaximum Analog CS=V CCInput Leakage V IN=V CC30.33µA Current V IN=GND−3−0.3−3µAPower Supply Sensitivity V CC=5V±5%±1/16±1⁄4±1/16±1⁄4±1⁄4LSBADC08203DC Electrical CharacteristicsThe following specifications apply for V CC =5V,unless otherwise specified.Boldface limits apply from T MIN to T MAX ;all other limits T A =T J =25˚C.ParameterConditionsADC0820BCN,ADC0820CCN Limit UnitsADC0820CCJ ADC0820BCV,ADC0820BCWM ADC0820CCWM,ADC0820CIWM Typ Tested Design Typ Tested Design (Note 6)Limit Limit (Note 6)Limit Limit (Note 7)(Note 8)(Note 7)(Note 8)V IN(1),Logical “1”V CC =5.25VCS ,WR ,RD 2.0 2.0 2.0V Input Voltage Mode 3.5 3.5 3.5V V IN(0),Logical “0”V CC =4.75V CS ,WR ,RD 0.80.80.8V Input Voltage Mode1.5 1.51.5V I IN(1),Logical “1”V IN(1)=5V;CS ,RD0.00510.0051µA Input Current V IN(1)=5V;WR 0.130.10.33µA V IN(1)=5V;Mode5020050170200µA I IN(0),Logical “0”V IN(0)=0V;CS ,RD ,WR ,−0.005−1−0.005−1µA Input Current ModeV OUT(1),Logical “1”V CC =4.75V,I OUT =−360µA; 2.42.82.4VOutput VoltageDB0–DB7,OFL ,INT V CC =4.75V,I OUT =−10µA; 4.54.64.5VDB0–DB7,OFL ,INTV OUT(0),Logical “0”V CC =4.75V,I OUT =1.6mA;0.40.340.4VOutput Voltage DB0–DB7,OFL ,INT ,RDY I OUT ,TRI-STATE V OUT =5V;DB0–DB7,RDY 0.130.10.33µA Output Current V OUT =0V;DB0–DB7,RDY −0.1−3−0.1−0.3−3µA I SOURCE ,Output V OUT =0V;DB0–DB7,OFL −12−6−12−7.2−6mA Source Current INT−9−4.0−9−5.3−4.0mA I SINK ,Output Sink V OUT =5V;DB0–DB7,OFL ,147148.47mACurrentINT ,RDY I CC ,Supply CurrentCS =WR =RD =07.5157.51315mAAC Electrical CharacteristicsThe following specifications apply for V CC =5V,t r =t f =20ns,V REF (+)=5V,V REF (−)=0V and T A =25˚C unless otherwise specified.TypTested Design ParameterConditions(Note 6)Limit Limit Units(Note 7)(Note 8)t CRD ,Conversion Time for RD Mode Pin 7=0,Figure 2 1.6 2.5µs t ACC0,Access Time (Delay from Pin 7=0,Figure 2t CRD +20t CRD +50ns Falling Edge of RD to Output Valid)t CWR-RD ,Conversion Time for Pin 7=V CC ;t WR =600ns, 1.52µsWR-RD Mode t RD =600ns;Figures 3,4t WR ,Write Time Min Pin 7=V CC ;Figures 3,4600ns Max (Note 4)See Graph 50µs t RD ,Read TimeMinPin 7=V CC ;Figures 3,4600ns(Note 4)See Grapht ACC1,Access Time (Delay from Pin 7=V CC ,t RD <t I ;Figure 3Falling Edge of RD to Output Valid)C L =15pF 190280ns C L =100pF210320nsA D C 0820 4AC Electrical Characteristics(Continued)The following specifications apply for V CC=5V,t r=t f=20ns,V REF(+)=5V,V REF(−)=0V and T A=25˚C unless otherwise specified.Typ Tested Design Parameter Conditions(Note6)Limit Limit Units(Note7)(Note8)t ACC2,Access Time(Delay from Falling Edge of RD to Output Valid)Pin7=V CC,t RD>t I;Figure4C L=15pF70120ns C L=100pF90150nst ACC3,Access Time(Delay fromRising Edge of RDY to OutputValid)R PULLUP=1k and C L=15pF30nst I,Internal Comparison Time Pin7=V CC;Figures4,58001300nsC L=50pFt1H,t0H,TRI-STATE Control R L=1k,C L=10pF100200ns(Delay from Rising Edge of RD toHi-Z State)t INTL,Delay from Rising Edge of Pin7=V CC,C L=50pFWR to Falling Edge of INT t RD>t I;Figure4t I nst RD<t I;Figure3t RD+200t RD+290nst INTH,Delay from Rising Edge of Figures2,3,4125225nsRD to Rising Edge of INT C L=50pFct INTHWR,Delay from Rising Edge of Figure5,C L=50pF175270nsWR to Rising Edge of INTt RDY,Delay from CS to RDY Figure2,C L=50pF,Pin7=050100nst ID,Delay from INT to Output Valid Figure52050nst RI,Delay from RD to INT Pin7=V CC,t RD<t I200290nsFigure3t P,Delay from End of Conversion Figures2,3,4,5500nsto Next Conversion(Note4)See GraphSlew Rate,Tracking0.1V/µsC VIN,Analog Input Capacitance45pFC OUT,Logic Output Capacitance5pFC IN,Logic Input Capacitance5pFNote1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.DC and AC electrical specifications do not apply when operatingthe device beyond its specified operating conditions.Note2:All voltages are measured with respect to the GND pin,unless otherwise specified.Note3:Total unadjusted error includes offset,full-scale,and linearity errors.Note4:Accuracy may degrade if t WR or t RD is shorter than the minimum value specified.See Accuracy vs.t WR and Accuracy vs.t RD graphs.Note5:When the input voltage(V IN)at any pin exceeds the power supply rails(V IN<V−or V IN>V+)the absolute value of current at that pin should be limitedto1mA or less.The4mA package input current limits the number of pins that can exceed the power supply boundaries with a1mA current limit to four.Note6:Typicals are at25˚C and represent most likely parametric norm.Note7:Tested limits are guaranteed to National’s AOQL(Average Outgoing Quality Level).Note8:Design limits are guaranteed but not100%tested.These limits are not used to calculate outgoing quality levels.Note9:Human body model,100pF discharged through a1.5kΩresistor.ADC08205TRI-STATE Test Circuits and Waveformst 1H0055010300550104t r =20nst 0H0055010500550106t r =20nsTiming Diagrams00550107Note:On power-up the state of INT can be high or low.FIGURE 2.RD Mode (Pin 7is Low)A D C 0820 6Timing Diagrams(Continued)00550108FIGURE 3.WR-RD Mode (Pin 7is High and t RD <t I )00550109FIGURE 4.WR-RD Mode (Pin 7is High and t RD >t I )00550110FIGURE 5.WR-RD Mode (Pin 7is High)Stand-Alone OperationADC08207Typical Performance CharacteristicsLogic Input Threshold Voltage vs.Supply VoltageConversion Time (RD Mode)vs.Temperature0055013400550135Power Supply Current vs.Temperature(not including reference ladder)Accuracy vs.t WR0055013600550137Accuracy vs.t RD Accuracy vs.t p0055013800550139A D C 0820 8Typical Performance Characteristics(Continued)Accuracy vs.V REF[V REF=V REF(+)-V REF(-)]t I,Internal Time Delay vs.Temperature0055014000550141 Output Current vs.Temperature00550142ADC08209Description of Pin FunctionsPin Name Function1V IN Analog input;range =GND ≤V IN ≤V CC 2DB0TRI-STATE data output —bit 0(LSB)3DB1TRI-STATE data output —bit 14DB2TRI-STATE data output —bit 25DB3TRI-STATE data output —bit 36WR /RDYWR-RD ModeWR:With CS low,the conversion is started on the falling edge of WR.Approximately 800ns (the preset internal time out,t I )after the WR rising edge,the result of the conversion will be strobed into the output latch,provided that RD does not occur prior to this time out (see Figures 3,4).RD ModeRDY:This is an open drain output (no internal pull-up device).RDY will go low after the falling edge of CS;RDY will go TRI-STATE when the result of theconversion is strobed into the output latch.It is used to simplify the interface to a microprocessor system (see Figure 2).7ModeMode:Mode selection input —it is internally tied to GND through a 50µA current source.RD Mode:When mode is low WR-RD Mode:When mode is high8RDWR-RD ModeWith CS low,the TRI-STATE data outputs (DB0-DB7)will be activated when RD goes low (see Figure 5).RD can also be used to increase the speed of the converter by reading data prior to thepreset internal time out (t I ,∼800ns).If this is done,the data result transferred to output latch is latched after the falling edge of the RD (see Figures 3,4).RD ModeWith CS low,the conversion will start with RD going low,also RD will enable the TRI-STATE data outputs at the completion of the conversion.RDY going TRI-STATE and INT going low indicates thecompletion of the conversion (see Figure 2).Pin Name Function9INTWR-RD ModeINT going low indicates that theconversion is completed and the data result is in the output latch.INT will go low,∼800ns (the preset internal time out,t I )after the rising edge of WR (see Figure 4);or INT will go low after the falling edge of RD ,if RD goes low prior to the 800ns time out (see Figure 3).INT is reset by the rising edge of RD or CS (see Figures 3,4).RD ModeINT going low indicates that theconversion is completed and the dataresult is in the output latch.INT is reset by the rising edge of RD or CS (see Figure 2).10GND Ground11V REF (−)The bottom of resistor ladder,voltage range:GND ≤V REF (−)≤V REF (+)(Note 5)12V REF (+)The top of resistor ladder,voltage range:V REF (−)≤V REF (+)≤V CC (Note 5)13CS CS must be low in order for the RD or WR to be recognized by the converter.14DB4TRI-STATE data output —bit 415DB5TRI-STATE data output —bit 516DB6TRI-STATE data output —bit 617DB7TRI-STATE data output —bit 7(MSB)18OFLOverflow output —If the analog input is higher than the V REF (+),OFL will be low at the end of conversion.It can be used to cascade 2or more devices to have more resolution (9,10-bit).This output is always active and does not go into TRI-STATE as DB0–DB7do.19NC No connection 20V CCPower supply voltage1.0Functional Description1.1GENERAL OPERATIONThe ADC0820uses two 4-bit flash A/D converters to make an 8-bit measurement (Figure 1).Each flash ADC is made up of 15comparators which compare the unknown input to a reference ladder to get a 4-bit result.To take a full 8-bit reading,one flash conversion is done to provide the 4most significant data bits (via the MS flash ADC).Driven by the 4MSBs,an internal DAC recreates an analog approximation of the input voltage.This analog signal is then subtracted from the input,and the difference voltage is converted by a second 4-bit flash ADC (the LS ADC),providing the 4least significant bits of the output data word.The internal DAC is actually a subsection of the MS flash converter.This is accomplished by using the same resistor ladder for the A/D as well as for generating the DAC signal.The DAC output is actually the tap on the resistor ladderA D C 0820101.0Functional Description(Continued)which most closely approximates the analog input.In addi-tion,the“sampled-data”comparators used in the ADC0820provide the ability to compare the magnitudes of severalanalog signals simultaneously,without using input summingamplifiers.This is especially useful in the LS flash ADC,where the signal to be converted is an analog difference.1.2THE SAMPLED-DATA COMPARATOREach comparator in the ADC0820consists of a CMOS in-verter with a capacitively coupled input(Figures6,7).Ana-log switches connect the two comparator inputs to the inputcapacitor(C)and also connect the inverter’s input and out-put.This device in effect now has one differential input pair.A comparison requires two cycles,one for zeroing the com-parator,and another for making the comparison.In the first cycle,one input switch and the inverter’s feedbackswitch(Figure6)are closed.In this interval,C is charged tothe connected input(V1)less the inverter’s bias voltage(V B,approximately1.2V).In the second cycle(Figure7),thesetwo switches are opened and the other(V2)input’s switch isclosed.The input capacitor now subtracts its stored voltagefrom the second input and the difference is amplified by theinverter’s open loop gain.The inverter’s input(V B')becomesand the output will go high or low depending on the sign ofV B'−V B.The actual circuitry used in the ADC0820is a simple butimportant expansion of the basic comparator describedabove.By adding a second capacitor and another set ofswitches to the input(Figure8),the scheme can be ex-panded to make dual differential comparisons.In this circuit,the feedback switch and one input switch on each capacitor(Z switches)are closed in the zeroing cycle.A comparison isthen made by connecting the second input on each capacitorand opening all of the other switches(S switches).Thechange in voltage at the inverter’s input,as a result of thechange in charge on each input capacitor,will now dependon both input signal differences.1.3ARCHITECTUREIn the ADC0820,one bank of15comparators is used in each4-bit flash A/D converter(Figure12).The MS(most signifi-cant)flash ADC also has one additional comparator to detectinput overrange.These two sets of comparators operatealternately,with one group in its zeroing cycle while the otheris comparing.When a typical conversion is started,the WR line is broughtlow.At this instant the MS comparators go from zeroing to00550112•V O=V B•V on C=V1−V B•C S=stray input node capacitor•V B=inverter input bias voltageZeroing PhaseFIGURE6.Sampled-Data Comparator00550113Compare PhaseFIGURE7.Sampled-Data Comparator0055011400550145FIGURE8.ADC0820Comparator(from MS Flash ADC)ADC08201.0Functional Description(Continued)comparison mode (Figure 11).When WR is returned high after at least 600ns,the output from the first set of compara-tors (the first flash)is decoded and latched.At this point the two 4-bit converters change modes and the LS (least signifi-cant)flash ADC enters its compare cycle.No less than 600ns later,the RD line may be pulled low to latch the lower 4data bits and finish the 8-bit conversion.When RD goes low,the flash A/Ds change state once again in preparation for the next conversion.Figure 11also outlines how the converter’s interface timing relates to its analog input (V IN ).In WR-RD mode,V IN is measured while WR is low.In RD mode,sampling occurs during the first 800ns of RD.Because of the input connec-tions to the ADC0820’s LS and MS comparators,the con-verter has the ability to sample V IN at one instant (Section 2.4),despite the fact that two separate 4-bit conversions are being done.More specifically,when WR is low the MS flash is in compare mode (connected to V IN ),and the LS flash is in zero mode (also connected to V IN ).Therefore both flash ADCs sample V IN at the same time.1.4DIGITAL INTERFACEThe ADC0820has two basic interface modes which are selected by strapping the MODE pin high or low.RD ModeWith the MODE pin grounded,the converter is set to Read mode.In this configuration,a complete conversion is done by pulling RD low until output data appears.An INT line is provided which goes low at the end of the conversion as well as a RDY output which can be used to signal a processor that the converter is busy or can also serve as a system Transfer Acknowledge signal.RD Mode (Pin 7is Low)00550116When in RD mode,the comparator phases are internally triggered.At the falling edge of RD,the MS flash converter goes from zero to compare mode and the LS ADC’s com-parators enter their zero cycle.After 800ns,data from the MS flash is latched and the LS flash ADC enters compare mode.Following another 800ns,the lower 4bits are recov-ered.WR then RD ModeWith the MODE pin tied high,the A/D will be set up for the WR-RD mode.Here,a conversion is started with the WR input;however,there are two options for reading the outputdata which relate to interface timing.If an interrupt driven scheme is desired,the user can wait for INT to go low before reading the conversion result (Figure 10).INT will typically go low 800ns after WR’s rising edge.However,if a shorter conversion time is desired,the processor need not wait for INT and can exercise a read after only 600ns (Figure 9).If this is done,INT will immediately go low and data will appear at the outputs.Stand-AloneFor stand-alone operation in WR-RD mode,CS and RD can be tied low and a conversion can be started with WR.Data will be valid approximately 800ns following WR’s rising edge.WR-RD Mode (Pin 7is High)Stand-Alone Operation0055011900550117FIGURE 9.WR-RD Mode (Pin 7is High and t RD <t I )00550118FIGURE 10.WR-RD Mode (Pin 7is High and t RD >t I )A D C 08201.0Functional Description(Continued)OTHER INTERFACE CONSIDERATIONSIn order to maintain conversion accuracy,WR has a maxi-mum width spec of50µs.When the MS flash ADC’s sampled-data comparators(Section1.2)are in comparison mode(WR is low),the input capacitors(C,Figure8)must hold their charge.Switch leakage and inverter bias current can cause errors if the comparator is left in this phase for too long.Since the MS flash ADC enters its zeroing phase at the end of a conversion(Section1.3),a new conversion cannot be started until this phase is complete.The minimum spec for this time(t P,Figures2,3,4,5)is500ns.00550120Note:MS means most significantLS means least significantFIGURE11.Operating Sequence(WR-RD Mode)ADC0820Detailed Block Diagram00550115FIGURE 12.A D C 08202.0Analog Considerations2.1REFERENCE AND INPUTThe two V REF inputs of the ADC0820are fully differential and define the zero to full-scale input range of the A to D con-verter.This allows the designer to easily vary the span of the analog input since this range will be equivalent to the voltage difference between V IN(+)and V IN(−).By reducing V REF(V REF=V REF(+)−V REF(−))to less than5V,the sensitivity of the converter can be increased(i.e.,if V REF=2V then1 LSB=7.8mV).The input/reference arrangement also facili-tates ratiometric operation and in many cases the chip power supply can be used for transducer power as well as the V REF source.This reference flexibility lets the input span not only be varied but also offset from zero.The voltage at V REF(−)sets the input level which produces a digital output of all zeroes. Though V IN is not itself differential,the reference design affords nearly differential-input capability for most measure-ment applications.Figure13shows some of the configura-tions that are possible.2.2INPUT CURRENTDue to the unique conversion techniques employed by the ADC0820,the analog input behaves somewhat differently than in conventional devices.The A/D’s sampled-data com-parators take varying amounts of input current depending on which cycle the conversion is in.The equivalent input circuit of the ADC0820is shown in Figure14.When a conversion starts(WR low,WR-RD mode),all input switches close,connecting V IN to thirty-one 1pF capacitors.Although the two4-bit flash circuits are not both in their compare cycle at the same time,V IN still sees all input capacitors at once.This is because the MS flash converter is connected to the input during its compare inter-val and the LS flash is connected to the input during its zeroing phase(Section1.3).In other words,the LS ADC uses V IN as its zero-phase input.The input capacitors must charge to the input voltage through the on resistance of the analog switches(about5kΩto10kΩ).In addition,about12pF of input stray capacitance must also be charged.For large source resistances,the analog input can be modeled as an RC network as shown in Figure15.As R S increases,it will take longer for the input capacitance to charge.In RD mode,the input switches are closed for approximately 800ns at the start of the conversion.In WR-RD mode,the time that the switches are closed to allow this charging is the time that WR is low.Since other factors force this time to be at least600ns,input time constants of100ns can be accommodated without special consideration.Typical total input capacitance values of45pF allow R S to be1.5kΩwithout lengthening WR to give V IN more time to settle.External Reference2.5V Full-Scale Power Supply as Reference Input Not Referred to GND005501210055012200550123FIGURE13.Analog Input Options ADC08202.0Analog Considerations(Continued)2.3INPUT FILTERINGIt should be made clear that transients in the analog input signal,caused by charging current flowing into V IN ,will not degrade the A/D’s performance in most cases.In effect the ADC0820does not “look”at the input when these transientsoccur.The comparators’outputs are not latched while WR is low,so at least 600ns will be provided to charge the ADC’s input capacitance.It is therefore not necessary to filter out these transients by putting an external cap on the V IN termi-nal.2.4INHERENT SAMPLE-HOLDAnother benefit of the ADC0820’s input mechanism is its ability to measure a variety of high speed signals without the help of an external sample-and-hold.In a conventional SAR type converter,regardless of its speed,the input must re-main at least 1⁄2LSB stable throughout the conversion pro-cess if full accuracy is to be maintained.Consequently,for many high speed signals,this signal must be externally sampled,and held stationary during the conversion.Sampled-data comparators,by nature of their input switch-ing,already accomplish this function to a large degree (Sec-tion 1.2).Although the conversion time for the ADC0820is 1.5µs,the time through which V IN must be 1⁄2LSB stable is much smaller.Since the MS flash ADC uses V IN as its “compare”input and the LS ADC uses V IN as its “zero”input,the ADC0820only “samples”V IN when WR is low (Sections 1.3and 2.2).Even though the two flashes are not done simultaneously,the analog signal is measured at one instant.The value of V IN approximately 100ns after the rising edge of WR (100ns due to internal logic prop delay)will be the measured value.Input signals with slew rates typically below 100mV/µs can be converted without error.However,because of the input time constants,and charge injection through the opened comparator input switches,faster signals may cause errors.Still,the ADC0820’s loss in accuracy for a given increase in signal slope is far less than what would be witnessed in a conventional successive approximation device.An SAR type converter with a conversion time as fast as 1µs would still not be able to measure a 5V 1kHz sine wave without the aid of an external sample-and-hold.The ADC0820,with no such help,can typically measure 5V,7kHz waveforms.00550124FIGURE 14.00550125FIGURE 15.A D C 08203.0Typical Applications8-Bit Resolution Configuration005501269-Bit Resolution Configuration00550127ADC08203.0Typical Applications(Continued)Telecom A/D Converter00550128•V IN =3kHz max ±4V P•No track-and-hold needed •Low power consumptionMultiple Input Channels005501298-Bit 2-Quadrant Analog Multiplier00550130A D C 08203.0Typical Applications(Continued)Fast Infinite Sample-and-Hold00550131ADC08203.0T y p i c a l A p p l i c a t i o n s(C o n t i n u e d )D i g i t a l W a v e f o r m R e c o r d e00550132A D C 0820Physical Dimensionsinches (millimeters)unless otherwise notedHermetic Dual-In-Line Package (J)Order Number ADC0820CCJ NS Package Number J20ASO Package (M)Order Number ADC0820BCWM,ADC0820CCWM or ADC0820CIWMNS Package Number M20BADC082021Physical Dimensionsinches (millimeters)unless otherwise noted (Continued)Molded Dual-In-Line Package (N)Order Number ADC0820BCN or ADC0820CCNNS Package Number N20AMolded Chip Carrier Package (V)Order Number ADC0820BCV NS Package Number V20AA D C 0820 22NotesLIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices orsystems which,(a)are intended for surgical implant into the body,or(b)support or sustain life,and whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury to the user.2.A critical component is any component of a lifesupport device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.BANNED SUBSTANCE COMPLIANCENational Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification(CSP-9-111C2)and the Banned Substances and Materials of Interest Specification (CSP-9-111S2)and contain no‘‘Banned Substances’’as defined in CSP-9-111S2.National Semiconductor Americas CustomerSupport CenterEmail:new.feedback@ Tel:1-800-272-9959National SemiconductorEurope Customer Support CenterFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)6995086208English Tel:+44(0)8702402171Français Tel:+33(0)141918790National SemiconductorAsia Pacific CustomerSupport CenterEmail:ap.support@National SemiconductorJapan Customer Support CenterFax:81-3-5639-7507Email:jpn.feedback@Tel:81-3-5639-7560 ADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。

微机原理实验报告--数模转换

微机原理实验报告实验题目：数/模转换器DAC0832系部：电子与信息工程系学生姓名：专业班级：学号：指导教师：2013.12.30一. 实验目的1.掌握D/A转换原理；2.熟悉D/A芯片接口设计方法；3.掌握DAC0832芯片的使用方法。

二. 实验设备1.PC微机一台；2.TD-PIT实验装置一台；3.示波器一台。

三. 实验要求用DAC0832设计一个D/A转换接口电路，采用单缓冲工作方式，产生方波、三角波、锯齿波和正弦波。

四．实验原理1.DAC3802的结构及性能（1）输入/输出信号。

D7-D为8位数据输入线；IOUT1为DAC电流输出1，I OUT2为DAC电流输出2，IOUT1和IOUT2之和为一常量；RFB为反馈信号输入端，反馈电阻在芯片内。

（2）控制信号。

ILE为允许输入锁存信号；WR1和WR2分别为锁存输入数据信号和锁存输入寄存器到DAC寄存器的写信号；XFER为传送控制信号；CS为片选信号。

（3）电源。

VCC 为主电源，电压范围为+5V到+15V；VREF为参考输入电压，范围为-10V到+10V。

DAC0832管脚及其内部结构框图2.工作方式外部五个控制信号：ILE，CS，WR1,WR2，XFER连接方式的不同，可工作于多种方式:直通方式，单缓冲方式，双缓冲方式（1）直通方式ILE接高、CS、WR1、WR2、XFER接地，两级寄存器均直通；（2）单缓冲方式两级寄存器一个受控，一个直通；（3）双缓冲方式两级寄存器均受控。

0832为电流输出型D/A ，要得模拟电压，必需外加转换电路（运放）。

五. 实验内容1.硬件电路图：2.软件程序设计（1）产生方波stack segment stack 'stack'dw 32 dup(?)stack endscode segmentbegin proc farassume ss:stack,cs:codepush dssub ax,axpush axMOV DX,0D800H；片选信号输入地址MOV AL,0NEXT:OUT DX,ALMOV DX,0D800HOUT DX,ALLOOP $；延时NOT AL；求反，由高电平转为低电平或有低电平转为高电平 PUSH AX；保护数据MOV AH,11INT 21HCMP AL,0；有按键退出POP AXJZ NEXTretbegin endpcode endsend begin（2）产生三角波stack segment stack 'stack'dw 32 dup(?)stack endsdata segmentdata endscode segmentbegin proc farassume ss:stack,cs:code,ds:datapush dssub ax,axpush axMOV DX,0D800HMOV AL,0NEXT:OUT DX,ALCALL DELAY；调用延时CMP AL,0FFHJNE NEXT；自增至15NEXT1:OUT DX,ALCALL DELAY；调用延时DEC ALCMP AL,0JNE NEXT1PUSH AXMOV AH,11INT 21HCMP AL,0POP AXJZ NEXT；自减至0retbegin endpDELAY PROCPUSH CXMOV CX,10000LOOP $POP CXRETDELAY ENDP；延时子程序code endsend begin（3）产生锯齿波stack segment stack 'stack' dw 32 dup(?)stack endscode segmentbegin proc farassume ss:stack,cs:code push dssub ax,axpush axMOV DX,0D800HMOV AL,0UP:OUT DX,ALINC ALPUSH AX；保护数据MOV AH,11INT 21HCMP AL,0JZ UP；循环从0自增至15retbegin endpcode endsend begin（4）产生正弦波stack segment stack 'stack'dw 32 dup(?)stack endsdata segmentDATA DB7FH,87H,8FH,97H,9FH,0A6H,0AEH,0B5H,0BCH,0C3H,0CAH,0D0H,0D6H,0DCH,0E1H,0E6H,0EBH,0EFH,0F2H,0F6H,0F8H,0FAH,0FCH,0FDH,0FEH,0FFH,0FEH,0FDH,0FCH,0FAH,0F8H,0F6H,0F2H,0EFH,0EBH,0E6H,0E1H,0DCH,0D6H,0D0H,0CAH,0C3H,0BCH,0B5H,0AEH,0A6H,9FH,97H,8FH,87H,7FH,77H,6FH,67H,5FH,58H,50H,49H,42H,3BH,34H,2EH,28H,22H,1DH,18H,13H,0FH,0CH,8H,6H,4H,2H,1H,0,0,0,1H,2H,4H,6H,8H,0CH,0FH,13H,18H,1DH,22H,28H,2EH,34H,38H,42H,49H,50H,58H,5FH,67H,6FH,77H；建表，在正弦波一个周期内均匀采样100个点，用matlab将每点的值转换为相应的波形数字量（该处用16进制数表示）data endscode segmentbegin proc farassume ss:stack,cs:code,ds:datapush dssub ax,axpush axmov ax,datamov ds,axAG:MOV SI,OFFSET DATA；将表DATA放入SI中MOV DX,0D800HMOV BX,0NEXT:MOV AL,BYTE PTR[SI]OUT DX,ALCALL DELAY；调用延时INC BXINC SICMP BX,100JE AGPUSH AX；保护数据MOV AH,11CMP AL,0POP AXJZ NEXT；循环100次将表中的值输出 retbegin endpDELAY PROCPUSH CXMOV CX,10000LOOP $POP CXRETDELAY ENDP；延时子程序code endsend begin六. 实验结果用示波器观测波形，截图如下：1.方波2.三角波3.锯齿波4.正弦波七. 实验总结在本次实验中，首先自己在课外将实验原理充分掌握，提前画好电路图，并思考软件部分的代码核心，进入实验室后，进行电路连接及与软件的连调。

ADC0820实验

ADC0820实验一：实验要求按要求连接线路，编译程序写入单片机，通过串口调试助手察看返回值，并计算实际电压值。

二：实验目的1．掌握ADC0820与单片机的接口电路连接方式2．学会编程实现单片机对ADC0820的控制。

三：实验原理A/D转换器（以下简称ADC）是一种用来将连续的模拟信号转换成二进制数的器件。

一个完整的ADC通常包括这样一些信号：模拟输入信号、参考电压、数字输出信号、启动转换信号、转换结束信号、数据输出允许信号等。

高速ADC 一般还采用保持电路，以减少孔径误差。

ADC按结构分有很多种，按其采样速度和精度可分为：多比较器快速（Flash）ADC；数字跃升式（Digital Ramp）ADC；逐次逼近ADC；管道ADC；Sigma-Delta ADC。

任何一种ADC的输出都等于2的N次方乘以它的增益（输入信号），再除以它的参考电压。

ADC0820是一种多比较器（Flash），CMOS、高速、8位ADC，属于，带有采样/保持功能，双列20脚封装,8位串并行比较型模数转换器,电源电压=5V,电源电流=15mA,典型模拟输入电压=5V,典型基准输入电压=5V,工作温度=0～70℃。

多比较器（Flash）ADC中用到的比较器很多，如一个8位的ADC就需要255个比较器。

该类产品采样速率确实很高，但因为多个比较器的存在，其功耗很大，而且管芯也较大。

以下是ADC0820的引脚图：VREF（+），VREF（-）：比较电压的正极和接地极。

/OFL：溢出输出，当模拟输入电压大于VREF（+）时，/OFL在转换结束后为LO，/OFL可以用来级联更多的芯片以实现更高位数的数模转换。

MODE：模式选择输入，当MODE为HI时为RD模式，当MODE为LO 时为WR-RD模式。

/INT：中断请求信号输出，低电平动作。

/WR/RDY：用来启动转换的控制输入，相当于ADC转换的开始（/CS=0时），当/WR由HI变为LO时，转换器被清除；当/WR回到HI时，转换正式开始。

TLC0820A中文资料

2008年北京市大学生电子设计竞赛芯片资料TLC372 双路通用LinCMOSTM 差动比较器∙单电源或双电源供电∙宽电源范围供电2V~18V∙5V电源时低漏电流150μA∙TTL输入电平时快速响应时间200ns∙内置ESD保护∙高输入阻抗典型值1012Ω∙外部低输入偏置电流典型值5PA∙超稳定的低输入偏置电压∙输入失调电压在最恶劣的输入条件下变化0.23μV/月，包括第一个30天∙共模输入电压包括地∙输出兼容TTL MOS CMOS∙引脚兼容LM393引脚功能∙1IN - 1路比较器反相输入∙1IN+ 1路比较器通向输入∙1OUT 1路比较器输出∙2IN - 2路比较器反相输入∙2IN+ 2路比较器同相输入∙2OUT 2路比较器输出∙GND 电源地∙VCC 电源正∙NC 空脚，不连接这个器件由两个独立电压比较器，使用LinCMOSTM工艺制造的，支持单电源。

输出是N 沟道漏极开路，实现正逻辑连接。

完全最大的测定值运行环境范围（除非另行注释）支持电压VDD(注释1)...............................................................+18V差分输入电压VID(注释2)...........................................................±18V输入电压范围.....................................................................-0.3~18V输出电压VO (18V)输入电流II ......................................................................±5mA输出电流IO.......................................................................20mA输出短路到地持续电流.............................................................无限制注释：1、差分电压除外，全部电压相对于地。

报告样板：实验8模数转换器(ADC)

模/数转换器（ADC）实验报告学院名称：软件学院学生学号：0681490008学生姓名：谭家海同作者: 周杰实验日期：2008-11-16实验题目：实验八模/数转换器（ADC）一、实验目的：1)了解模/数转换器ADC的工作原理。

2)学习ADC模拟“看门狗”功能的应用，了解如何设置ADC模式和通道，进一步学习模拟“看门狗”的选择与使用。

3)学习并掌握解模/数转换器ADC在单通道模式模式下启动插入转换链，通过PWM定时器的TRGO信号来触发插入转换的功能与原理。

4)学习并掌握主程序中配置ADC的工作参数和模拟看门狗参数的配置。

二、实验环境（软件与硬件）：软件环境：IAR集成开发环境。

硬件环境：STR750开发板。

三、实验内容及实验原理1．模/数转化器（ADC）的主要特点：1）在最大的ADC时钟频率（F CK_ADC＝8MHz）下转换时间3.5µs有以下因素组成：采样时间：11个ADC时钟周期；转换时间：19个ADC 时钟周期；2）分辨度：10Bits；3）单调性：好；4）无缺失码：有保证；5）输入为0时的读数：0000h6）满刻度读数：03FFh；7）16×10位数据寄存器（每个通道一个寄存器）；8）单通道模式或扫描模式（不需任何软件交互可成功地转换16个通道的部分或全部内容）；9）在定时器TIM0OC2触发后开始转换（在单通道模式或扫描模式）；10 链式注入模式，由定时器PWM的TRGO触发；11）低功耗模式；12）当4个可选的模拟看门狗通道的转换值超出软件程序预先设定的门限时，则产生中断；13）转换完成会自动产生DMA请求。

可以由软件或硬件使能DMA转换器（使用连接到TM2定时器OC2上的DMA外部使能触发器）。

2．功能描述下面分别介绍ADC的功能特性及其配置方法。

1)校准开始：为了达到目标精确度，在每次家电或从停止待命模式重启时，强制校准ADC。

2)转换开始：用户由三种方法启动编程转换过程。

实验七DAC0832数模转换实验

实验七、DAC0832数模转换实验一、实验目的1、掌握DAC0832直通方式、单缓冲方式、双缓冲方式的编程方法2、掌握DA转换程序的编程方法和调试方法。

二、实验说明美国国家半导体公司产品，具有两个输入数据寄存器的8位DAC,能直接与MCS-51单片机相连。

主要特性如下：分辨率为8位；* 电流输出，稳定时间为1 s；* 可双缓冲输入、单缓冲输入或直接数字输入；* 单一电源供电（+5～+15V）；DAC0832的逻辑结构：其引脚分布如图所示：DAC0832各引脚说明：DI0-DI7：转换数据输入端；CS：片选信号输入端。

ILE：数据锁存允许信号输入端，高电平有效。

WR1：输入寄存器写选通控制端。

当CS*=0、ILE=1、 WR1*=0时，数据信号被锁存在输入寄存器中。

Xfer：数据传送控制信号输入端，低电平有效。

WR2：DAC寄存器写选通控制端。

当XFER*=0，WR2* =0 时，输入寄存器状态传入DAC 寄存器中。

Iout1：电流输出1端，当数据全为1时，电流输出最大；当数据全为0时，输出电流最小。

Iout2：电流输出2端。

DAC0802具有Iout1+Iout2=常数的特性。

Rfb：反馈电阻端。

Vref：基准电压输入端，是外加的高精度电压源，它与芯片内的电阻网络相连接，该电压范围为-10V~10V；VCC和GND：芯片的电源和接地端。

DAC内部有两个寄存器，而这两个寄存器的控制信号有五个，输入寄存器有LIE、CS、WR1控制，DAC寄存器由WR2、Xref控制，用软件指令控制这五个控制端可以实现三种工作方式：直通方式，单缓冲方式，双缓冲方式。

直通方式是将两个寄存器的五个控制端预先置为有效信号，两个寄存器都开通，只要有数字信号输入就立即进入DA转换。

单缓冲方式是使DAC0832的两个输入寄存器中由一个处于直通方式，另一个处于受控方式，可以将WR2和Xref相连接到地上，并把WR1接到80C51的WR上，LIE接高电平，CS 接高位地址或地址译码的输出端上。

TLC0820A中文资料

元器件交易网IMPORTANT NOTICETexas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductorproduct or service without notice, and advises its customers to obtain the latest version of relevant informationto verify, before placing orders, that the information being relied on is current.TI warrants performance of its semiconductor products and related software to the specifications applicable atthe time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques areutilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of eachdevice is not necessarily performed, except those mandated by government requirements.Certain applications using semiconductor products may involve potential risks of death, personal injury, orsevere property or environmental damage (“Critical Applications”).TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTEDTO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHERCRITICAL APPLICATIONS.Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TIproducts in such applications requires the written approval of an appropriate TI officer. Questions concerningpotential risk applications should be directed to TI through a local SC sales office.In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards should be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance, customer product design, software performance, orinfringement of patents or services described herein. Nor does TI warrant or represent that any license, eitherexpress or implied, is granted under any patent right, copyright, mask work right, or other intellectual propertyright of TI covering or relating to any combination, machine, or process in which such semiconductor productsor services might be or are used.Copyright © 1995, Texas Instruments Incorporated。

模数转换器(ADC)实验

模/数转换器(ADC)实验1.实验目的(1)掌握LM3S8962中的ADC 的基本原理和使用方法(2)掌握CCS 开发环境平台2.实验内容(1)ARM 的初始化配置(2)ADC 的初始化配置(3)ADC 对内部温度传感器的温度值采样输出的实验3.ADC 的工作原理ADC 能够将连续变化的模拟电压转化成离散的数字量。

通常通过传感器或变送器将生产过程中的工艺参数转换为电信号，然后经过模拟量输入通道来处理：一般由I/V 变换将电流信号转化为电压信号处理，然后由多路转换器选择输入通道，经过采样保持器保持信号后由A/D 转换器转换信号，转换过程由接口及控制逻辑控制。

在上述模拟输入通道中A/D 转换器和接口及控制逻辑是必不可少的两块。

下图1是ADC 的模块框图。

模数转换器ADCPSSI ADCSAC ADCSSFIFO0ADCSSFIFO1ADCSSFIFO2ADCSSFIFO3ADCSSMUX0ADCSSCTL0ADCSSFSTAT0ADCACTSS ADCOSTATADCUSTATADCSSPRI 采样序列发生器0ADCSSMUX1ADCSSCTL1ADCSSFSTAT1采样序列发生器1ADCSSMUX2ADCSSCTL2ADCSSFSTAT2采样序列发生器2ADCSSMUX3ADCSSCTL3ADCSSFSTAT3采样序列发生器3SS3ADCEMUXADCIMADCRISADCISC 中断控制模拟输入硬件平均电路FIFO 块控制状态SS2SS1SS0比较器GPIO定时器PWM 比较器GPIO定时器PWM 比较器GPIO定时器PWM 比较器GPIO 定时器PWM 触发事件SS0中断SS0中断SS0中断SS0中断图1 ADC 模块框图LM3S8962 ADC 模块的转换分辨率为10位，并支持4个输入通道，以及一个内部温度传感器。

ADC 模块含有4个可编程的采样序列发生器，它可在无需控制器干涉的情况下对多个模拟输入源进行控制。

TLC0820A中文资料

输出是N 沟道漏极开路，实现正逻辑连接。

实验三数模转换器(0809)

实验三数/模转换器（0809）一．实验目的了解模/数转换的基本原理。

掌握ADC0809的使用方法二．实验内容1．通过实验台左下角电位器RW1输出0—5V直流电压送入ADC0809通道0（INT0）,利用DEBUG 的输出命令启动A/D转换器，输入命令读取转换结果，验证输入电压与转换后数字的关系。

启动IN0开始转换：O 0298,0读取转换结果：I 02982．编程采集IN0输入的电压，在屏幕上显示出转换结果。

三．实验提示1．ADC0809的IN0口地址为298H，IN1口地址为299H。

微机分配的ADC0809的IN0口地址为0C418H,IN1口地址为0C419H。

2．IN0单极性输入电压与转换后数字的关系为：N=Ui/（Uref/256）其中Ui为输入电压，Uref为参考电压，这里参考电压为PC机的+5V电压。

3．一次A/D转换的程序可以为MOV DX ,口地址；启动结果OUT DX，AL; 延时IN AL, DX ;读取转换结果放在AL中四．参考流程图五．输入源程序CODE SEGMENT ASSUME CS:CODE START:MOV DX,0C418H OUT DX,ALDELAY:IN AL,DXMOV BL,ALMOV CL,4SHR BL,CLMOV DL,BLCMP DL,09HJBE SHOW1ADD DL,07HSHOW1:ADD DL,30HMOV AH,02HINT 21HMOV BL,ALAND BL,0FHMOV DL,BLCMP DL,09HJBE SHOW2ADD DL,07HSHOW2:ADD DL,30HMOV AH,02HINT 21HMOV AH,02HINT 21HMOV DL,0FFHMOV AH,O6HINT 21HJZ STARTMOV AH,4CHINT 21HCODE ENDSEND START源程序分析本程序结构比较简单。

在程序开头设置了IN0口地址0C418H,设为连接口。

7-TLC0820模数转换器应用实验

三、模数转换原理
1、双积分型（低速高精度，后面的实验再介绍）双积分型（低速高精度，后面的实验再介绍） 2、逐次比较型
数字输出控制
比较器基准 DAC －＋模拟输入
以三位为例，简单说明其原理。以三位为例，简单说明其原理。假如基准为7V 被测模拟电压为4V9 7V， 4V9。假如基准为7V，被测模拟电压为4V9。那么模数转换器的逐次比较过程如下：那么模数转换器的逐次比较过程如下：第一次送数到数模转换器为100B 模拟输出为4V 100B， 4V，第一次送数到数模转换器为100B，模拟输出为4V，比较器的输出为逻辑1 则高位固定为1 比较器的输出为逻辑1，则高位固定为1；第二次送110B 模拟输出为6V 110B， 6V，第二次送110B，模拟输出为6V，比较器的输出为逻则次高位固定为0 辑0，则次高位固定为0；第三次送101B 模拟输出为5V 101B， 5V，第三次送101B，模拟输出为5V，比较器的输出为逻则低位固定为0 辑0，则低位固定为0；经过逐次送数后，使最后的数字输出结果为100B 100B。经过逐次送数后，使最后的数字输出结果为100B。这个过程类似砝码称重。由此可见，输入4V9 4V9而转换这个过程类似砝码称重。由此可见，输入4V9而转换 100B，即显示为4V的数字量，最大误差大约为1V 4V的数字量 1V。为100B，即显示为4V的数字量，最大误差大约为1V。更多位的推论同学们可以自己做一下，显而易见，更多位的推论同学们可以自己做一下，显而易见，位数越多精度越高。数越多精度越高。
注1
注2
在写－读方式下 ( MODE=1 ) ：伴随变低，伴随CS变低变低，在写－作为输入信号的下降沿变换开始；在WR作为输入信号的下降沿变换开始；作为输入信号的下降沿变换开始在读方式下( 在读方式下 MODE=0 )：RDY在CS的下降沿：在的下降沿变低，变换结果选通进入输出锁存器后变为高阻态。变低，变换结果选通进入输出锁存器后变为高阻态。

实验七 DA转换器的应用

单极性转换电路
+5V
20 19 8
D7 13 D6 14 D5 D4 D3 D2 D1 D0
15 16 4 5 6 7 1
VCC VREF ILE
Rfb DAC0832 Iout1 Iout2
CSWR1WR2 XFER AGND DGND
2 3 10 17 18
9 11 12
+
VO
VREF Vo = − 8 (d7 ⋅ 27 + d6 ⋅ 26 +... + d1 ⋅ 21 + d0 ⋅ 20 ) 2 输入范围 00000000—11111111、输出 0 -- +5V 、
三、实验原理
CS WR1 AGND D3 D2 D1 D0 VREF RF DGND
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16
VCC ILE WR2 XFER D4 D5 D6 D7 Iout1 Iout2
DAC0832
15 14 13 12 11
DAC0832功能框图及引脚功能框图及引脚
+
10/20K
+
VO
2R=(20+8.2)K
-VREF
WR1
VREF V (d7 ⋅ 27 + d6 ⋅ 26 +... + d1 ⋅ 21 + d0 ⋅ 20 )+ REF 28 2 输入范围 00000000—11111111、输出、输出-2.5 — +2.5V Vo = −
四、实验内容
1.用DAC0832 实现用实现D/A单极性转换；单极性转换；单极性转换 2. 用DAC0832 实现实现D/A双极性转换。双极性转换。双极性转换

微机原理实验——数模转换报告

学号：38152115 姓名：张亚婷实验日期：2010年12月28日一、实验名称：数模转换二、实验目的：了解数模转换的原理，学习数模转换芯片的使用方法，掌握利用数模转换芯片产生方波或正弦波的方法。

三、实验内容：① 在数据段中存放好对应能够产生方波或正弦波的数字量，正弦波要求20个值。

② 编写程序将数据段中的数字量送到DA0832的输出端产生方波或正弦波。

四、实验原理图：电路中DA0832采用单缓冲方式，具有单、双极性输出端（图示中分别为Ua 、Ub ）。

五、实验流程图：NOYESNOYESD7D0...WR1CS XFER WR2Vref ILE-+Rf Iout 1Iout 2Ua +5V DB 290H~298H IOW -+20K 20K 10K Ub (-5~0V)(-5~+5V)定义数据段，将正弦波对应的数字量存入将20个数字量依次取出，在输出端输出有键按下用电压表测量电压值并记录有键按下返回DOS六、实验结论：在电路输出Ub端，使用电压表测量其电压值并记录，记录20个值之后使用模拟波形将测量值导入，结果图如下：七、实验心得感想：这次硬件实验，主要的心得有：硬件外部连线部分比较主要，实验时将外部电路开启更是重要，在本次试验中，开始由于忽略了外部电路，浪费了不少时间；其次，在实验中要注意实际操作与理论的差别，比如实验编程中要用到的实际地址，要据计算机的实际情况来查找确定。

附：程序清单STACK SEGMENT STACKDB 100 DUP(?)STACK ENDSDA TA SEGMENTX DB 0,255Y DB 128,168,203,232,250,255,250,232,203,168,128,88,53,24,6,0,6,24,53,88DA TA ENDSCODE SEGMENTASSUME CS:CODE,DS:DA TA,SS:STACKMAIN PROCMOV AX,DATAMOV DS,AXNEXT1:MOV SI,OFFSET YMOV CX,20NEXT:MOV AL,[SI]MOV DX,0EF00H-280H+290HOUT DX,ALMOV AH,1INT 21HINC SILOOP NEXTMOV AH,6MOV DL,0FFHINT 21HJZ NEXT1MOV AH,4CHINT 21HMAIN ENDPCODE ENDSEND MAIN。

模数转换技术的应用-2013-6

设计利用NE555产生TLC0820读时序脉冲。测量电位器的输出电压，由LED显示输出结果。
2
课程内容

1 概述 2 ADC基本原理 3 ADC类型与指标 4 TLC0820 5 NE555振荡器 6 实验电路及步骤 7 实验报告要求
3
1 概述

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伴随微处理器（MCU）的发展，仪器仪表设计多以其作为核心器件，信息处理过程由硬件电路为主转变为以软件为主。
7 2
8
4 3
D8 R1 0 7 50 LED
R1
1 0K C2 1 03
6 1 5
共 8路
6.2 实验步骤

用万用表测量并记录正参考电压值。
调节电位器可以得到0到5V之间的模拟输入信号，记录模拟输入0V、1V、2V、3V、4V、5V对应的输出数据。将理论计算值与ADC输出数据对比，计算误差。

对ADC/DAC要求
ቤተ መጻሕፍቲ ባይዱ
精
度：保证处理结果的准确性。
转换速度：保证快速检测过程的可靠。

一些MCU内部集成了增益可编程放大器和多通道甚至高精度的模数转换器。
2 ADC基本原理

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AD转换过程

技术特征：时间上：输入模拟信号连续，输出数字信号离散；转换过程：在一系列选定的瞬间实现。
2.1 采样

离散采样要求：为保证能够从采样信号中恢复出原始信号，需要满足奈奎斯特采样定律： f s 2 fi (max)
工程上：一般时间上均匀离散采样，且 f s (3 ~ 5) fi (max)

2.2 采样保持

采样保持电路工作原理：