南京工程学院EDA所有实验报告(包含程序以及波形图)潘清明

电子设计自动化EDA技术实验K数控121
一位全加器源程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY QJQ IS
PORT(A,B,CIN:IN STD_LOGIC;
SUM,CO:OUT STD_LOGIC);
END QJQ;
ARCHITECTURE ART1 OF QJQ IS
BEGIN
PROCESS(A,B,CIN)
BEGIN
IF(A='0'AND B='0'AND CIN='0')THEN
SUM<='0';
CO<='0';
ELSIF(A='1'AND B='0'AND CIN='0')THEN
SUM<='1';
CO<='0';
ELSIF(A='0'AND B='1'AND CIN='0')THEN
SUM<='1';
CO<='0';
ELSIF(A='1'AND B='1'AND CIN='0')THEN
SUM<='0';
CO<='1';
ELSIF(A='0'AND B='0'AND CIN='1')THEN
SUM<='1';
CO<='0';
ELSIF(A='1'AND B='0'AND CIN='1')THEN
SUM<='0';
CO<='1';
ELSIF(A='0'AND B='1'AND CIN='1')THEN
SUM<='0';
CO<='1';
ELSE
SUM<='1';
CO<='1';
END IF;
END PROCESS;
END ART1;
一位全加器
4位全加器
电子设计自动化EDA技术实验K数控121
8线-3线优先编码器源程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY BMQ IS
PORT(IN1:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
SEL:IN STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
YS:OUT STD_LOGIC;
YEX:OUT STD_LOGIC);
END BMQ ;
ARCHITECTURE ART3 OF BMQ IS
BEGIN
PROCESS(IN1,SEL)
BEGIN
IF SEL='1' THEN Y<="111";YS<='1';YEX<='1';
ELSIF IN1="11111111"THEN Y<="111";YS<='0';YEX<='1';
ELSIF IN1(7)='0' THEN Y<="111";YS<='1';YEX<='0';
ELSIF IN1(6)='0' THEN Y<="110";YS<='1';YEX<='0';
ELSIF IN1(5)='0' THEN Y<="101";YS<='1';YEX<='0';
ELSIF IN1(4)='0' THEN Y<="100";YS<='1';YEX<='0';
ELSIF IN1(3)='0' THEN Y<="011";YS<='1';YEX<='0';
ELSIF IN1(2)='0' THEN Y<="010";YS<='1';YEX<='0';
ELSIF IN1(1)='0' THEN Y<="001";YS<='1';YEX<='0';
ELSIF IN1(0)='0' THEN Y<="000";YS<='1';YEX<='0';
ELSE NULL;
END IF;
END PROCESS;
END ART3;
8线-3线优先编码器
电子设计自动化EDA技术实验K数控121
十进制计数器源程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JSQ IS
PORT(CP,LD,UD:IN STD_LOGIC;
D:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Q:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY JSQ;
ARCHITECTURE ART OF JSQ IS
BEGIN
PROCESS(CP,D,LD)IS
BEGIN
IF(CP'EVENT AND CP='1')THEN
IF LD='1'THEN
Q<=D;
ELSIF UD='0'THEN
IF(Q=9)THEN
Q<="0000";
ELSE
Q<=Q+1;
END IF;
ELSE
IF(Q=0)THEN
Q<="1001";
ELSE
Q<=Q-1;
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE ART;
移位寄存器源程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY YWJCQ IS
PORT(CP,LD,LR:IN STD_LOGIC;
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOT:BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY YWJCQ;
ARCHITECTURE ART OF YWJCQ IS
BEGIN
PROCESS(CP,D,LD)IS
BEGIN
IF LD='1'THEN
DOT<=D;
ELSIF(CP'EVENT AND CP='1')THEN
IF LR='0'THEN
DOT<=DOT(0)&DOT(7 DOWNTO 1);
ELSE
DOT<=DOT(6 DOWNTO 0)&DOT(7);
END IF;
END IF;
END PROCESS;
END ARCHITECTURE ART;。