EDA技术与VHDL(第2版)习题解答

第3章 VHDL 基础3-1 如图所示inputoutputenablebuf3smux21in0in1outputsel3-2程序： IF_THEN 语句 LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 SPORT ( s1,s0 : IN STD_LOGIC_VECTOR ; a,b,c,d : IN STD_LOGIC ; y : OUT STD_LOGIC ) ; END ENTITY mux21 ;ARCHITECTURE one OF mux21 IS BEGINPROCESS ( s0,s1,a,b,c,d ) BEGINIF s1=‟0‟ AND s0=‟0‟ THEN y<=a ; ELSIF s1=‟0‟ AND s0=‟1‟ THEN y<=b ; ELSIF s1=‟1‟ AND s0=‟0‟ THEN y<=c ; ELSIF s1=‟1‟ AND s0=‟1‟ THEN y<=d ; ELSE y<=NULL ; END IF ;END PROCESS ; END ARCHITECTURE one ;CASE 语句LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ; ENTITY mux21 ISPORT ( s1,s0 : IN STD_LOGIC_VECTOR ;a,b,c,d : IN STD_LOGIC ;y : OUT STD_LOGIC ) ;END ENTITY mux21 ;ARCHITECTURE two OF mux21 ISSIGNAL s : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ;BEGINs<=s1 & s0 ;PROCESS ( s )BEGINCASE s ISWHEN “00” => y<=a ;WHEN “01” => y<=b ;WHEN “10” => y<=c ;WHEN “11” => y<=d ;WHEN OTHERS => NULL ;END CASE ;END PROCESS ;END ARCHITECTURE two ;3-3 程序：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY MUXK ISPORT ( s0,s1 : IN STD_LOGIC ;a1,a2,a3 : IN STD_LOGIC ;outy : OUT STD_LOGIC ) ;END ENTITY MUXK ;ARCHITECTURE double OF MUXK ISSIGNAL tmp : STD_LOGIC ; --内部连接线SIGNAL u1_s, u1_a, u1_b, u1_y : STD_LOGIC ;SIGNAL u2_s, u2_a, u2_b, u2_y : STD_LOGIC ;BEGINp_MUX21A_u1 : PROCESS ( u1_s, u1_a, u1_b, u1_y )BEGINCASE u1_s ISWHEN …0‟ => u1_y<= u1_a ;WHEN …1‟ => u1_y<= u1_b ; WHEN OTHERS => NULL ; END CASE ;END PROCESS p_ MUX21A_u1 ;p_ MUX21A_u2 : PROCESS ( u2_s, u2_a, u2_b, u2_y ) BEGINCASE u2_s ISWHEN …0‟ => u2_y<= u2_a ;WHEN …1‟ => u2_y<= u2_b ; WHEN OTHERS => NULL ; END CASE ;END PROCESS p_ MUX21A_u2 ; u1_s<= s0 ; u1_a<= a2 ; u1_b<= a3 ; tmp<= u1_y ;u2_s<=s1 ; u2_a<= a1 ; u2_b<= tmp; outy <= u2_y ;END ARCHITECTURE double ; 3-4 程序：（1）1位半减器x y 00011011被减数减数高位低位0000s_out diff 111 s_out= x · y diff= x · y + x · y(2)1位半减器的设计选用（2）图，两种表达方式：一、LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY h_suber ISPORT ( x,y : IN STD_LOGIC ;s_out ,diff : OUT STD_LOGIC ) ;END ENTITY h_suber ;ARCHITECTURE fhd1 OF h_suber ISBEGINdiff<=x XOR y ; s_out<= ( NOT a ) AND b ;END ARCHITECTURE fhd1 ;二、LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY h_suber ISPORT ( x,y : IN STD_LOGIC ;s_out ,diff : OUT STD_LOGIC ) ;END ENTITY h_suber ;ARCHITECTURE fhd1 OF h_suber ISSIGNAL s : STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ;BEGINs<= x & y ;PROCESS ( s )BEGINCASE s ISWHEN “00” => s_out <=‟0‟ ; diff<=‟0‟ ;WHEN “01” => s_out <=‟1‟ ; diff<=‟1‟ ;WHEN “10” => s_out <=‟0‟ ; diff<=‟1‟ ;WHEN “11” => s_out <=‟0‟ ; diff<=‟0‟ ;WHEN OTHERS => NULL ;END CASE ;END PROCESS ;LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY or ISPORT ( a,b : IN STD_LOGIC ;c : OUT STD_LOGIC ) ;END ENTITY or ;ARCHITECTURE one OF or ISBEGINc<= a OR b ;END ARCHITECTURE one ;1位全减器：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY f_suber ISPORT ( x,y,sub_in : IN STD_LOGIC ;sub_out ,diffr : OUT STD_LOGIC ) ;END ENTITY f_suber ;ARCHITECTURE fhd1 OF f_suber ISCOMPONENT h_suber ISPORT ( x,y : IN STD_LOGIC ;s_out ,diff : OUT STD_LOGIC ) ;END COMPONENT h_suber ;COMPONENT or ISPORT ( a,b : IN STD_LOGIC ;c : OUT STD_LOGIC ) ;END COMPONENT or ;SIGNAL d,e,f : STD_LOGIC ;BEGINu1 : h_suber PORT MAP ( x=>x, y=>y, diff=>d, s_out=>e ) ;u2 : h_suber PORT MAP ( x=>d, y=>sub_in, diff=>diffr, s_out=>f ) ;u3 : or PORT MAP ( a=>f, b=>e, c=>sub_out ) ;END ARCHITECTURE fhd1 ;（2）8位减法器：f_suber sub_in x ysub_out4f_subersub_in x ysub_out5f_subersub_in x ysub_out6f_subersub_in x ysub_out7sub_out e f gu4u5u6u7LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY 8f_suber ISPORT ( x0,x1,x2,x3,x4,x5,x6,x7 : IN STD_LOGIC ;y0,y1,y2,y3,y4,y5,y6,y7 : IN STD_LOGIC ;sub_in : IN STD_LOGIC ;sub_out : OUT STD_LOGIC ;diffr0,diffr1,diffr2,diffr3 : OUT STD_LOGIC ;diffr4,diffr5,diffr6,diffr7 : OUT STD_LOGIC ) ;END ENTITY 8f_suber ;ARCHITECTURE 8fhd1 OF 8f_suber ISCOMPONENT f_suber ISPORT ( x,y,sub_in : IN STD_LOGIC ;sub_out ,diffr : OUT STD_LOGIC ) ;END COMPONENT f_suber ;SIGNAL a,b,c,d,e,f,g : STD_LOGIC ;BEGINu0 : f_suber PORT MAP ( x=>x0, y=>y0, sub_in=>, sub_out=>a, diff=>diff0 ) ;u1 : f_suber PORT MAP ( x=>x1, y=>y1, sub_in=>a, sub_out=>b, diff=>diff1 ) ;u2 : f_suber PORT MAP (x=>x2, y=>y2, sub_in=>b, sub_out=>c, diff=>diff2 ) ;u3 : f_suber PORT MAP (x=>x3, y=>y3, sub_in=>c, sub_out=>d, diff=>diff3 ) ;u4 : f_suber PORT MAP (x=>x4, y=>y4, sub_in=>d, sub_out=>e, diff=>diff4 ) ;u5 : f_suber PORT MAP (x=>x5, y=>y5, sub_in=>e, sub_out=>f, diff=>diff5 ) ;u6 : f_suber PORT MAP (x=>x6, y=>y6, sub_in=>f, sub_out=>g, diff=>diff6 ) ;u7 : f_suber PORT MAP (x=>x7, y=>y7, sub_in=>g, sub_out=> sub_out, diff=>diff7 ) ;END ARCHITECTURE 8fhd1 ;3-5 程序：或非门逻辑描述：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY nor ISPORT ( d, e : IN STD_LOGIC ;f : OUT STD_LOGIC ) ;END ENTITY nor ;ARCHITECTURE one OF nor ISBEGINf <= NOT ( d OR e ) ;END ARCHITECTURE one ;时序电路描述：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY circuit ISPORT ( CL, CLK0 : IN STD_LOGIC ;OUT1 : OUT STD_LOGIC ) ;END ENTITY circuit ;ARCHITECTURE one OF circuit ISCOMPONENT DFF1 ISPORT ( CLK : IN STD_LOGIC ;D : IN STD_LOGIC ;Q : OUT STD_LOGIC ) ;END COMPONENT DFF1 ;COMPONENT nor ISPORT ( d, e : IN STD_LOGIC ;f : OUT STD_LOGIC ) ;END COMPONENT nor ;COMPONENT not ISPORT ( g : IN STD_LOGIC ;h : OUT STD_LOGIC ) ;END COMPONENT not ;SIGNAL a, b : STD_LOGIC ;BEGINu0 : nor PORT MAP ( d=>b, e=>CL, f=>a ) ;u1 : DFF1 PORT MAP ( CLK=>CLK0, D=>a, Q=>b ) ;u2 : not PORT MAP ( g=>b, h=>OUT1 ) ;END ARCHITECTURE one ;3-6 LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY MX3256 ISPORT( INA,INB,INCK,INC: IN STD_LOGIC ;E,OUT1: OUT STD_LOGIC) ;END ENTITY MX3256;ARCHITECTURE one OF MX3256 ISCOMPONENT LK35 ISPORT ( A1,A2,CLK: IN STD_LOGIC ;O1,O2: OUT STD_LOGIC) ;END COMPONENT LK35;BEGIN3-7LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;USE IEEE.STD_LOGIC_unsigned.ALL ;ENTITY CNT ISPORT( CLK,EN,RST,opcode: IN STD_LOGIC ;CQ: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;COUT: OUT STD_LOGIC) ;END ENTITY CNT;ARCHITECTURE behav1 OF CNT ISBEGINPROCESS( RST,EN,CLK,opcode )VARIABLE CQI: STD_LOGIC_VECTOR( 15 DOWNTO 0) ;beginIF RST=‟1‟ THEN CQI:=( OTHERS=>‟0‟) ;ELSIF EN=‟1‟ THENIF CLK‟EVENT AND CLK=‟1‟ THENCASE opcode ISWHEN …0‟ =>CQI:=CQI+1;WHEN …1‟ =>CQI:=CQI-1;WHEN OTHERS =>NULL;END CASE;END IF;END IF;CASE opcode ISWHEN …0‟ => IF CQI=65535 THEN COUT<=‟1‟;ELSE COUT<=‟0‟;END IF;WHEN …1‟ => IF CQI=0 THEN COUT<=‟1‟;ELSE COUT<=‟0‟;END IF;WHEN OTHERS =>NULL;END CASE;CQ<=CQI;END PROCESS;END behav1;3-83-93-103-113-123-133-14程序1：SIGNAL A,EN : STD_LOGIC ;PROCESS ( A, EN )VARIABLE B : STD_LOGIC ;BEGINIF EN = …1‟THEN B := A ;END IF ;END PROCESS ;程序2：ARCHITECTURE one OF sample ISBEGINPROCESS ( )VARIABLE a,b,c : integer range…;BEGINc := a+b ;END PROCESS;END ARCHITECTURE one ;程序3：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY mux21 ISPORT ( a,b : IN STD_LOGIC ;sel : IN STD_LOGIC ;c : OUT STD_LOGIC ) ;END ENTITY mux21 ;ARCHITECTURE one OF mux21 ISBEGINPROCESS ( )BEGINIF sel = …0‟THEN c<=a ;ELSE c<=b ;END IF ;END PROCESS;END ARCHITECTURE one ;第4章Quartus II使用方法习题4-1第5章VHDL状态机习题5-1 例5-4（两个进程）：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY MOORE1 ISPORT ( DATAIN : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ;CLK,RST : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ) ;END ENTITY MOORE1 ;ARCHITECTURE behav OF MOORE1 ISTYPE ST_TYPE IS ( ST0,ST1,ST2,ST3,ST4 ) ;SIGNAL C_ST ,N_ST : ST_TYPE ;BEGINREG : PROCESS ( RST ,CLK )BEGINIF RST=‟1‟THEN C_ST<=ST0; Q<=”0000”;ELSIF CLK ‟EVENT AND CLK=‟1‟THENC_ST<=N_ST ;END IF ;END PROCESS ;COM : PROCESS (C_ST , DATAIN)BEGINCASE C_ST ISWHEN ST0 =>IF DATAIN = “10”THEN N_ST <= ST1 ;ELSE N_ST <= ST0 ;END IF ;Q <=”1001” ;WHEN ST1 =>IF DATAIN = “11”THEN N_ST <= ST2 ;ELSE N_ST <= ST1 ;END IF ;Q <=” 0101” ;WHEN ST2 =>IF DATAIN = “01”THEN N_ST <= ST3 ;ELSE N_ST <= ST0 ;END IF ;Q <=” 1100” ;WHEN ST3 =>IF DATAIN = “00”THEN N_ST <= ST4 ;ELSE N_ST <= ST2 ;END IF ;Q <=” 0010” ;WHEN ST4 =>IF DATAIN = “11”THEN N_ST <= ST0 ;ELSE N_ST <= ST3 ;END IF ;Q <=” 1001” ;WHEN OTHERS => N_ST <= ST0 ;END CASE ;END PROCESS ;END ARCHITECTURE behav ;5-2 例5-5（单进程）：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY MEALY1 ISPORT ( CLK, DATAIN ,RESET : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0 ) ) ;END ENTITY MEALY1 ;ARCHITECTURE behav OF MEALY1 ISTYPE states IS ( st0,st1,st2,st3,st4 ) ;SIGNAL STX : states ;BEGINPROCESS ( CLK, RESET )BEGINIF RESET = …1‟THEN STX<= st0 ;ELSIF CLK‟ EVENT AND CLK = …1‟THENCASE STX ISWHEN st0 =>IF DATAIN = …1‟THEN STX<= st1; Q<=”10000” ;ELSE Q<=”01010” ;END IF ;WHEN st1 =>IF DATAIN = …0‟THEN STX<= st2; Q<=”10111” ;ELSE Q<=” 10100” ;END IF ;WHEN st2 =>IF DATAIN = …1‟THEN STX<= st3; Q<=”10101” ;ELSE Q<=” 10011” ;END IF ;WHEN st3 =>IF DATAIN = …0‟THEN STX<= st4; Q<=”11011” ;ELSE Q<=” 01001” ;END IF ;WHEN st4 =>IF DATAIN = …1‟THEN STX<= st0; Q<=”11101” ;ELSE Q<=” 01101” ;END IF ;WHEN OTHERS => STX<=st0; Q<=”00000” ;END CASE ;END PROCESS ;END ARCHITECTURE behav ;5-3 序列检测器：要求1：要求2：要求3：5-45-5第6章16位CISC CPU设计习题6-16-26-36-46-56-66-76-8第7章VHDL语句习题7-17-27-37-4 因为每条并行赋值语句在结构体中是同时执行的，所以每条并行赋值语句都相当于一条缩写的进程语句，这条语句的所有输入信号都被隐性地列入此缩写进程的敏感信号表中。