三星DDR2内存SPD芯片说明
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M470T5663QZ3-CE7/CF7/CE6/CD5/CCC
Organization:256M x 64
Composition:128M x 8 * 16ea
Used component part #:K4T1G084QQ-HCE7/F7/E6/D5/CC
# of rows in module:2 Row
# of banks in component:8 banks
Feature:30mm height & double sided component
Refresh:8K/64ms
Bin Sort:E7(DDR2-800@CL=5), F7(DDR2-800@CL=6), E6(DDR2-667@CL=5), D5(DDR2-533@CL=4), CC(DDR2-400@CL=3)
AUG. 2007
Note :1.This will typically be programmed as 128 Bytes.
2.This will typically be programmed as 256 Bytes.
3.From Datasheet
4.High order bit is Self Refresh "flag". If set to "1", the assembly supports self refresh.
5.These bytes are programmed by code of Date Year & Date Week with BCD format
6.These bytes are Undefined and can be used for Samsung's own purpose
AUG. 2007