静态时序分析基本原理和时序分析模型

Designer must enter timing requirements & exceptions
−
Used to guide fitter during placement & routing − Used to compare against actual results
PRE
PRE Q D Q
Setup Slack = Data Required Time – Data Arrival Time
Positive slack − Timing requirement met Negative slack − Timing requirement not met
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 13
Tsu Latch Edge
CLK Data must be valid here REG2.CLK REG2.D
Tclk2
Tsu
Data Valid
Data Required Time = Clock Arrival Time - Tsu - Setup Uncertainty
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 10
Setup Slack
The margin by which the setup timing requirement is met. It ensures launched data arrives in time to meet the latching requirement.
REG1
PRE
Data Required Time - Setup
The minimum time required for the data to get latched into the destination register
REG1
PRE
REG2
D
Q
Comb. Logic
PRE
D
Q
CLR
CLR
Tclk2
Together, the setup time and hold time form a Data Required Window, the time around a clock edge in which data must be stable.
Hold:
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 7
DATA
D PRE Q
CLK
Tsu Th
DATA Valid
CLK
CLR
Setup:
The minimum time data signal must be stable BEFORE clock edge The minimum time data signal must be stable AFTER clock edge
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 4
Path & Analysis Types
Tclk1 Tco
Data Valid
Tdata
REG2.D Data Valid
Data Arrival Time = launch edge + Tclk1 + Tco +Tdata
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 8
Launch & Latch Edges
Launch Edge
CLK DATA Data Valid
Latch Edge
Launch Edge: Latch Edge:
the edge which “launches” the data from source register the edge which “latches” the data at destination register (with respect to the launch edge, selected by timing analyzer; typically 1 cycle)
IN CLK CLR
D
OUT
CLR
CLR
combinational delays
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 3
Timing Analysis Basics
Launch vs. latch edges Setup & hold times Data & clock arrival time Data required time Setup & hold slack analysis I/O analysis Recovery & removal Timing models
Data Required Time - Hold
The minimum time required for the data to get latched into the destination register
REG1
PRE
REG2
D
Q
Comb. Logic
PRE
Dቤተ መጻሕፍቲ ባይዱ
Q
CLR
CLR
Tclk2
Th Latch Edge
Quartus® II Software Design Series: Timing Analysis
- Timing analysis basics
© 2009 Altera Corporation 1
Objectives
Display a complete understanding of timing analysis
Clock Arrival Time
The time for clock to arrive at destination register’s clock input
REG1
PRE
REG2
D
Q
Comb. Logic
PRE
D
Q
CLR
CLR
Tclk2 Latch Edge CLK
Tclk2
REG2.CLK
Every device path in design must be analyzed with respect to timing specifications/requirements
−
Catch timing-related errors faster and easier than gate-level simulation & board testing
Tdata
Comb. Logic
REG2
PRE
D
Q
D
Q
Tclk1
CLR
CLR
TCO Launch Edge CLK REG1.CLK REG1.Q
Tclk2
Tsu Latch Edge
Tclk1 Tco
Data Valid
Tdata
REG2.D Data Valid
Tclk2
REG2.CLK
© 2009 Altera Corporation
Hold Slack
The margin by which the hold timing requirement is met. It ensures latch data is not corrupted by data from another launch edge.
REG1
Async Path
PRE D Q
Data Path
D
PRE Q
CLR
CLR
Clock Paths Async Path
Three types of Paths: 1. Clock Paths 2. Data Path 3. Asynchronous Paths* Two types of Analysis: 1. Synchronous – clock & data paths 2. Asynchronous* – clock & async paths
© 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 2