FPGA定时器24s倒计时.doc

设计一个用于篮球比赛的定时器。要求：

（1）定时时间为 24 秒，按递减方式计时，每隔 1 秒，定时器减1；

（2）定时器的时间用两位数码管显示；

（3）设置两个外部控制开关，开关 K1 控制定时器的直接复位 / 启动计时，开关 K2 控制定时器的暂停 / 连续计时；当定时器递减计时到零（即定时时间到）时，定时器保持零不变，同

时发出报警信号，报警信号用一个发光二极管指示。

（4）输入时钟脉冲的频率为 1kHz。

（5）用 Verilog HDL语言设计，用Modelsim 软件做功能仿真，用Quartus II 综合。（6）将设计代码和仿真代码写在作业本上。

module gcount(out,sel,clock_1k,clear,pause,gcon);

input clock_1k,clear,pause;

output [6:0] out;

output sel,gcon;

reg [6:0] out;

reg sel,gcon;

reg [3:0] cnt_sl,cnt_sh,count;

reg wire [9:0] fenpin;

clock_1 = fenpin[9]; // 1Hz;

always @(posedge clock_1k or negedge clear)

begin

if (!clear)

fenpin <= 10'b0;

else

fenpin <= fenpin + 1;

end

//cnt_sl

always@(posedge clock_1 or negedge clear)

//always@(posedge clock_1 or negedge clear or posedge pause) begin

if(!clear)

cnt_sl<=4'h4;

else if (!pause)

cnt_sl<=cnt_sl;

else if (cnt_sh == 0 && cnt_sl == 0)

cnt_sl<=4'h0;

else if (cnt_sl == 0)

cnt_sl<=4'h9;

else

cnt_sl<=cnt_sl-1;

end

//cnt_sh

always@(posedge clock_1 or negedge clear)

//always@(posedge clock_1 or negedge clear or posedge pause) begin

if(!clear)

cnt_sh<=4'h2;

else if (!pause)

cnt_sh <= cnt_sh;

else if (cnt_sh == 0 && cnt_sl == 0)

cnt_sh<=4'h0;

else if (cnt_sl == 0)

cnt_sh<=cnt_sh-1;

else

cnt_sh <= cnt_sh;

end

//gcon

//always@(posedge clock_1 or negedge clear)

always@(cnt_sh or cnt_sl)

begin

if (cnt_sh == 0 && cnt_sl == 0)

gcon<=1;

else

gcon <= 0;

end

//reg

always@(posedge clock_1k or negedge clear)

begin

if(!clear)

sel<=0;

else

sel <= ~sel;

end

always @(sel)

count = (sel == 0)?cnt_sh:cnt_sl;

always @(count)

begin

case(count)

4'b0000: out=7'b011_1111;

4'b0001: out=7'b000_0110;

4'b0010: out=7'b101_1011;

4'b0011: out=7'b100_1111;

4'b0100: out=7'b110_0110;

4'b0101: out=7'b110_1101;

4'b0110: out=7'b111_1101;

4'b0111: out=7'b000_0111;

4'b1000: out=7'b111_1111;

4'b1001: out=7'b110_1111;

default: out=7'b000_0000;

endcase

end

endmodule

`timescale 1ns/1ns

`include"./gcount.v"

module test;

reg Clock_1k,Clear,Pause;

wire [6:0] Out;

wire Sel,Gcon;

initial

begin

Clock_1k<=0;

Clear<=1;

Pause<=1;

#100 Clear<=0;

#100 Clear<=1;

#5000 Pause<=0;

#5000 Pause<=1;

#5000 Clear<=0;

#5000 Clear<=1;

end

always #1 Clock_1k<=~Clock_1k;

gcount

m(.out(Out),.sel(Sel),.clock_1k(Clock_1k),.clear(Clear),.pause(Pause),.gcon(Gco n));

endmodule