cs42l52中文数据手册
Skyworks Solutions Si552 Dual-Frequency VCXO数据手册说明
999900999789989D UAL F REQUENCY V OLTAGE -C ONTROLLED C RYSTAL O SCILLATOR (VCXO) 10MH Z TO 1.4GH ZFeaturesApplicationsDescriptionThe Si552 dual-frequency VCXO utilizes Skyworks Solutions’ advanced DSPLL ® circuitry to provide a very low jitter clock for all output frequencies.The Si552 is available with any-rate output frequency from 10 to 945MHz and selected frequencies to 1400MHz. Unlike traditional VCXOs, where a different crystal is required for each output frequency, the Si552 uses one fixed crystal frequency to provide a wide range of output frequencies. This IC-based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments typically found in communication systems. The Si552 IC-based VCXO is factory-configurable for a wide variety of user specifications including frequency, supply voltage, output format, tuning slope, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating the long lead times associated with custom oscillators.Functional Block Diagram⏹Available with any-rate outputfrequencies from 10–945MHz and selected frequencies to 1.4GHz ⏹Two selectable output frequencies⏹3rd generation DSPLL ® with superiorjitter performance⏹3x better frequency stability thanSAW-based oscillators⏹Internal fixed crystal frequency ensures high reliability and low aging⏹Available CMOS, LVPECL, LVDS, and CML outputs⏹ 3.3, 2.5, and 1.8V supply options ⏹Industry-standard 5x 7mm package and pinout⏹Pb-free/RoHS-compliant⏹SONET/SDH ⏹xDSL⏹10GbE LAN/WAN⏹Low-jitter clock generation ⏹Optical modules⏹Clock and data recoveryCOrdering Information:See page 10.Si5602Si552R EVISION DSi5522SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•1. Electrical SpecificationsTable 1. Recommended Operating ConditionsParameterSymbol Test Condition Min Typ Max Units Supply Voltage 1V DD3.3V option 2.97 3.3 3.63V 2.5V option 2.25 2.5 2.75V 1.8V option1.71 1.8 1.89VSupply CurrentI DDOutput enabledLVPECL CML LVDS CMOS ————120108999013011710898mATristate mode—6075mA Frequency Select (FS)2V IH 0.75x V DD——V V IL——0.5V Operating Temperature RangeT A–40—85ºCNotes:1.Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 10 for further details.2. FS pin includes a 17 k Ω resistor to VDD.Table 2. V C Control Voltage InputParameterSymbol Test Condition Min Typ Max Units Control Voltage Tuning Slope 1,2,3K V10 to 90% of V DD—334590135180356—ppm/VControl Voltage Linearity 4L VC BSL –5±1+5%Incremental–10±5+10%Modulation Bandwidth BW 9.310.010.7kHz V C Input Impedance Z VC 500——k ΩNominal Control Voltage V CNOM @ f O—V DD /2—V Control Voltage Tuning RangeV CV DDVNotes:1.Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 10.2. For best jitter and phase noise performance, always choose the smallest K V that meets the application’s minimum APRrequirements. See “AN266: VCXO Tuning Slope (K V ), Stability, and Absolute Pull Range (APR)” for more information.3. K V variation is ±10% of typical values.4. BSL determined from deviation from best straight line fit with V C ranging from 10 to 90% of V DD . Incremental slopedetermined with V C ranging from 10 to 90% of V DD .Si552SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•3Table 3. CLK± Output Frequency CharacteristicsParameterSymbol Test Condition Min Typ Max Units Nominal Frequency 1,2,3f OLVDS/CML/LVPECL10—945MHz CMOS 10—160MHz Temperature Stability 1,4T A =–40 to +85°C–20–50–100———+20+50+100ppm Absolute Pull Range 1,4APR±12—±375ppm AgingFrequency drift over first year.——±3ppm Frequency drift over 15 year life.——±10ppm Power up Time 5t OSC——10ms Settling Time After FS Changet FRQ——10msNotes:1.See Section 3. "Ordering Information" on page 10 for further details.2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.3. Nominal output frequency set by V CNOM =V DD /2.4. Selectable parameter specified by part number.5. Time from power up or tristate mode to f O (to within ±1ppm of f O ).Table 4. CLK± Output Levels and SymmetryParameter Symbol Test ConditionMin Typ Max Units LVPECL Output Option 1V O mid-level V DD – 1.42—V DD – 1.25V V OD swing (diff) 1.1— 1.9V PP V SEswing (single-ended)0.55—0.95V PP LVDS Output Option 2V O mid-level 1.125 1.20 1.275V V ODswing (diff)0.50.70.9V PPCML Output Option 2V O 2.5/3.3V option mid-level —V DD – 1.30—V 1.8V option mid-level —V DD – 0.36—V V OD2.5/3.3V option swing (diff) 1.10 1.50 1.90V PP 1.8V option swing (diff)0.350.4250.50V PP CMOS Output Option 3V OH I OH =32mA 0.8x V DD—V DDV V OL I OL =32mA——0.4VRise/Fall time (20/80%)t R, t FLVPECL/LVDS/CML ——350ps CMOS with C L =15pF —1—ns Symmetry (duty cycle)SYMLVPECL:V DD – 1.3V (diff)LVDS: 1.25V (diff)CMOS:V DD /245—55%Notes:1.50 Ω to V DD –2.0 V.2. R term = 100 Ω (differential).3. C L = 15 pFSi5524SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•Table 5. CLK± Output Phase JitterParameterSymbolTest ConditionMin Typ Max Units Phase Jitter (RMS)1,2,3 for F OUT > 500 MHzJKv =33ppm/V12kHz to 20MHz (OC-48) 50kHz to 80MHz (OC-192)——0.260.26——psKv =45ppm/V12kHz to 20MHz (OC-48) 50kHz to 80MHz (OC-192)——0.270.26——psKv =90ppm/V12kHz to 20MHz (OC-48) 50kHz to 80MHz (OC-192)——0.320.26——psKv =135 ppm/V12kHz to 20MHz (OC-48) 50kHz to 80MHz (OC-192)——0.400.27——psKv =180 ppm/V12kHz to 20MHz (OC-48) 50kHz to 80MHz (OC-192)——0.490.28——psKv =356ppm/V12kHz to 20MHz (OC-48) 50kHz to 80MHz (OC-192)——0.870.33——psNotes:1.Refer to AN255, AN256, and AN266 for further information.2. For best jitter and phase noise performance, always choose the smallest K V that meets the application’s minimum APRrequirements. See “AN266: VCXO Tuning Slope (K V ), Stability, and Absolute Pull Range (APR)” for more information.3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supplyrejection (PSR) advantage of Si55x versus SAW-based solutions.4. Max jitter for LVPECL output with V C =1.65V, V DD =3.3V, 155.52 MHz.5. Max offset frequencies: 80MHz for F OUT > 250MHz, 20MHz for 50MHz < F OUT <250MHz,2MHz for 10MHz < F OUT <50MHz.Si552SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•5Phase Jitter (RMS)1,2,3,4,5for F OUT of 125 to 500MHzJKv =33ppm/V12kHz to 20MHz (OC-48) 50kHz to 80MHz (OC-192)——0.370.33——psKv =45ppm/V12kHz to 20MHz (OC-48) 50kHz to 80MHz (OC-192)——0.370.330.4—psKv =90ppm/V12kHz to 20MHz (OC-48) 50kHz to 80MHz (OC-192)——0.430.34——psKv =135 ppm/V12kHz to 20MHz (OC-48) 50kHz to 80MHz (OC-192)——0.500.34——psKv =180 ppm/V12kHz to 20MHz (OC-48) 50kHz to 80MHz (OC-192)——0.590.35——psKv =356ppm/V12kHz to 20MHz (OC-48) 50kHz to 80MHz (OC-192)——1.000.39——psTable 5. CLK± Output Phase Jitter (Continued)ParameterSymbolTest ConditionMin Typ Max Units Notes:1.Refer to AN255, AN256, and AN266 for further information.2. For best jitter and phase noise performance, always choose the smallest K V that meets the application’s minimum APRrequirements. See “AN266: VCXO Tuning Slope (K V ), Stability, and Absolute Pull Range (APR)” for more information.3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supplyrejection (PSR) advantage of Si55x versus SAW-based solutions.4. Max jitter for LVPECL output with V C =1.65V, V DD =3.3V, 155.52 MHz.5. Max offset frequencies: 80MHz for F OUT > 250MHz, 20MHz for 50MHz < F OUT <250MHz,2MHz for 10MHz < F OUT <50MHz.Si5526SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•Phase Jitter (RMS)1,2,5for F OUT 10 to 160MHz CMOS Output OnlyJKv =33ppm/V12kHz to 20MHz (OC-48)50kHz to 20MHz ——0.630.62——psKv =45ppm/V12kHz to 20MHz (OC-48)50kHz to 20MHz ——0.630.62——psKv =90ppm/V12kHz to 20MHz (OC-48)50kHz to 20MHz ——0.670.66——psKv =135 ppm/V12kHz to 20MHz (OC-48) 50kHz to 20MHz ——0.740.72——psKv =180 ppm/V12kHz to 20MHz (OC-48)50kHz to 20MHz ——0.830.8——psKv =356ppm/V12kHz to 20MHz (OC-48)50kHz to 20MHz——1.261.2——psTable 6. CLK± Output Period JitterParameterSymbol Test ConditionMin Typ Max Units Period Jitter*J PERRMS —2—ps Peak-to-Peak—14—ps*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N =1000 cycles. Refer to AN279 for further information.Table 5. CLK± Output Phase Jitter (Continued)ParameterSymbolTest ConditionMin Typ Max Units Notes:1.Refer to AN255, AN256, and AN266 for further information.2. For best jitter and phase noise performance, always choose the smallest K V that meets the application’s minimum APRrequirements. See “AN266: VCXO Tuning Slope (K V ), Stability, and Absolute Pull Range (APR)” for more information.3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supplyrejection (PSR) advantage of Si55x versus SAW-based solutions.4. Max jitter for LVPECL output with V C =1.65V, V DD =3.3V, 155.52 MHz.5. Max offset frequencies: 80MHz for F OUT > 250MHz, 20MHz for 50MHz < F OUT <250MHz,2MHz for 10MHz < F OUT <50MHz.Si552SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•7Table 7. CLK± Output Phase Noise (Typical)Offset Frequency74.25MHz 90ppm/V LVPECL491.52MHz 45ppm/V LVPECL 622.08MHz 135ppm/V LVPECL Units100Hz 1kHz 10kHz 100kHz 1MHz 10MHz 100MHz–87–114–132–142–148–150n/a–75–100–116–124–135–146–147–65–90–109–121–134–146–147dBc/HzTable 8. Environmental ComplianceThe Si552 meets the following qualification test requirements.ParameterConditions/Test Method Mechanical Shock MIL-STD-883F, Method 2002.3 B Mechanical Vibration MIL-STD-883F, Method 2007.3 A Solderability MIL-STD-883F, Method 203.8Gross & Fine Leak MIL-STD-883F, Method 1014.7Resistance to Solvents MIL-STD-883F, Method 2016Moisture Sensitivity Level J-STD-020, MSL 1Contact PadsJ-STD-020, MSL 1Table 9. Thermal Characteristics(Typical values TA =25ºC, V DD =3.3V)ParameterSymbol Test ConditionMin Typ Max Unit Thermal Resistance Junction to Ambient θJA Still Air —84.6—°C/W Thermal Resistance Junction to Case θJC Still Air—38.8—°C/W Ambient Temperature T A –40—85°C Junction TemperatureT J——125°CSi552Table 10. Absolute Maximum Ratings1Parameter Symbol Rating Units Maximum Operating Temperature T AMAX85ºC Supply Voltage, 1.8V Option V DD–0.5 to +1.9V Supply Voltage, 2.5/3.3V Option V DD–0.5 to +3.8VInput Voltage (any input pin)V I–0.5 to V DD +0.3V Storage Temperature T S–55 to +125ºCESD Sensitivity (HBM, per JESD22-A114)ESD2500V Soldering Temperature (Pb-free profile)2T PEAK260ºC Soldering Temperature Time @ T PEAK (Pb-free profile)2t P20–40seconds Notes:1.Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functionaloperation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability.2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available athttps:///Product_Certificate.aspx for further information, including soldering profiles.8SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•Si552SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•92. Pin DescriptionsTable 11. Si552 Pin DescriptionsPin Name Type Function1V C Analog InputControl Voltage2FS*Input Frequency Select:0=first frequency selected 1=second frequency selected 3GND Ground Electrical and Case Ground 4CLK+Output Oscillator Output 5CLK–(N/A for CMOS)Output Complementary Output (N/C for CMOS)6V DDPowerPower Supply Voltage*Note: FS includes a 17k pullup resistor to V DD . See Section 3. "Ordering Information" on page 10 for details on frequencyselect and OE polarity ordering options.V CG NDFS V DDCLK+CLK–(Top View)Si5523. Ordering InformationThe Si552 supports a variety of options including frequency, temperature stability, tuning slope, output format, and V DD. Specific device configurations are programmed into the Si552 at time of shipment. Configurations are speci-fied using the Part Number Configuration chart shown below. Skyworks Solutions provides a web browser-based part number configuration utility to simplify this process. Refer to https:///en/Products/Timing to access this tool and for further ordering instructions. The Si552 VCXO series is supplied in an industry-standard, RoHS-compliant, lead-free, 6-pad, 5x7mm package. Tape and reel packaging is an ordering option.Example Part Number: 552AF000108DGR is a 5x7mm Dual VCXO in a 6 pad package. Since the six digit code (000108) is >000100, f0 is 644.53125 MHz (lower frequency) and f1 is 693.48299 (higher frequency), with a 3.3V supply and LVPECL output.Temperature stability is specified as ±50 ppm and the tuning slope is 135 ppm/V. The part is specified for a -40 to +85 C° ambienttemperature range operation and is shipped in tape and reel format.Figure1.Part Number Convention10SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•Si552SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************• 114. Package Outline and Suggested Pad LayoutFigure 2 illustrates the package details for the Si552. Table 12 lists the values for the dimensions shown in the illustration.Figure 2.Si552 Outline DiagramTable 12. Package Diagram Dimensions (mm)DimensionMin Nom Max A 1.50 1.65 1.80b 1.30 1.40 1.50c 0.500.600.70D 5.00 BSC D1 4.304.40 4.50e 2.54 BSC.E 7.00 BSC.E1 6.10 6.20 6.30H 0.550.650.75L 1.17 1.27 1.37p 1.80— 2.60R 0.70 REF aaa 0.15bbb 0.15ccc 0.10ddd 0.10eee0.50Si55212SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•5. 6-Pin PCB Land PatternFigure 3 illustrates the 6-pin PCB land pattern for the Si552. Table 13 lists the values for the dimensions shown in the illustration.Figure 3.Si552 PCB Land Pattern Table 13. PCB Land Pattern Dimensions (mm)DimensionMinMaxD2 5.08 REF e 2.54 BSC E2 4.15 REFGD 0.84—GE 2.00—VD 8.20 REF VE 7.30 REFX 1.70 TYP Y 2.15 REFZD — 6.78ZE—6.30Notes:1.Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.2. Land pattern design based on IPC-7351 guidelines.3. All dimensions shown are at maximum material condition (MMC).4.Controlling dimension is in millimeters (mm).Si552SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************• 136. Top Marking6.1. Si552 Top Marking6.2. Top Marking ExplanationLine Position Description1 1–10Part Family Number, 552 (First3 characters in part number) 2 1–10Si552: Option1+Option2+Freq(7)+TempSi552 w/ 8-digit resolution: Option1+Option2+ConfigNum(6)+Temp3Trace Code Position 1Pin 1 orientation mark (dot)Position 2Product Revision (D)Position 3–6Tiny Trace Code (4 alphanumeric characters per assembly release instructions)Position 7Year (least significant year digit), to be assigned by assembly site (ex: 2007=7)Position 8–9Calendar Work Week number (1–53), to be assigned by assembly site Position 10“+” to indicate Pb-Free and RoHS-compliantSi55214SkyworksSolutions,Inc.•Phone[781]376-3000•Fax[781]376-3100•*********************•D OCUMENT C HANGE L ISTRevision 0.6 to Revision 1.0⏹Updated Table 4 on page 3.● Updated 2.5V/3.3V and 1.8V CML output levelspecifications.⏹Updated Table 5 on page 4.● Removed the words “Differential Modes:LVPECL/LVDS/CML” in the footnote referring to AN256.● Added footnotes clarifying max offset frequency test conditions.● Added CMOS phase jitter specs.⏹Updated Table 10 on page 8.● Separated 1.8V, 2.5V/3.3V supply voltagespecifications.⏹Updated and clarified Table 8 on page 7● Added “Moisture Sensitivity Level” and “Contact Pads”rows.⏹Updated 6. "Top Marking" on page 13 to reflect specific marking information (previously, figure was generic).⏹Updated 4. "Package Outline and Suggested Pad Layout" on page 11.● Added cyrstal impedance pin in Figure2 on page 11 andTable 12 on page 11.⏹Reordered spec tables and back matter to conform to data sheet quality conventions.Revision 1.0 to Revision 1.1⏹Added Table 9, “Thermal Characteristics,” on page 7.Revision 1.1 to Revision 1.2June, 2018⏹Changed “Trays” to “Coil Tape” in section 3.“Ordering Information”.Copyright © 2022 Skyworks Solutions, Inc. All Rights Reserved.Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products or services. These materials, including the information contained herein, are provided by Skyworks as a service to its customers and may be used for informational purposes only by thecustomer. Skyworks assumes no responsibility for errors or omissions in these materials or the information contained herein. Skyworks may change its documentation, products, services, specifications or product descriptions at any time, without notice. Skyworks makes no commitment to update the materials or information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from any future changes.No license, whether express, implied, by estoppel or otherwise, is granted to any intellectual property rights by this document. Skyworks assumes no liability for any materials, products or information provided hereunder, including the sale, distribution, reproduction or use of Skyworks products, information or materials, except as may be provided in Skyworks’ Terms and Conditions of Sale.THE MATERIALS, PRODUCTS AND INFORMATION ARE PROVIDED “AS IS” WITHOUT WARRANTY OF ANY KIND, WHETHER EXPRESS, IMPLIED,STATUTORY, OR OTHERWISE, INCLUDING FITNESS FOR A PARTICULAR PURPOSE OR USE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT; ALL SUCH WARRANTIES ARE HEREBY EXPRESSL Y DISCLAIMED. SKYWORKS DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO ANY SPECIAL, INDIRECT, INCIDENTAL, STATUTORY, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESUL T FROM THE USE OF THE MATERIALS OR INFORMATION, WHETHER OR NOT THE RECIPIENT OF MATERIALS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE Skyworks products are not intended for use in medical, lifesaving or life-sustaining applications, or other equipment in which the failure of the Skyworks products could lead to personal injury, death, physical or environmental damage. Skyworks customers using or selling Skyworks products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale.Customers are responsible for their products and applications using Skyworks products, which may deviate from published specifications as a result of design defects, errors, or operation of products outside of published parameters or design specifications. Customers should include design and operating safeguards to minimize these and other risks. Skyworks assumes no liability for applications assistance, customer product design, or damage to any equipment resulting from the use of Skyworks products outside of Skyworks’ published specifications or parameters.Skyworks, the Skyworks symbol, Sky5®, SkyOne®, SkyBlue™, Skyworks Green™, Clockbuilder®, DSPLL®, ISOmodem®, ProSLIC®, and SiPHY® are trademarks or registered trademarks of Skyworks Solutions, Inc. or its subsidiaries in the United States and other countries. Third-party brands and names are for identification purposes only and are the property of their respective owners. Additional information, including relevant terms and conditions, posted at , are incorporated by reference.SkyworksSolutions,Inc.|Nasdaq:SWKS|*********************|USA: 781-376-3000 | Asia: 886-2-2735 0399 | Europe: 33 (0)1 43548540Portfolio Quality/qualitySW/HW/CBProSupport & Resources/support。
UAF42中文数据手册
基于通用有源滤波器UAF42的滤波器设计尽管有源滤波器在现代电子工业中是非常重要的，但是其设计和检验却要耗费很多时间。
为了便于有源滤波器的设计，BURR-BROWN提供了一种FilterPro TM电脑辅助设计。
通过FILTER42程序和UAF42可以设计实现所有种类的有源滤波器。
UAF42是一个单片集成电路，其中包含了运算放大器、匹配电阻和状态可调双极滤波极对所需的精密电容，以及一个独立的精密四运放。
UAF42实现的滤波器是时间连续的，同时避免了开关噪声和开关电容滤波器的混叠误差。
这种状态可调拓扑结构带来的另外的好处是滤波器受外部器件的影响很小，同时，可以得到低通、高通、带通的输出。
一个UAF42外加两个电阻器就可以实现一个简单的双极滤波器，见图1。
注：UAF42和两个外接电阻构成一个单增益、1.25dB纹波的双极低通切比雪夫滤波器，根据阻值所示，截止频率为10kHz。
图1. 采用UAF42实现的双极低通滤波器设计程序与DOS系统兼容，可以自动计算出外围器件的值，实用于设计低通、高通、带通、带阻（或陷波）滤波器。
有源滤波器被设计成近似理想的滤波器响应。
例如：一种理想的低通滤波器完全消除了截止频率之上的信号，而低于截止频率的信号则无损通过。
而现实的滤波器为了接近理想滤波器要进行各种权衡。
一些滤波器优化了通带增益的平坦度，另一些则权衡通带增益的变化来实现通带和阻带间比较陡的衰减，还有一些是舍弃增益平坦度和陡的衰减特性来保证脉冲响应的保真度。
FILTER42支持这三种最常用的全极滤波器类型：巴特沃斯、切比雪夫和贝塞尔。
同时也支持较少应用的反切比雪夫滤波器。
如果选择了双极带通或陷波滤波器，则程序默认是谐振电路响应。
巴特沃斯（幅度最平坦）：这种滤波器通带内的幅度响应最平坦。
在设计的截止频率下衰减为-3dB，超出截止频率为每十倍频-20dB。
巴特沃斯滤波器的脉冲响应具有适度的过冲和振铃。
切比雪夫（同样的纹波幅度）：这种滤波器响应在截止频率外有比巴特沃斯更陡的衰减特性，优势体现在通带内振幅变化（纹波）的减小。
CS4525_08中文资料
Preliminary Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without notice.30W Digital Audio Amplifier with Integrated ADCDigital Amplifier FeaturesFully Integrated Power MOSFETs No Heatsink Required–Programmable Power Foldback on Thermal Warning –High Efficiency>100dB Dynamic Range <0.1% THD+N @ 1WConfigurable Outputs (10% THD+N)– 1 x 30W into 4Ω, Parallel Full-Bridge – 2 x 15W into 8Ω, Full-Bridge–2 x 7W into 4Ω, Half-Bridge + 1 x 15W into 8Ω, Full-BridgeBuilt-In Protection with Error Reporting–Overcurrent /Undervoltage /Thermal Overload Shutdown–Thermal Warning ReportingPWM Popguard ® for Half-Bridge Mode Click-free Start-upProgrammable Channel Delay for SystemNoise & Radiated Emissions ManagementADC FeaturesStereo, 24-bit, 48kHz Conversion Multi-bit Architecture95dB Dynamic Range (A-wtd) -86dB THD+NSupports 2Vrms Input with PassiveComponentsSystem FeaturesAsynchronous 2-channel Digital Serial Port 32kHz to 96kHz Input Sample Rates Operation with On-chip Oscillator Driver orApplied SYS_CLK at 18.432, 24.576 or 27.000MHzIntegrated Sample Rate Converter (SRC)–Eliminates Clock-jitter Effects–Input Sample Rate Independent Operation –Simplifies System IntegrationSpread Spectrum PWM Modulation–Reduces EMI Radiated EnergyLow Quiescent Current(Features continued on page 2)CS4525Software Mode System FeaturesDigital Audio Processing– 5 Programmable Parametric EQ Filters–Selectable High-pass Filter–Bass/Treble Tone Control–Adaptive Loudness Compensation–2-channel Mixer– 2.1 Bass Management–24dB/octave Linkwitz-Riley Crossover Filters–De-emphasis FilterSelectable Serial Audio Interface Formats –Left-justified up to 24-bit–I²S up to 24-bit–Right-justified 16-, 18-, 20-, 24-bitsDigital Serial Connection to Additional CS4525 or DACs for SubwooferDigital Interface to External Lip-sync DelayPWM Switch Rate Shifting Eliminates AM Frequency InterferenceDigital Volume Control with Soft Ramp –+24 to -103dB in 0.5dB stepsProgrammable Peak Detect and Limiter2-Channel Logic-level PWM Output–Programmable Channel Mapping–Can Drive an External PWM Amplifier, Headphone Amplifier, or Line-out Amplifier –Integrated Headphone DetectionFlexible Power Output ConfigurationsThermal Foldback for Interruption-free Power-stage Protection–Supports Internal and External Power StagesOperation from On-chip Oscillator Driver or Applied Systems ClockSupports I²C® Host Control Interface Hardware Mode System Features2-Channel Stereo Full Bridge Power Outputs Analog and Digital InputsI²S and Left-justified Serial Input FormatsThermal Foldback for Interruption-free Protection of Internal Power StageOperation from Applied Systems ClockExternal Mute Input Common ApplicationsIntegrated Digital TV’sFlat Panel TV MonitorsComputer/TV MonitorsMini/Micro Shelf SystemsDigital Powered SpeakersPortable Docking StationsComputer Desktop AudioGeneral DescriptionThe CS4525 is a stereo analog or digital input PWM high efficiency Class D amplifier audio system with an integrated stereo analog-to-digital (A/D) converter. The stereo power amplifiers can deliver up to 15W per channel into 8 Ω speakers from a small space-saving 48-pin QFN package. The PWM amplifier can achieve greater than 85% efficiency. The package is thermally enhanced for optimal heat dissipation which eliminates the need for a heatsink.The power stage outputs can be configured as two full-bridge channels for 2x15W operation, two half-bridge channels and one full-bridge channel for 2x7W+1x15W operation, or one parallel full-bridge channel for 1x30W operation. The CS4525 integrates on-chip over-current, under-voltage, and over-tempera-ture protection and error reporting as well as a thermal warning indicator and programmable foldback of the output power to allow cooling.The main digital serial port on the CS4525 can support asynchronous operation with the integrated on-chip sample rate converter (SRC) which eases system inte-gration. The SRC allows for a fixed PWM switching frequency regardless of incoming sample rate as well as optimal clocking for the A/D modulators.An on-chip oscillator driver eliminates the need for an external crystal oscillator circuit, reducing overall design cost and conserving circuit board space. The CS4525 automatically uses the on-chip oscillator driver in the absence of an applied master clock.The CS4525 is available in a 48-pin QFN package in Commercial grade (0° to +70° C). The CRD4525-Q1 4-layer, 1oz. copper and CRD4525-D1 2-layer, 1oz. cop-per customer reference designs are also available. Please refer to “Ordering Information” on page97 for complete ordering information.TABLE OF CONTENTS1. PIN DESCRIPTIONS - SOFTWARE MODE (8)2. PIN DESCRIPTIONS - HARDWARE MODE (10)2.1 Digital I/O Pin Characteristics (12)3. TYPICAL CONNECTION DIAGRAMS (13)4. TYPICAL SYSTEM CONFIGURATION DIAGRAMS (15)5. CHARACTERISTICS AND SPECIFICATIONS (18)6. APPLICATIONS (26)6.1 Software Mode (26)6.1.1 System Clocking (26)6.1.1.1 SYS_CLK Input Clock Mode (26)6.1.1.2 Crystal Oscillator Mode (27)6.1.2 Power-Up and Power-Down (28)6.1.2.1 Power-Up Sequence (28)6.1.2.2 Power-Down Sequence (28)6.1.3 Input Source Selection (29)6.1.4 Digital Sound Processing (29)6.1.4.1 Pre-Scaler (30)6.1.4.2 Digital Signal Processing High-Pass Filter (30)6.1.4.3 Channel Mixer (30)6.1.4.4 De-Emphasis (31)6.1.4.5 Tone Control (31)6.1.4.6 Parametric EQ (33)6.1.4.7 Adaptive Loudness Compensation (34)6.1.4.8 Bass Management (35)6.1.4.9 Volume and Muting Control (36)6.1.4.10 Peak Signal Limiter (37)6.1.4.11 Thermal Limiter (39)6.1.4.12 Thermal Foldback (40)6.1.4.13 2-Way Crossover & Sensitivity Control (42)6.1.5 Auxiliary Serial Output (43)6.1.6 Serial Audio Delay & Warning Input Port (44)6.1.6.1 Serial Audio Delay Interface (44)6.1.6.2 External Warning Input Port (44)6.1.7 Powered PWM Outputs (45)6.1.7.1 Output Channel Configurations (45)6.1.7.2 PWM Popguard Transient Control (45)6.1.8 Logic-Level PWM Outputs (46)6.1.8.1 Recommended PWM_SIG Power-Up Sequence for an External PWM Amplifier (47)6.1.8.2 Recommended PWM_SIG Power-Down Sequence for an External PWM Amplifier 476.1.8.3 Recommended PWM_SIG Power-Up Sequence for Headphone & Line-Out (48)6.1.8.4 Recommended PWM_SIG Power-Down Sequence for Headphone & Line-Out (48)6.1.8.5 PWM_SIG Logic-Level Output Configurations (49)6.1.9 PWM Modulator Configuration (50)6.1.9.1 PWM Channel Delay (50)6.1.9.2 PWM AM Frequency Shift (51)6.1.10 Headphone Detection & Hardware Mute Input (51)6.1.11 Interrupt Reporting (53)6.1.12 Automatic Power Stage Shut-Down (53)6.2 Hardware Mode (54)6.2.1 System Clocking (54)6.2.2 Power-Up and Power-Down (54)6.2.2.1 Power-Up Sequence (54)6.2.2.2 Power-Down Sequence (55)6.2.3 Input Source Selection (55)6.2.4 PWM Channel Delay (55)6.2.5 Digital Signal Flow (56)6.2.5.1 High-Pass Filter (56)6.2.5.2 Mute Control (56)6.2.5.3 Warning and Error Reporting (56)6.2.6 Thermal Foldback (57)6.2.7 Automatic Power Stage Shut-Down (58)6.3 PWM Modulators and Sample Rate Converters (58)6.4 Output Filters (59)6.4.1 Half-Bridge Output Filter (59)6.4.2 Full-Bridge Output Filter (Stereo or Parallel) (60)6.5 Analog Inputs (61)6.6 Serial Audio Interfaces (62)6.6.1 I²S Data Format (62)6.6.2 Left-Justified Data Format (62)6.6.3 Right-Justified Data Format (63)6.7 Integrated VD Regulator (63)6.8 I²C Control Port Description and Timing (64)7. PCB LAYOUT CONSIDERATIONS (65)7.1 Power Supply, Grounding (65)7.2 Output Filter Layout (65)7.3 QFN Thermal Pad (65)8. REGISTER QUICK REFERENCE (66)9. REGISTER DESCRIPTIONS (69)9.1 Clock Configuration (Address 01h) (69)9.1.1 SYS_CLK Output Enable (EnSysClk) (69)9.1.2 SYS_CLK Output Divider (DivSysClk) (69)9.1.3 Clock Frequency (ClkFreq[1:0]) (69)9.1.4 HP_Detect/Mute Pin Active Logic Level (HP/MutePol) (70)9.1.5 HP_Detect/Mute Pin Mode (HP/Mute) (70)9.1.6 Modulator Phase Shifting (PhaseShift) (70)9.1.7 AM Frequency Shifting (FreqShift) (70)9.2 Input Configuration (Address 02h) (71)9.2.1 Input Source Selection (ADC/SP) (71)9.2.2 ADC High-Pass Filter Enable (EnAnHPF) (71)9.2.3 Serial Port Sample Rate (SPRate[1:0]) - Read Only (71)9.2.4 Input Serial Port Digital Interface Format (DIF [2:0]) (71)9.3 AUX Port Configuration (Address 03h) (72)9.3.1 Enable Aux Serial Port (EnAuxPort) (72)9.3.2 Delay & Warning Port Configuration (DlyPortCfg[1:0]) (72)9.3.3 Aux/Delay Serial Port Digital Interface Format (AuxI²S/LJ) (72)9.3.4 Aux Serial Port Right Channel Data Select (RChDSel[1:0]) (72)9.3.5 Aux Serial Port Left Channel Data Select (LChDSel[1:0]) (73)9.4 Output Configuration (Address 04h) (73)9.4.1 Output Configuration (OutputCfg[1:0]) (73)9.4.2 PWM Signals Output Data Select (PWMDSel[1:0]) (73)9.4.3 Channel Delay Settings (OutputDly[3:0]) (73)9.5 Foldback and Ramp Configuration (Address 05h) (74)9.5.1 Select VP Level (SelectVP) (74)9.5.2 Enable Thermal Foldback (EnTherm) (74)9.5.3 Lock Foldback Adjust (LockAdj) (74)9.5.4 Foldback Attack Delay (AttackDly[1:0]) (75)9.5.5 Enable Foldback Floor (EnFloor) (75)9.5.6 Ramp Speed (RmpSpd[1:0]) (75)9.6 Mixer / Pre-Scale Configuration (Address 06h) (75)9.6.1 Pre-Scale Attenuation (PreScale[2:0]) (75)9.6.2 Right Channel Mixer (RChMix[1:0]) (76)9.6.3 Left Channel Mixer (LChMix[1:0]) (76)9.7 Tone Configuration (Address 07h) (76)9.7.1 De-Emphasis Control (DeEmph) (76)9.7.2 Adaptive Loudness Compensation Control (Loudness) (76)9.7.3 Digital Signal Processing High-Pass Filter (EnDigHPF) (77)9.7.4 Treble Corner Frequency (TrebFc[1:0]) (77)9.7.5 Bass Corner Frequency (BassFc[1:0]) (77)9.7.6 Tone Control Enable (EnToneCtrl) (77)9.8 Tone Control (Address 08h) (78)9.8.1 Treble Gain Level (Treb[3:0]) (78)9.8.2 Bass Gain Level (Bass[3:0]) (78)9.9 2.1 Bass Manager/Parametric EQ Control (Address 09h) (78)9.9.1 Freeze Controls (Freeze) (78)9.9.2 Hi-Z PWM_SIG Outputs (HiZPSig) (79)9.9.3 Bass Cross-Over Frequency (BassMgr[2:0]) (79)9.9.4 Enable Channel B Parametric EQ (EnChBPEq) (79)9.9.5 Enable Channel A Parametric EQ (EnChAPEq) (79)9.10 Volume and 2-Way Cross-Over Configuration (Address 55h) (80)9.10.1 Soft Ramp and Zero Cross Control (SZCMode[1:0]) (80)9.10.2 Enable 50% Duty Cycle for Mute Condition (Mute50/50) (80)9.10.3 Auto-Mute (AutoMute) (80)9.10.4 Enable 2-Way Crossover (En2Way) (81)9.10.5 2-Way Cross-Over Frequency (2WayFreq[2:0]) (81)9.11 Channel A & B: 2-Way Sensitivity Control (Address 56h) (81)9.11.1 Channel A and Channel B Low-Pass Sensitivity Adjust (LowPass[3:0]) (81)9.11.2 Channel A and Channel B High-Pass Sensitivity Adjust (HighPass[3:0]) (82)9.12 Master Volume Control (Address 57h) (82)9.12.1 Master Volume Control (MVol[7:0]) (82)9.13 Channel A and B Volume Control (Address 58h & 59h) (83)9.13.1 Channel X Volume Control (ChXVol[7:0]) (83)9.14 Sub Channel Volume Control (Address 5Ah) (83)9.14.1 Sub Channel Volume Control (SubVol[7:0]) (83)9.15 Mute/Invert Control (Address 5Bh) (84)9.15.1 ADC Invert Signal Polarity (InvADC) (84)9.15.2 Invert Channel PWM Signal Polarity (InvChX) (84)9.15.3 Invert Sub PWM Signal Polarity (InvSub) (84)9.15.4 ADC Channel Mute (MuteADC) (84)9.15.5 Independent Channel A & B Mute (MuteChX) (84)9.15.6 Sub Channel Mute (MuteSub) (85)9.16 Limiter Configuration 1 (Address 5Ch) (85)9.16.1 Maximum Threshold (Max[2:0]) (85)9.16.2 Minimum Threshold (Min[2:0]) (85)9.16.3 Peak Signal Limit All Channels (LimitAll) (86)9.16.4 Peak Detect and Limiter Enable (EnLimiter) (86)9.17 Limiter Configuration 2 (Address 5Dh) (87)9.17.1 Limiter Release Rate (RRate[5:0]) (87)9.18 Limiter Configuration 3 (Address 5Eh) (87)9.18.1 Enable Thermal Limiter (EnThLim) (87)9.18.2 Limiter Attack Rate (ARate[5:0]) (87)9.19.1 Automatic Power Stage Retry (AutoRetry) (88)9.19.2 Enable Over-Current Protection (EnOCProt) (88)9.19.3 Select VD Level (SelectVD) (88)9.19.4 Power Down ADC (PDnADC) (88)9.19.5 Power Down PWM Power Output X (PDnOutX) (89)9.19.6 Power Down (PDnAll) (89)9.20 Interrupt (Address 60h) (89)9.20.1 SRC Lock State Transition Interrupt (SRCLock) (90)9.20.2 ADC Overflow Interrupt (ADCOvfl) (90)9.20.3 Channel Overflow Interrupt (ChOvfl) (90)9.20.4 Amplifier Error Interrupt Bit (AmpErr) (91)9.20.5 Mask for SRC State (SRCLockM) (91)9.20.6 Mask for ADC Overflow (ADCOvflM) (91)9.20.7 Mask for Channel X and Sub Overflow (ChOvflM) (91)9.20.8 Mask for Amplifier Error (AmpErrM) (92)9.21 Interrupt Status (Address 61h) - Read Only (92)9.21.1 SRC State Transition (SRCLockSt) (92)9.21.2 ADC Overflow (ADCOvflSt) (92)9.21.3 Sub Overflow (SubOvflSt) (92)9.21.4 Channel X Overflow (ChXOvflSt) (93)9.21.5 Ramp-Up Cycle Complete (RampDone) (93)9.22 Amplifier Error Status (Address 62h) - Read Only (93)9.22.1 Over-Current Detected On Channel X (OverCurrX) (93)9.22.2 External Amplifier State (ExtAmpSt) (93)9.22.3 Under Voltage / Thermal Error State (UVTE[1:0]) (94)9.23 Device I.D. and Revision (Address 63h) - Read Only (94)9.23.1 Device Identification (DeviceID[4:0]) (94)9.23.2 Device Revision (RevID[2:0]) (94)10. PARAMETER DEFINITIONS (95)11. REFERENCES (95)12. PACKAGE DIMENSIONS (96)13. THERMAL CHARACTERISTICS (97)13.1 Thermal Flag (97)14. ORDERING INFORMATION (97)15. REVISION HISTORY (98)LIST OF FIGURESFigure 1.Typical Connection Diagram - Software Mode (13)Figure 2.Typical Connection Diagram - Hardware Mode (14)Figure 3.Typical System Configuration 1 (15)Figure 4.Typical System Configuration 2 (15)Figure 5.Typical System Configuration 3 (16)Figure 6.Typical System Configuration 4 (17)Figure 7.Serial Audio Input Port Timing (21)Figure 8.AUX Serial Port Interface Master Mode Timing (22)Figure 9.SYS_CLK Timing from Reset (23)Figure 10.PWM_SIGX Timing (23)Figure 11.Control Port Timing - I²C (24)Figure 12.Typical SYS_CLK Input Clocking Configuration (26)Figure 13.Typical Crystal Oscillator Clocking Configuration (27)Figure 14.Digital Signal Flow (29)Figure 15.De-Emphasis Filter (31)Figure 17.Peak Signal Detection & Limiting (37)Figure 18.Foldback Process (40)Figure 19.Popguard Connection Diagram (46)Figure 20.2-Channel Full-Bridge PWM Output Delay (50)Figure 21.3-Channel PWM Output Delay (50)Figure 22.Typical SYS_CLK Input Clocking Configuration (54)Figure 23.Hardware Mode PWM Output Delay (55)Figure 24.Hardware Mode Digital Signal Flow (56)Figure 25.Foldback Process (57)Figure 26.Output Filter - Half-Bridge (59)Figure 27.Output Filter - Full-Bridge (60)Figure 28.Recommended Unity Gain Input Filter (61)Figure 29.Recommended 2V RMS Input Filter (61)Figure 30.I²S Serial Audio Formats (62)Figure 31.Left-Justified Serial Audio Formats (62)Figure 32.Right-Justified Serial Audio Formats (63)Figure 33.Control Port Timing, I²C Write (64)Figure 34.Control Port Timing, I²C Read (64)LIST OF TABLESTable 1. I/O Power Rails (12)Table 2. Bass Shelving Filter Corner Frequencies (31)Table 3. Treble Shelving Filter Corner Frequencies (32)Table 4. Bass Management Cross-Over Frequencies (35)Table 5. 2-Way Cross-Over Frequencies (42)Table 6. Auxiliary Serial Port Data Output (43)Table 7. Nominal Switching Frequencies of the Auxiliary Serial Output (43)Table 8. PWM Power Output Configurations (45)Table 9. Typical Ramp Times for Various VP Voltages (46)Table 10. PWM Logic-Level Output Configurations (49)Table 11. PWM Output Switching Rates and Quantization Levels (51)Table 12. Output of PWM_SIG Outputs (52)Table 13. SYS_CLK Frequency Selection (54)Table 14. Input Source Selection (55)Table 15. Serial Audio Interface Format Selection (55)Table 16. Thermal Foldback Enable Selection (57)Table 17. PWM Output Switching Rates and Quantization Levels (58)Table 18. Low-Pass Filter Components - Half-Bridge (59)Table 19. DC-Blocking Capacitors Values - Half-Bridge (59)Table 20. Low-Pass Filter Components - Full-Bridge (60)Table 21. Power Supply Configuration and Settings (63)1.PIN DESCRIPTIONS - SOFTWARE MODEPin Name Pin #Pin DescriptionINT 1Interrupt (Output) - Indicates an interrupt condition has occurred.SCL2Serial Control Port Clock (Input) - Serial clock for the I²C control port.SDA3Serial Control Data (Input/Output) -Bi-directional data I/O for the I²C control port.LRCK4Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line.SCLK5Serial Clock (Input) - Serial bit clock for the serial audio interface.SDIN6Serial Audio Data Input (Input) - Input for two’s complement serial audio data.HP_DETECT/ MUTE 7Headphone Detect / Mute (Input) - Headphone detection or mute input signal as configured via the I²C control port.RST 8Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when this pin is driven low.VPOUT1PGNDPGNDOUT2VPVPOUT3PGNDPGNDOUT4VPVA_REGAGNFILT+VAFILTLAFILTAINAINOCREPGNPGNDRAMP_CATITOYS_CLKUX_LRCK/ADUX_SCLKUX_SDOUTLY_SDIN/EX_TWRLY_SDOUTWM_SIG1WM_SIG2GNDGNDLVD9VD Voltage Level Indicator (Input) - Identifies the voltage level attached to VD. When applying 5.0V to VD, LVD must be connected to VD. When applying 2.5V or 3.3V to VD, LVD must be DGND.DGND10Digital Ground (Input) - Ground for the internal logic and digital I/O.VD_REG11Core Logic Power (Output) - Internally generated low voltage power supply for digital logic. VD12Power (Input) - Positive power supply for the internal regulators and digital I/O.VA_REG13Analog Power (Output)- Internally generated positive power for the analog section and I/O. AGND14Analog Ground (Input) - Ground reference for the internal analog section and I/O.FILT+15Positive Voltage Reference (Output) - Positive reference voltage for the internal ADC sampling circuits.VQ16Common Mode Voltage (Output)-Filter connection for internal common mode voltage.AFILTL AFILTR 1718Antialias Filter Connection (Output) - Antialias filter connection for ADC inputs.AINL AINR 1920Analog Input (Input)-The full-scale input level is specified in the ADC Analog Characteristics specification table.OCREF21Over Current Reference Setting (Input) - Sets the reference for over current detection.PGND 22,2327,2833,3437,38Power Ground (Input) - Ground for the individual output power half-bridge devices.RAMP_CAP24Output Ramp Capacitor (Input) - Used by the PWM Popguard Transient Control to suppress the initial pop in half-bridge-configured outputs.VP 25,30,31,36High Voltage Power (Input) - High voltage power supply for the individual half-bridge devices.OUT4 OUT3 OUT2 OUT126293235PWM Output (Output) - Amplified PWM power outputs.PWM_SIG2 PWM_SIG13940Logic Level PWM Output (Output) - Logic Level PWM switching signals.DLY_SDOUT41Delay Serial Audio Data Out (Output) - Output for two’s complement serial audio data.DLY_SDIN/ EX_TWR 42Delay Serial Audio Data Input (Input) - Input for two’s complement serial audio data.External Thermal Warning (Input) - Input for an external thermal warning signal. Configurable via the I²C control port.AUX_SDOUT43Auxiliary Port Serial Audio Data Out (Output) - Output for two’s complement auxiliary port serial data.AUX_SCLK44Auxiliary Port Serial Clock (Output) - Serial clock for the auxiliary port serial interface.AUX_LRCK/ AD045Auxiliary Port Left Right Clock (Output) - Determines which channel, Left or Right, is currently active on the serial audio data line.AD0 (Input) - Sets the LSB of the I²C device address. Sensed on the release of RST.SYS_CLK46System Clock (Input/Output) -Clock source for the internal logic, processing, and modulators. This pin should be connected to through a 10kΩ to ground when unused.XTO47Crystal Oscillator Output(Output) - Crystal oscillator driver output. XTI48Crystal Oscillator Input (Input) - Crystal oscillator driver input.Thermal Pad-Thermal Pad - Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page65 for more information.2.PIN DESCRIPTIONS - HARDWARE MODEPin NamePin #Pin DescriptionCLK_FREQ0CLK_FREQ112Clock Frequency (Input) - Determines the frequency of the clock expected to be driven into the SYS_CLK pin. CLK_FREQ1 must be connected to DGND.ADC/SP 3ADC/Serial Port (Input) - Selects between the Analog to Digital Converter and the Serial Port for audio input. Selects the ADC when high or the serial port when low.LRCK 4Left Right Clock (Input ) - Determines which channel, Left or Right, is currently active on the serial audio data line.SCLK 5Serial Clock (Input ) - Serial bit clock for the serial audio interface.SDIN 6Serial Audio Data Input (Input ) - Input for two’s complement serial audio data.MUTE 7Mute (Input ) - The PWM outputs will output silence as a 50% duty cycle signal when this pin is driven low.RST8Reset (Input ) - The device enters a low power mode and all internal registers are reset to their default settings when this pin is driven low.VP OUT1PGND PGND OUT2VP VP OUT3PGND PGND OUT4VPV A _R E GA G N F I L T +V A F I L T LA F I L T A I N A I N O C R E P G N P G N DR A M P _C ALVD9VD Voltage Level Indicator (Input) - Identifies the voltage level attached to VD. When applying 5.0V to VD, LVD must be connected to VD. When applying 2.5V or 3.3V to VD, LVD must be con-nected to DGND.DGND10Digital Ground (Input) - Ground for the internal logic and I/O.VD_REG11Core Logic Power (Output) - Internally generated low voltage power supply for digital logic. VD12Digital Power (Input) - Positive power supply for the internal regulators and digital I/O.VA_REG13Analog Power (Output)- Internally generated positive power for the analog section and I/O. AGND14Analog Ground (Input) - Ground reference for the internal analog section and I/O.FILT+15Positive Voltage Reference (Output) - Positive reference voltage for the internal ADC sampling circuits.VQ16Common Mode Voltage (Output)-Filter connection for internal common mode voltage.AFILTL AFILTR 1718Antialias Filter Connection (Output) - Antialias filter connection for ADC inputs.AINL AINR 1920Analog Input (Input)-The full-scale input level is specified in the ADC Analog Characteristics specification table.OCREF21Over Current Reference Setting (Input) - Sets the reference for over current detection.PGND 22,2327,2833,3437,38Power Ground (Input) - Ground for the individual output power half-bridge devices.RAMP_CAP24Output Ramp Capacitor (Input) - This pin should be connected directly to VP in hardware mode.VP 25,30,31,36High Voltage Power (Input) - High voltage power supply for the individual half-bridge devices.OUT4 OUT3 OUT2 OUT126293235PWM Output (Output) - Amplified PWM power outputs.TSTO 3940Test Output(Output) - These pins are outputs used for the Logic Level PWM switching signals available only in software mode. They must be left unconnected for hardware mode operation.TWR 41Thermal Warning Output (Output) - Thermal warning output.ERRUVTE 42Thermal and Undervoltage Error Output (Output) - Error flag for thermal shutdown and under-voltage.ERROC 43Overcurrent Error Output(Output) - Overcurrent error flag.EN_TFB44Enable Thermal Feedback(Input) - Enables the thermal foldback feature when high.I2S/LJ45I²S/Left Justified(Input) - Selects between I²S and Left-Justified data format for the serial input port. Selects I²S when high and LJ when low.SYS_CLK46System Clock (Input/Output) -Clock source for the delta-sigma modulators.TSTO47Test Output(Output) - This pin is an output used for the crystal oscillator driver available only in software mode. It must be left unconnected for normal hardware mode operation.TSTI48Test Input (Input) - This pin is an input used for the crystal oscillator driver available only in soft-ware mode. It must be tied to digital ground for normal hardware mode operation.Thermal Pad-Thermal Pad - Thermal relief pad for optimized heat dissipation. See “QFN Thermal Pad” on page65 for more information.2.1Digital I/O Pin CharacteristicsThe logic level for each input is set by its corresponding power supply and should not exceed the maximum ratings.Power SupplyPinNumberPin Name I/O Driver ReceiverSoftware ModeVD1INT Output 2.5V-5.0V, Open Drain2SCL Input- 2.5V-5.0V, with Hysteresis3 SDA Input/Output 2.5V-5.0V, Open Drain 2.5V-5.0V, with Hysteresis7HP_DETECTMUTE InputInput--2.5V-5.0V2.5V-5.0V41DLY_SDOUT Output 2.5V-5.0V, CMOS-42DLY_SDINEX_TWR InputInput--2.5V-5.0V2.5V-5.0V43AUX_SDOUT Output 2.5V-5.0V, CMOS-44AUX_SCLK Output 2.5V-5.0V, CMOS-45AUX_LRCK Output 2.5V-5.0V, CMOS-VD_REG39PWM_SIG2Output 2.5V, CMOS-40PWM_SIG1Output 2.5V, CMOS-Hardware ModeVD1CLK_FREQ0Input- 2.5V-5.0V 2CLK_FREQ1Input- 2.5V-5.0V3ADC/SP Input- 2.5V-5.0V7MUTE Input- 2.5V-5.0V41TWR Output 2.5V-5.0V, Open Drain-42ERRUVTE Output 2.5V-5.0V, Open Drain-43ERROC Output 2.5V-5.0V, Open Drain-44EN_TFB Input- 2.5V-5.0V45I²S/LJ Input- 2.5V-5.0V All ModesVD4LRCK Input- 2.5V-5.0V 5SCLK Input- 2.5V-5.0V6SDIN Input- 2.5V-5.0V8RST Input- 2.5V-5.0V9LVD Input- 2.5V-5.0V46SYS_CLK Input/Output 2.5V-5.0V, CMOS 2.5V-5.0V VP26OUT4Output8.0V-18.0V Power MOSFET-29OUT3Output8.0V-18.0V Power MOSFET-32OUT2Output8.0V-18.0V Power MOSFET-35OUT1Output8.0V-18.0V Power MOSFET-Table 1. I/O Power Rails3.TYPICAL CONNECTION DIAGRAMSFigure 1. Typical Connection Diagram - Software ModeFigure 2. Typical Connection Diagram - Hardware Mode4.TYPICAL SYSTEM CONFIGURATION DIAGRAMSFigure 3. Typical System Configuration 1Figure 4. Typical System Configuration 2Figure 5. Typical System Configuration 3Figure 6. Typical System Configuration 45.CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONSAGND = DGND = PGND = 0 V; all voltages with respect to ground.Notes:1.For VD =2.5 V, VA_REG and VD_REG must be connected to VD. See section 6.7 on page 63 fordetails.ABSOLUTE MAXIMUM RATINGSAGND =DGND =PGND =0V; all voltages with respect to ground.WARNING:Operation at conditions beyond the Recommended Operating Conditions may affect device reliability,and functional operation beyond Recommended Operating Conditions is not implied.Notes:2.Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not causeSCR latch-up.3.The maximum over/under voltage is limited by the input current.ParametersSymbol Min Nom Max UnitsDC Power SupplyDigital and Analog Core(Note 1)VD 2.375 2.5 2.625V VD 3.135 3.3 3.465V VD4.755.0 5.25V Amplifier OutputsVP 8.0-18.0V TemperatureAmbient Temperature T A 0-+70°C Junction TemperatureT J-+125°CParametersSymbol Min Max UnitsDC Power SupplyPower Stage Outputs Switching and Under LoadPower StageNo Output SwitchingDigital and Analog CoreVP VP VD -0.3-0.3-0.319.823.06.0V V V InputsInput Current (Note 2)I in -±10mA Analog Input Voltage (Note 3)V INA AGND - 0.7VA_REG + 0.7V Digital Input Voltage(Note 3)V IND-0.3VD + 0.4VTemperatureAmbient Operating Temperature - Power AppliedCommercialT A -20+85°C Storage TemperatureT stg-65+150°C。
ADI中文版数据手册说明书
Rev. 0 Document FeedbackInformation furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Speci cations subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support ADI 中文版数据手册是英文版数据手册的译文，敬请谅解翻译中可能存在的语言组织或翻译错误，ADI 不对翻译中存在的差异或由此产生的错误负责。
如需确认任何词语的准确性，请参考ADI 提供的最新英文版数据手册。
典型应用电路CHANNEL 2BUCK REGULATOR (1.2A/2.5A/4A)CHANNEL 3BUCK REGULATOR(1.2A)OSCILLATOR INT VREG 100mAQ1Q2L1L2VREGSYNC/MODERT FB1BST1SW1DL1PGND DL2SW2BST2FB2L3BST3SW3FB3PGND3L4BST4SW4FB4PGND4VREGPVIN1COMP1EN1PVIN2COMP2EN2PVIN3PWRGD SS34COMP3EN3PVIN4COMP4EN4C2C1C4C3C5C6C7C8C9C10C11C12C134.5V TO 15VVOUT1VOUT2VOUT3VOUT4R ILIM1R ILIM2VREGEXPOSED PADSS12C0VDDCHANNEL 5200mA LDO REGULATORFB5PVIN5EN5VOUT5C14C15VOUT51.7V TO 5.5VADP5052CHANNEL 1BUCK REGULATOR (1.2A/2.5A/4A)CHANNEL 4BUCK REGULATOR(1.2A)10900-001图1.带四通道降压调节器和200 mA LDO 调节器的5通道集成式电源解决方案产品特性宽输入电压范围：4.5 V 至15 V输出精度：±1.5%(整个温度范围内)可调开关频率范围：250 kHz 至1.4 MHz 可调/固定输出选项，可通过工厂熔丝调节电源调节通道1和通道2：带低端FET 驱动器的可编程1.2 A/2.5 A/4 A 同步降压调节器通道3和通道4：1.2 A 同步降压调节器通道5：200 mA 低压差(LDO)调节器针对小负载要求，5.1 V LDO 电源始终处于激活状态8 A 单通道输出(通道1和通道2并联工作)精密使能，0.8 V 精确阈值有源输出放电开关FPWM 或自动PWM/PSM 模式选择频率同步输入或输出针对OVP/OCP 故障提供可选的闩锁保护所选通道的电源良好指示UVLO 、OCP 和TSD 保护48引脚7 mm × 7 mm LFCSP 封装结温范围：−40°C 至+125°C应用小型蜂窝基站FPGA 和处理器应用安防和监控医疗应用概述ADP5052在一个48引脚LFCSP 封装中集成了四个高性能降压调节器和一个200 mA 低压差(LDO)调节器，可满足严苛的性能和电路板空间要求。
外文翻译---STC89C52 数据手册
外文翻译---STC89C52 数据手册STC89C52 Date XXXThe STC89C52 is a high-performance and low-power CMOS 8-bit microcontroller that comes with 8K bytes of in-system programmable Flash memory。
It is manufactured using Atmel's high-density XXX and is compatible with the industry-standard 80C51 n set and pinout。
The device's on-chip Flash enables the program memory to be reprogrammed in-XXX STC89C52 XXX combines a versatile 8-bit CPU with in-system programmable Flash on a single chip。
This makes it a highly-flexible and cost-XXX.In n。
the STC89C52 XXX for a wide range of embedded control ns。
Its in-system programmable Flash XXX industry-standard 80C51 n set make it an XXX.The STC89C52 microcontroller is equipped with us standard features。
including 8Kbytes of Flash。
256 bytes of RAM。
32I/O lines。
a watchdog timer。
two data pointers。
CS5205-2中文资料
CS5205−25.0 A, 1.5 V Fixed Linear RegulatorThe CS5205−2 linear regulator provides 5.0 A @ 1.5 V with an accuracy of ±2.0%.The regulator is intended for use as an active termination for the GTL bus on Intel based motherboards. The fast loop response and low dropout voltage make these regulators ideal for applications where low voltage operation and good transient response are important.The circuit is designed to operate with dropout voltages as low as 1.0 V depending on the output current level. The maximum quiescent current is only 10 mA at full load.The regulator is fully protected against overload conditions with protection circuitry for Safe Operating Area (SOA), overcurrent and thermal shutdown.The CS5205−2 is available in TO−220−3 and surface mount D 2PAK−3packages.Features•Output Current to 5.0 A•Output V oltage Trimmed to ±2.0%•Dropout V oltage 1.2 V @ 5.0 A •Fast Transient Response •Fault Protection Circuitry −Thermal Shutdown −Overcurrent Protection −Safe Area ProtectionFigure 1. Block DiagramV OUTGNDV INSee detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.ORDERING INFORMATIONMAXIMUM RATINGS*2.60 second maximum above 183°C*The maximum package power dissipation must be observed.ELECTRICAL CHARACTERISTICS (C IN = 10 m F, C OUT = 22 m F Tantalum, V IN − V OUT = 3.0 V, V IN≤ 10 V, 0°C ≤ T A≤ 70°C, T≤ +150°C, unless otherwise specified, I = 5.0 A)Fixed Output Voltagevoltage due to thermal gradients or temperature changes must be taken into account separately.4.Specifications apply for an external Kelvin sense connection at a point on the output pin 1/4” from the bottom of the package.5.Dropout voltage is a measurement of the minimum input/output differential at full load.PACKAGE PIN DESCRIPTIONTYPICAL PERFORMANCE CHARACTERISTICSFigure 2. Dropout Voltage vs. OutputCurrentFigure 3. Reference Voltage vs.TemperatureFigure 6. Ripple Rejection vs. Frequency(Fixed Versions)T J (°C)0.1010O u t p u t V o l t a g e D e v i a t i o n (%)0.080.060.040.020.00−0.02−0.04−0.06−0.08−0.10−0.1202030405060708090100110120130Frequency (Hz)10101010100Output Current (A)D r o p o u t V o l t a g e (V )1.301.251.201.151.101.051.000.950.900.850.800.750.7012345O u t p u t V o l t a g e D e v i a t i o n (%)0.2000.1750.1500.1250.1000.0750.0500.0250.000APPLICATIONS INFORMATIONThe regulator is protected against short circuit, and includes thermal shutdown and safe area protection (SOA) circuitry. The SOA protection circuitry decreases the maximum available output current as the input−output differential voltage increase.The CS5205−2 has a composite PNP−NPN output transistor and requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section.Stability ConsiderationsThe output or compensation capacitor helps determine three main characteristics of a linear regulator: start−up delay, load transient response, and loop stability.The capacitor value and type is based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution. However, when the circuit operates at low temperatures, both the value and ESR of the capacitor will vary considerably. The capacitor manufacturer’s data sheet provides this information.A 22 m F tantalum capacitor will work for most applications, but with high current regulators such as the CS5205−2 the transient response and stability improve with higher values of capacitance. The majority of applications for this regulator involve large changes in load current so the output capacitor must supply the instantaneous load current. The ESR of the output capacitor causes an immediate drop in output voltage given by:D V+D I ESRFor microprocessor applications it is customary to use an output capacitor network consisting of several tantalum and ceramic capacitors in parallel. This reduces the overall ESR and reduces the instantaneous output voltage drop under transient load conditions. The output capacitor network should be as close to the load as possible for the best results.Protection DiodesWhen large external capacitors are used with a linear regulator it is sometimes necessary to add protection diodes. If the input voltage of the regulator gets shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage and the rate at which V IN drops. In the CS5205−2 linear regulator, the discharge path is through a large junction and protection diodes are not usually needed. If the regulator is used with large values of output capacitance and the input voltage is instantaneously shorted to ground, damage can occur. In this case, a diode connected as shown in Figure 7 is recommended.Figure 7. Protection Diode Scheme for FixedOutput RegulatorsOutput Voltage SensingSince the CS5205−2 is a three terminal regulator, it is not possible to provide true remote load sensing. Load regulation is limited by the resistance of the conductors connecting the regulator to the load. For best results the regulator should be connected as shown in Figure 8.Figure 8. Conductor Parasitic Resistance EffectsCan Be Minimized With the Above GroundingScheme for Fixed Output RegulatorsV INConductor ParasiticR LOADCalculating Power Dissipation and Heat Sink RequirementsThe CS5205−2 includes thermal shutdown and safe operating area circuitry to protect the device. High power regulators such as these usually operate at high junction temperatures so it is important to calculate the power dissipation and junction temperatures accurately to ensure that an adequate heat sink is used.The case is connected to V OUT on the CS5205−2, electrical isolation may be required for some applications. Thermal compound should always be used with high current regulators such as these.The thermal characteristics of an IC depend on the following four factors:1.Maximum Ambient Temperature T A (°C)2.Power dissipation P D (Watts)3.Maximum junction temperature T J (°C)4.Thermal resistance junction to ambient R q JA (°C/W) These four are related by the equationT J+T A)P D R Q JA(1) The maximum ambient temperature and the power dissipation are determined by the design while the maximum junction temperature and the thermal resistance depend on the manufacturer and the package type.The maximum power dissipation for a regulator is:P D(max)+{V IN(max)*V OUT(min)}I OUT(max))V IN(max)I Q(2) where:V IN(max) is the maximum input voltage,V OUT(min) is the minimum output voltage,I OUT(max) is the maximum output current, for the applicationI Q is the maximum quiescent current at I OUT(max).A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air.Each material in the heat flow path between the IC and the outside environment has a thermal resistance. Like series electrical resistances, these resistances are summed to determine R q JA, the total thermal resistance between the junction and the surrounding air.1.Thermal Resistance of the junction to case, R q JC(°C/W)2.Thermal Resistance of the case to Heat Sink, R q CS(°C/W)3.Thermal Resistance of the Heat Sink to the ambientair, R q SA (°C/W)These are connected by the equation:R Q JA+R Q JC)R Q CS)R Q SA(3) The value for R q JA is calculated using equation (3) and the result can be substituted in equation (1).R q JC is 1.6°C/Watt for the CS5205−2. For a high current regulator such as the CS5205−2 the majority of the heat is generated in the power transistor section. The value for R q SA depends on the heat sink type, while R q CS depends on factors such as package type, heat sink interface (is an insulator and thermal grease used?), and the contact area between the heat sink and the package. Once these calculations are complete, the maximum permissible value of R q JA can be calculated and the proper heat sink selected. For further discussion on heat sink selection, see application note “Thermal Management,” document number AND8036/D, available through the Literature Distribution Center or via our website at .ORDERING INFORMATIONSpecifications Brochure, BRD8011/D.TO−220THREE LEAD T SUFFIX CASE 221A−08ISSUE AANOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: INCH.SEATING PLANEDIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.5600.62514.2315.87B 0.3800.4209.6610.66C 0.1400.190 3.56 4.82D 0.0250.0350.640.89F 0.1390.155 3.53 3.93G 0.100 BSC 2.54 BSC H −−−0.280−−−7.11J 0.0120.0450.31 1.14K 0.5000.58012.7014.73L 0.0450.060 1.15 1.52N 0.200 BSC 5.08 BSC Q 0.1000.135 2.54 3.42R 0.0800.115 2.04 2.92S 0.0200.0550.51 1.39T 0.2350.255 5.97 6.47U 0.0000.0500.00 1.27V0.045−−−1.15−−−D2PAK−3DP SUFFIXCASE 418AB−01ISSUE OFor D2PAK Outline and Dimensions − Contact Factory PACKAGE THERMAL DATA*Depending on thermal properties of substrate. R q JA=R q JC+R q CAON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。
AT89S52中文手册
主要性能Array l 与MCS-51单片机产品兼容l 8K字节在系统可编程Flash存储器l 1000次擦写周期l 全静态操作：0Hz～33Hzl 三级加密程序存储器l 32个可编程I/O口线l 三个16位定时器/计数器l 八个中断源l 全双工UART串行通道l 低功耗空闲和掉电模式l 掉电后中断可唤醒l 看门狗定时器l 双数据指针l 掉电标识符功能特性描述A T89S52是一种低功耗、高性能CMOS8位微控制器，具有8K在系统可编程Flash存储器。
使用Atmel公司高密度非易失性存储器技术制造，与工业80C51产品指令和引脚完全兼容。
片上Flash允许程序存储器在系统可编程，亦适于常规编程器。
在单芯片上，拥有灵巧的8位CPU和在系统可编程Flash，使得A T89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。
A T89S52具有以下标准功能：8k字节Flash，256字节RAM，32位I/O口线，看门狗定时器，2个数据指针，三个16位定时器/计数器，一个6向量2级中断结构，全双工串行口，片内晶振及时钟电路。
另外，A T89S52可降至0Hz静态逻辑操作，支持2种软件可选择节电模式。
空闲模式下，CPU 停止工作，允许RAM、定时器/计数器、串口、中断继续工作。
掉电保护方式下，RAM内容被保存，振荡器被冻结，单片机一切工作停止，直到下一个中断或硬件复位为止。
引脚结构方框图引脚功能描述VCC : 电源GND:地P0口：P0口是一个8位漏极开路的双向I/O口。
作为输出口，每位能驱动8个TTL逻辑电平。
对P0端口写“1”时，引脚用作高阻抗输入。
当访问外部程序和数据存储器时，P0口也被作为低8位地址/数据复用。
在这种模式下，P0具有内部上拉电阻。
在flash编程时，P0口也用来接收指令字节；在程序校验时，输出指令字节。
程序校验时，需要外部上拉电阻。
P1口：P1口是一个具有内部上拉电阻的8位双向I/O口，p1输出缓冲器能驱动4个TTL逻辑电平。
CLL752中文资料
Continental Device India Limited Data Sheet Page 1 of 3SILICON ZENER DIODESHermetically Sealed Glass Silicon Zener DiodesSOD-80C Zener DiodesCLL750 to CLL759, 500mW Hermetically Sealed, Glass Silicon Zener DiodesElectrical Characteristics : T A = 25°C, V F = 1.5 V Max @ 200 mA for all types Nominal TestMax Reverse Leakage CurrentType Zener Voltage Current Max Zener Impedance Maximum No.VZ@ IZT I ZT Z ZT @ I ZT DC Zener CurrentT A = 25ºC T A = 150ºC (Note 1)(Note 2)(Note 2)Ohms I ZM I R @ V R = 1 VI R @ V R = 1 VVoltsmA mA µAµACLL750 4.720197595 2.030CLL751 5.120177085 1.020CLL752 5.620116580 1.020CLL753 6.220760700.120CLL754 6.820555650.120CLL7557.520650600.120CLL7568.220845550.120CLL7579.1201040500.120CLL75810.020*******.120CLL75912.0203030350.120Polarity :Cathode indicated by colour band.Note 1:CLL750 Series : ± 10% tolerance; Suffix A ± 5% tolerance.Note 2 : Pulse test : 20ms ≤ tp ≤ 50ms.Continental Device India LimitedAn ISO/TS 16949, ISO 9001 and ISO 14001 Certified CompanyCLL750_759Rev210902ESOD - 80CMini MELF (LL-34)All Dimensions are in mmSOD 80C (LL-34) Mini MELF Hermetically Sealed Glass PackageDrawings are not to scaleAll Dimensions are in mmAll Dimensions are in mmIdentification Label 2,500No. of Device Notes:1.Maximum of 0.5% of the total number of components per reel may be missing-exclusively at the beginning and at the end of the reel.2.A maximum of three consecutive components may be missing, provided this gap is followed by six consecutive components.TAPE & REELDe-reeling direction De-reeling directionSOD-80C T&R 2.5K/reel 225 gm/2.5K pcs 9" x 9" x 9"40K18" x 12" x 10"19" x 19" x 20"80K 320K 7.2 kgs 28.8 kgsPACKAGENet Weight/Qty Details STANDARD PACK INNER CARTON BOXQtyOUTER CARTON BOXQty Gr Wt Size Size Packing DetailContinental Device India LimitedData SheetPage 2 of 3CLL750_759Rev210902EComponent Disposal Instructions1. CDIL Semiconductor Devices are RoHS compliant, customers are requested to please dispose as per prevailing Environmental Legislation of their Country.CLL750_759Rev210902ECustomer NotesDisclaimerThe product information and the selection guides facilitate selection of the CDIL's Semiconductor Device(s)best suited for application in your product(s)as per your requirement.It is recommended that you completely review our Data Sheet(s)so as to confirm that the Device(s)meet functionality parameters for your application.The information furnished in the Data Sheet and on the CDIL Web Site/CD are believed to be accurate and reliable.CDIL however,does not assume responsibility for inaccuracies or incomplete information.Furthermore,CDIL does not assume liability whatsoever,arising out of the application or use of any CDIL product;neither does it convey any license under its patent rights nor rights of others.These products are not designed for use in life saving/support appliances or systems.CDIL customers selling these products (either as individual Discrete Semiconductor Devices or incorporated in their end products),in any life saving/support appliances or systems or applications do so at their own risk and CDIL will not be responsible for any damages resulting from such sale(s).CDIL strives for continuous improvement and reserves the right to change the specifications of its products without prior notice.CDIL is a registered Trademark of Continental Device India LimitedC-120 Naraina Industrial Area, New Delhi 110 028, India.Telephone + 91-11-2579 6150, 4141 1112 Fax + 91-11-2579 5290, 4141 1119email@ Continental Device India Limited Data Sheet Page 3 of 32. In Europe, please dispose as per EU Directive 2002/96/EC on Waste Electrical and Electronic Equipment (WEEE).SOD - 80CMini MELF (LL-34)元器件交易网。
ASIO4ALL_v2中文手册
ASIO4ALL v2中文手册ASIO4ALL v2通用 ASIO 驱动 & 适应于 WDM 音频- 中文手册 -(发布日期: 12/07/04)目录简介 (1)入门指南 (1)软件配置 (1)简易设置 (2)高级设置 (3)应用指南 (5)疑难解答 (5)简介欢迎使用ASIO4ALL v2！这份手册希望能帮助你充分使用好已安装的ASIO4ALL，本手册尤其将重点介绍最新加入到这个ASIO4ALL版本中的高级功能。
ASIO4ALL v2在安装之后将自动添加两个新的快捷方式图标到你的系统桌面上，一个链接到本手册，另一个则用来以脱机状态调用ASIO4ALL的控制面板。
入门指南软件配置在使用ASIO4ALL之前，你需要对相关的音频软件进行适当地配置。
要如何设置，这完全取决于你指定的应用程序。
通常，你可以在该软件的音频配置菜单中将ASIO驱动指定为“ASIO4ALL v2”。
现在你应该可以找到一个用来开启ASIO 控制面板的按钮。
这个按钮被定义到哪个选项卡内也完全取决于应用程序本身。
当你找到并按下此按钮，ASIO4ALL控制面板将弹出。
如果需要的话，请查阅该音频软件的联机帮助以获取更多信息。
有时，音频软件并没有提供可用的ASIO控制面板选项。
像Winamp和Foobar2000 的某些ASIO 输出插件就存在这种情况。
不管怎样，为配置ASIO4ALL 和这些应用程序，你还是可以从桌面上调用ASIO4ALL 的脱机控制面板。
注意，脱机控制面板在工作上如同自身的ASIO宿主，它无法同时反映出任何ASIO4ALL请求所打开的当前设备状态！只有当你重新启动音频软件后，脱机控制面板中所作的设置更改才会生效。
也就是说，相对于从已进行了适当配置的音频软件内部加载ASIO4ALL（联机）控制面板的方式而言，用户在脱机控制面板所作的设置将完全无法取得实时效果。
一旦你进入ASIO4ALL控制面板，就已经可以进行一些基本的设置操作了。
sl523中文资料_数据手册_IC数据表
SL523100MHz DUAL WIDEBAND LOG AMPLIFIER The SL523B and C are wideband amplifiers for use insuccessive detection logarithmic IF strips operating at centrefrequencies between 10 and 100MHz They are pincompatible with the SL521 series of logarithmic amplifiers andcomprise two amplifiers internally connected in cascadeSmall signal voltage gain is 24dB and an internal detector withan accurate logarithmic characteristic over a 20dB rangeproduces a maximum Output of 2.1 mA. A strip of SL523s canbe directly coupled and decoupling is provided on eachamplifier RF limiting occurs at an input voltage of 25mV RMSbut the device will withstand input voltages up to 1 8V RMSwithout damageThe device is also available as the 5962-89803 which hasguaranteed operation over the full Military TemperatureRange and is screened to MIL-STD-883 Class B. Data isavailable separately.FEATURESs Small Size/Weights Low Power Consumptions Readily Cascadables Accurate Logarithmic Detector Characteristic ABSOLUTE MAXIMUM RATINGS(Non-simultaneous)Storage temperature range-65°C to +150°C Operating temperature range-55°C to +125°C Thermal resistanceChip-to-ambient200°C/W Chip-to-case52°C/W Maximum instantaneous voltageat video output+12V Supply voltage +9V Fig.1 Pin connections (view from beneath)CM8Fig.2 Circuit diagram (one amplifier)DS3607 - 2.0QUICK REFERENCE DATAs Small Signal Voltage Gain: 24dBs Detector Output Current: 21mAs Noise Figure: 4dBs Frequency Range: 10-100MHzs Supply Voltage +6Vs Supply Current 30mAORDERING INFORMATIONSL523 B CMSL523 C CMSL523 CB CM5962-89803 (SMD)ADVANCE INFORMATIONSL523ELECTRICAL CHARACTERISTICSThese characteristics are guaranteed over the following condltions (unless otherwise stated)Ambient temperature = 22°C ± 2°C; Source impedance = 10Ω; Supply voltage = +6V; Load impedance = 8pF;Frequency = 60MHz; DC connection between Pin 6 and 7Fig.4 Voltage gain v. frequency (typical)OPERATING NOTESThe amplifier is designed to be directly coupled (seeFig.5)The fourth stage in an untuned cascade will give full output on the broad band noise generated by the first stage.Noise may be reduced by inserting a single tuned circuit in the chain As there is a large mismatch between stages a simple shunt or series circuit cannot be used The network chosen must give unity voltage gain at resonance to avoid distorting the log law The typical value for input impedance is 500Ω in parallel with 5pF and the output impedance is typically 30Ω.Although a 1nF supply line decoupling capacitor is included in the can an extra capacitor is required when the amplifiers are cascaded Minimum values for this capacitor are: 2 stages - 3nF, 3 or more stages 30nFIn cascades of 3 or more stages care must be taken to avoid oscillations caused either by inductance common to the input and output earths of the strip or by feedback along the common video line The use of a continuous earth plane will avoid earth inductance problems and a common base amplifier in the video line isolating the first two stages as shown in Fig 6 will eliminate feedback on the video lineFig.3 Rectified output current v. input signal (typical)Note:-Overload occurs when the input signal reaches a level sufficient to forward bias the base-collector junction to the inputtransistor on peaksSL523Fig.5 Simple log. IF stripFig.6 Wide dynamic range log. IF stripFig.7 Wideband logarithmic amplifierSL523Fig.9c Frequency response, detected outputTYPICAL PERFORMANCEUnselected SL523B devices were tested in a wideband logarithmic amplifier. described in RSRE Memo No 3027 and shown in Fig 7The amplifier consists of six logarithmic stages and two ‘lift’stages, giving an overall dynamic range of greater than 80dB The response and error curves were plotted on an RHG Log Test Set and bandwidth measurements were made with a Telonic Sweeper and Tektronix oscilloscopeFig 8 shows the dynamic range error curve and f requency response obtained. The stage gains of the SL523 devices used were as shown in Table 1The input v output characteristic (Fig.8a) is calibrated at 10dB/cm in the X axis and 1V/cm in the Y axis 80dB of dynamic range was attainedThe error characteristic (Fig 8b) is calibrated at 10dB/cm in the X axis and 1dB/cm in the Y axis; this shows the error between the log input v. output characterisitc and a mean straight line and shows that a dynamic range of 80dB was obtained with an accuracy of ±0.5dBAs a comparison, the log amplifier of Fig 7 was constructed with randomly selected SL521 Bs (two SL521 Bs replacing each SL523B). Again, a dynamic response of 80dB was obtained (Fig 9a) with an accuracy of 1 0 75dB (Fig.9b)Bandwidth curves are shown in Figs.8c and 9c, where the amplitude scale is 2dB/cm, with frequency markers at 10MHz intervals from 20 to 100MHz Using SL523Bs (Fig.8c), the frequency response at 90MHz is 4dB down on maximum and there is a fall-off in response after 50MHz Fig 9c shows that the frequency response of the amplifier falls off more gradually after 40MHz but again the response at 90MHz is 4dB down on maximumThese tests show that the SL523 is a very successful dual stage log amplifier element and, since it is pin-compatible with the SL521 enables retrofit to be carried out in existing log amplifiers It will be of greatest benefit however, in the design of new log amplifiers, enabling very compact units to be realised with a much shorter summation lineTable 1 Stage gains of SL523 used in performance testsFig.8a Input/output Fig.8b Error curve Fig.8c Frequency response, detected outputFig.9a Input/outputFig.9b Error curveFig.8 Characteristics of circuit shown in Fig 7 using SL523BsFig.9 Characteristics of circuit shown in Fig 7 using SL523Bs。
2SC5200中文资料(ST)中文数据手册「EasyDatasheet - 矽搜」
(IC = 0)
V(BR)CEO(1)
集电极 - 发射极击穿 电压（I B = 0)
集电极 - 基极击穿 V（BR）CBO 电压（I E = 0)
V(BR)EBO(1)
发射基地击穿
电压（I C = 0)
VCE(sat)(1)
集电极 - 发射极饱和
电压
VBE
基极 - 发射极电压
hFE DC
阻性负载
ton
开启时间
ts
贮存时间
tf
下降时间
f
转换频率
C
(IE = 0)
时间= 300微秒,占空比
电气特性
测试条件
VCB = 230 V
VEB = 5 V
IC =50毫安
IC = 100 µA
IE =1毫安
IC = 8 A
I =7A I =1A I =7A
I =800
V =5V V E =5V VCE = 5 V
Value 0.83
Unit V V V A A W °C °C
Unit °C/W
Doc ID 16310 Rev 1
芯片中文手册,看全文,戳
2SC5200
2
电气特性
Tcase = 25°C除非另有说明
表 4.
电气特性
符
参数
集电极截止电流
ICBO
(IE = 0)
发射极截止电流
I EBO
µs
30
MHz
150
pF
文件编号16310牧师1
芯片中文手册,看全文,戳
电气特性
2.1
电气特性（曲线）
图 2.
安全工作区
图 3.
降额曲线
DSP-152M中文资料
ЖTFDEJW
%44–401L, DSSV–401M–YD, DSSV–401M–T5 %0$ЖTFD7ҹՃ
7EJW
7EJW
όϦελɹVaristor 270V
ЖTFDEJW
όϦελɹVaristor 390V
ЖTFDEJW
S
ϊʔςʔϐϯά No taping
00
ςʔϐϯάੇ๏ Taping dimensions
߸ه Symbol
୯ҐɿmmɹUnit:mm
ςʔϓଆ෯ Taping width
ϐον Pitch
04
ʢϥδΞϧςʔϐϯάʣ (Radial taping)
12.7
12
26
10
22
52
10
00
ϊʔςʔϐϯά No taping
16
元器件交易网
SURGE ABSORBER
˙ಛ
α ˔ඇৗʹখ͋ͰܕΔʹ͔͔ΘΒͣɺ์ి։࢝ిѹ͕ߴిѹͰ͢ɻ
ồ δ
ʢ2700, 3000Vͷ2छʣ
Ξ ˔DSS-272MAC1200V-3ඵ·ͨ"$7ɺDSS-302MAC1500V-1
˙ߏ໊ܗ Part number system
DSSV
γϦʔζ໊ Series
ʵ 301
ྲྀ์ి։࢝ిѹʢVsʣ DC Spark-over voltage(Vs)
Lʵ
ྲྀ์ి։࢝ిѹڐ༰ࠩ DC Spark-over
voltage tolerance
YD
ܗঢ় Shape
࠷ॳͷ2ࣈిѹͷ༗ޮࣈͰ ୈ3ࣈΛද͢ɻ
DC 100V
DC 250V DC 100V DC 250V
MSK 4322 数据手册
MIL-PRF-38534 QUALIFIEDFEATURES:200V, 20 Amp CapabilityUltra Low Thermal Resistance - Junction to Case - 1.0°C/W (Each MOSFET)Self-Contained, Smart Lowside/Highside Drive Circuitry Under-Voltage Lockout, Internal 2µS Deadtime Capable of Switching Frequencies to 25KHz Isolated Case Allows Direct Heat SinkingCase Bolt-down Design Allows Superior Heat DissipationDESCRIPTION:The MSK 4322 is a 20 Amp, 3 Phase Bridge Smart Power Motor Drive Hybrid with a 200 volt rating on the output switches. The output switches are power MOSFETs with intrinsic fast-recovery diodes for the free-wheeling currents of motor drives. This new smart power motor drive hybrid is compatible with 5V CMOS or TTL logic levels. The internal circuitry prevents simultaneous turn-on of the in-line half bridge transistors with a built-in 2µS deadtime to prevent shoot-through. Undervoltage lockout shuts down the bridge when the supply voltage gets to a point of incomplete turn-on of the output switches. The internal high-side boot strap power supply derived from the +15 volt supply completely eliminates the need for 3 floating independent power sup-plies for the high-side drive. Current sense circuitry is provided to sense current from an external resistor to shut down the bridge for overcurrent.3 PHASE SIX STEP DC BRUSHLESS MOTOR DRIVE OR 3 PHASE SINUSOIDAL INDUCTION MOTOR DRIVE12345678910VCC AØHIN BØHIN CØHIN AØLIN FAULT CØLIN BØLIN VSS ITRIP20191817161514131211N/C AØV+N/C N/C BØN/C N/C CØCOM查询MSK4322供应商GROUP A SUBGROUP5V+High Voltage Supply.......200V V CC Logic Supply ..........18V I OUT Continuous Output Current ...20A I PK Peak Output Current.......30A θJC Thermal Resistance ......1.0°C/W (Output Switches) (Junction to Case) Storage Temperature RangeLead Temperature Range(10 Seconds) Case Operating Temperature MSK 4322 MSK 4322HJunction Temperature1Guaranteed by design but not tested. Typical parameters are representative of actual device performance but are for reference only.2Industrial grade devices shall be tested to subgroups 1 and 4 unless otherwise specified.3Military grade devices ("H" suffix) shall be 100% tested to subgroups 1, 2, 3 and 4.4Subgroups 5 and 6 testing available upon request.5Subgroup 1, 4TA =TC =+25°C2, 5TA =TC =+125°C 3, 6TA =TC =-55°CParametersMSK 4322H Min. Typ. Max.V+ = 200V V+ = 160V V+ = 200VV CC = 15V V CC = 15V V+ = 100V, V CC = 15V, I D = 20AV+ = 100V, V CC = 15V, I D = 20A -------------2.2----------3002.05.0TBD 2.0TBD TBD 6007503.0TBD 612TBD -0.8TBDTBD 45350TBD TBD 45350---------------2.2----------300-----------------------2-2.0--2.0--600750--6---0.8TBD TBD 45350TBD TBD 45350--MSK 4322Min. Typ. Max.UNITS OUTPUT CHARACTERISTICSReverse Recovery Time1BIAS SUPPLY CHARACTERISTICSINPUT SIGNAL CHARACTERISTICS Positive Trigger Threshold Voltage Negative Trigger Threshold Voltage SWITCHING CHARACTERISTICS Upper Drive:Turn-On Propagation Delay Turn-Off Propagation Delay Turn-On Turn-Off Lower Drive:Turn-On Propagation Delay Turn-Off Propagation Delay Turn-On Turn-Off Dead Time 1Minimum Pulse Width 1123123-1231231,2,31,2,3----------------------------------2-V V V V V V nS µA mA µA mA mA mA V VnS nS nS nS nS nS nS nS µS nS32Test ConditionsNOTES:VDS(ON) (Each Transistor)Instantaneous Forward Voltage(Intrinsic Diode)Leakage CurrentQuiescent Bias CurrentV CC = 15V (non-switching)I D = 20AI S = 20A1-65° to +150°C300°C-40°C to +85°C -55°C to +125°C +175°CTsT TLD TC TJPROTECTION-All logic inputs use a 300nS filter. A pulse width below this will get ignored.-VCC voltage below the cutoff level of 8.65 volts will reset all switch outputs off and ignore subse-quent logic inputs until VCC is restored.-Undervoltage lockout of the internal drivers for thehigh-side switches also occurs at 8.65 volts, but will not flag with the FAULT output. This may occur if the high-side output gets switched without switch ing the low-side. The interna l boot stra p power supply for the high-side switch will sag too low for adequate switching. The boot strap supply depends on PWMing of the low-side switches for proper opera tion.-Switching a low-side logic input while the corre-sponding pha se high-side logic input is a ctiva ted will turn off both switches. The opposite condition is a lso true. This is cross-conduction lockout a nd will occur a ny time low a nd high-side inputs for a ph a se a re a ctiv a ted a t the s a me time.-A 2µS dea dtime is a utoma tica lly inserted between high a nd low-side output switching to a llow com-plete turn-off of ea ch switch so no overla p will occur.-An overcurrent condition detected by the ITR IP pin will shut down a ll output switches until the overcurrent condition is removed a nd a ll three low-side logic inputs a re held high for 10µS,then normal operation will resume.-ITRIP ha s a 100nS lea ding edge bla nking time a fter switching to ignore a ny switching current tra nsients.TYPICAL OPERATIONMSK 4322 PIN DESCRIPTIONVCC - Is the low voltage supply for all the internal logic and drivers. A 0.1 µF ceramic capacitor in parallel with a 10µF tantalum capacitor is recommended bypassing for the VCC-VSS pins.VSS - Is the low voltage supply return pin and the input logic return reference. All logic input and logic output is referenced to this pin. This pin can vary ±5V from the COM power return pin without affecting any of the logic functions.AØHIN, BØHIN, CØHIN - Are low active logic inputs for signalling the corresponding phase high-side switch to turn on. The input levels are 5V CMOS or TTL compat-ible. Typica l propa ga tion dela ys a re a round 600nS.AØLIN, BØLIN, CØLIN - Are low active inputs for sig-nalling the corresponding phase low-side switch to turn on. The input levels are 5V CMOS or TTL compatible.Typica l propa ga tion dela ys a re a round 600nS.FAULT - Is a n open dra in logic output pin tha t gets enabled any time the VCC level goes below the cutoff point, or an overcurrent condition occurs. Bringing VCC back to normal levels will reset FAULT . Removing the overcurrent condition and allowing the low-side logic inputs to remain high(off) for 10µS will restore opera-tion.ITRIP - Is an analog input pin for sensing current flow-ing from the COM pin through a sense resistor to the high power ground. A 0.485 volt level at this pin with respect to VSS will signa l a n overcurrent condition,enable the FAULT pin and shut down all output switch-ing. Bringing the volta ge below this point (100 mV hysteresis) will remove the FAULT output and leaving the low-side logic inputs simultaneously high (de-acti-va ted) for 10µS will restore norma l opera tion.V+ - Is the high volta ge positive ra il for the bridge.Proper bypassing to VSS with sufficient capacitance to suppress any voltage transients and to ensure remov-ing any drooping during switching, should be done as close to the pins on the hybrid a s - Is the return side of the bridge. A sense resistor can be connected between this point and VSS , which is the high voltage negative rail. COM can float above and below the VSS pin up to 5 volts and proper opera-tion will be maintained. Precautions should be taken so as to not allow this voltage to get over ±5 volts under any conditions.AØ, BØ, CØ - Are the pins connecting the 3 pha se bridge switch outputs.The MSK 4322 is designed to be used with a +100 volt high voltage bus, +15 volt low power bus and +5 volt logic signals. Proper derating should be applied when designing the MSK 4322 into a system. High frequency layout techniques with ground planes on a printed circuit board is the only method that should be used for circuit construction. This will prevent pulse jitter caused by excessive noise pickup on the current sense signal or the error amp signal.Ground planes for the low power circuitry and high power circuitry should be kept separate. The connection between the bottom of the current sense resistor, VSS pin and the high power ground are connected at this point. This is a critical path and high currents should not be flowing between the current sense and VSS. Inductance in this path should be kept to a minimum. An RC filter (shown in 2 places) will filter out the current spikes and keep the detected noise for those circuits down to a minimum.In the system shown, two types of current limit are implemented. The first limit is a PWM pulse by pulse limit controlled by the motor controller. A second absolute maximum limit is set up for the MSK 4322 which will completely shut off the bridge in the event that current limit is exceeded.When controlling the motor speed by the PWM method, it is required that the low side switches be PWM pulsed due to the charge pump power supplies used to power the high side switch drives. The higher the PWM speed the higher the current load on the drive supply. PWM of the low side will prevent sagging of the high side supplies. The logic signals coming from the typical motor controller IC are set up for driving N channel low side and P channel high side switches directly and are usually 15 volt levels. Provision should be made for getting 5 volt logic signals to the MSK 4322 of the correct assertion levels. Typically, the low side signals out of the controller are high active and the high side are low active. Inverters are shown in the system schematic for the low side control-ler output.The information contained herein is believed to be accurate at the time of printing. MSK reserves the right to make changes to its products or specifications without notice, however and assumes no liability for the use of its products.ORDERING INFORMATIONMSK4322 H ULEAD CONFIGURATIONSS = STRAIGHT; U = BENT UP; D = BENT DOWN SCREENINGBLANK = INDUSTRIAL;H = MIL-PRF-38534GENERAL PART NUMBERAll dimensions are ±0.01 inches unless otherwise specified.M.S. Kennedy Corp.4707 Dey Road, Liverpool, New York 13088Phone (315) 701-6751FAX (315) 。
CDLL5232B中文资料
CDI TYPE NUMBER NOMINAL ZENER VOLTAGE VZ @ lZT (Note 1 & 3) VOLTS 2.4 2.5 2.7 2.8 3.0 3.3 3.6 3.9 4.3 4.7 5.1 5.6 6.0 6.2 6.8 7.5 8.2 8.7 9.1 10 11 12 13 14 15 16 17 18 19 20 22 24 25 27 28 30 33 36 39 43 47 51 56 60 62 68 75 82 87 91 100 110 MAXIMUM ZENER IMPEDANCE (Note 2) ZZT @ lZT ZZK@lZK=0.25mA OHMS 30 30 30 30 29 28 24 23 22 19 17 11 7.0 7.0 5.0 6.0 8.0 8.0 10 17 22 30 13 15 16 17 19 21 23 25 29 33 35 41 44 49 58 70 80 93 105 125 150 170 185 230 270 330 370 400 500 750 OHMS 1200 1250 1300 1400 1600 1600 1700 1900 2000 1900 1600 1600 1600 1000 750 500 500 600 600 600 600 600 600 600 600 600 600 600 600 600 600 600 600 600 600 600 700 700 800 900 1000 1100 1300 1400 1400 1600 1700 2000 2200 2300 2600 3000 MAXIMUM REVERSE CURRENT lR @ VR
S5215M中文资料
S52xxMLow Drop Output Voltage RegulatorDescriptionThe S52xxM is a u-cap 150mA linear voltage regulator in the SOT-25 package. This regulator has very low dropout voltage and very low ground current. It is designed especially for hand-sets, battery-powered devices and can be controlled by a CMOS or TTL. When the S52xxM is disabled, power consumption drops to nearly zero.Features• Low dropout voltage regulator• Low quiescent current and guaranteed 150mA output • Zero off-mode currentOrdering InformationType NO. Marking Package Code S52xxM5□□SOT - 25□□: V oltage CodeS e m i c o n d u c t o rAbsolute Maximum Ratings Ta=25°CUnitRatingsCharacteristic Symbol~+16 VInput supply voltage V IN -0.4Enable Input Voltage V EN -0.4~+16 VPower Dissipation Pd 500 mW~+125 °CJunction Temperature Range T j -40~+150 °CStorage Temperature Range T stg -60Lead Temperature Time T sol260 (5 Sec) °CElectrical Characteristics=(※V=V+1V; I = 100uA; C=4.7uF; V≥2.0V; T=25℃) Array *Note1 : Dropout V oltage is the difference between the input voltage and the output voltage at whitch point the regulatorstarts to fall out of regulation (this is the point when the output voltage decreases by 100mV).Table 1Electrical Characteristics TableTest Condition; V IN = V OUT(TYP) +1V , I OUT =100uA, T A =25℃, unless otherwise specified.Voltage Limit [V]Output Voltage[V] Voltage CodeMIN MAX1.5 15 1.440 1.560 1.8 18 1.728 1.8722.5 25 2.400 2.600 2.8 28 2.688 2.9123.0 30 2.880 3.120 3.3 33 3.168 3.432 5.0 504.8005.200■Typical ApplicationsElectrical Characteristic CurvesElectrical Characteristic Curves (Cont.)Shutdown (Dis/Enable) OperationThe S52xxM output can be turned off by applying 0.4V or less to the device’s Dis/Enable pin (pin3). In shutdown mode, the S52xxM draws less than 1uA quiescent current. The output of the S52xxM is enabled by applying 1.5V to 13V at the Dis/Enable pin. In applications were the S52xxM output will always remain enabled, the Dis/Enable pin may be connected to Vin(pin1). The S52xxM’s shutdown circuitry includes hysteresis, as such the device will operate properly even if a slow moving signal is applied to the Dis/Enable pin. The device’s shutdown pin includes a 2M Ω internal pull down resistor connected to ground.Short Circuit ProtectionThe S52xxM output can withstand momentary short circuit to ground. Moreover , the regulator can deliver very high output peak current due to its 1A instantaneous short circuit current capability.Noise Bypass CapacitorIn low noise applications, the self noise of the S52xxM can be decreased further by connecting a capacitor from the noise bypass pin (pin4) to ground (pin2). The noise bypass pin is a high impedance node as such care should be taken in printed circuit board layout to avoid noise pick-up from external sources. Moreover , the noise bypass capacitor should have low leakage. Noise bypass capacitors with a value as low as 470pF may be used. However , for optimum performance, use a 0.01uF or larger , ceramic chip capacitor . Note that the turn on and turn off response of the S52xxM is inversely proportional to the value of the noise bypass capacitor . For fast turn on and turn off, use a small value noise Bypass capacitor . In applications were exceptionally low output noise is not required, consider omitting the noise Bypass capacitor altogether .Output Capacitor SelectionAUK strongly recommends the use of low ESR(Equivalent series resistance) ceramic capacitors for Cout and C N . The S52xxM is stable with low ESR capacitor (as low as zero Ω). The value of the output capacitor should be 1uF or higher. Either ceramic chip or a tantalum capacitor may be used at the output. Use of ceramic chip capacitors offer significant advantages over tantalum capacitors. A Ceramic capacitor is typically cheaper than a tantalum capacitor, it usually has a smaller footprint, lower height, and lighter weight than a tantalum capacitor. Furthermore, unlike tantalum capacitors which are polarized and can be damaged if connected incorrectly, ceramic capacitors are non-polarized. Low value ceramic chip capacitors with X5R or X7R dielectric are available in the 100pF to 4.7uF range. Beware of using ceramic capacitors with Y5V dielectric since their ESR increases significantly at cold temperatures. Figure 9 shows a list of recommended ceramic capacitors for use at the output of S52xxM.If a tantalum output capacitor is used then for stable operation AUK recommends a low ESR tantalum capacitor with maximum rated ESR at or below 0.4Ω. Low ESR tantalum capacitors, such as the TPS series from AVX Corporation () or the T495 series from Kemet () may be used.In applications where a high output surge current can be expected, use a high value but low ESR output capacitor for superior load transient response. The S52xxM is stable with no load.Fig. 9C OUT Capacitor Size I OUT Dielectric Part Number Capacitor Vendor1µF 0805 0 to 150mA X5R C2012X5R1A105KT TDK′′0805 ′′X7R GRM40X7R105K010 muRata′′0805 ′′X7R LMK212BJ105KG Taiyo-Yuden ′′1206 ′′X7R GRM42-6X7R105K016 muRata′′1206 ′′X7R EMK316BJ105KL Taiyo-Yuden ′′1206 ′′X5R TMK316BJ105KL Taiyo-Yuden2.2µF 0805 0 to 150mA X5R GRM40X5R225K 6.3 muRata′′0805 ′′X5R C2012X5R0J225KT TDK′′1206 ′′X5R EMK316BJ225ML Taiyo-Yuden4.7µF 1206 0 to 150mA X5R GRM42-6X5R475K010 MuRata′′1206 ′′X7R LMK316BJ475ML Taiyo-Yuden。
ARGUS 152 VDSL+ADSL 多功能测试器数据手册说明书
V D S L+A D S L C O M B I T E S T E RThe VDSL+ADSL universal test setCompact, lightweight and robust: The ARGUS 152 multifunction tester checks interfaces and services quickly and reliably - and at a very reasonable price! VDSL2, ADSL, Ethernet, ISDN (BRI S/T/U) and POTS, as well as the physical condition of the local loop, can be easily tested without having to swap modules. GigaBit Ethernet interface and testsA new high-quality ADSL/VDSL chipset with improved efficiency ensures that the ARGUS 152 delivers high-performance testing and rapid analysis. In addition to resistance, capacitance and voltage measurement, the ARGUS 152 features, when using its Gigabit Ethernet interface, an optional HTTP download, which enables speeds at more than 200 Mbit/s on the protocol level. The ARGUS 152's optional Ethernet cabling tests make it possible to detect shorts, opens or mismatches, but also the delay or polarity of the wire pairs, among other things.Physical analysis of the local loopOn request, the universal tester can also be extended on an individual basis, thus offering the user a high degree of flexibility. For instance, additional copper tests (Cu tests) can be used to assess line quality, even without synchronization with the DSLAM. If necessary, these tests can also be considerably extended in the field by simply connecting the new compact ARGUS Copper Box via USB, thus enabling all important elec-trical parameters such as voltage, current, isolation resistance, symmetry (at 1 MHz), and many more, to be automatically and quickly determined via tip, ring and ground. The optional Active Probe II can even be used to carry out high-impedance measurements on an existing DSL connection, without creating interference on it.To quickly identify any asymmetries between the wires, if required, a symmetry test compares the balance over the whole DSL frequency spectrum (up to 30 MHz) between the tip wire and the ring wire with reference to ground. In the event of damage, the integrated TDR (Time Domain Reflectometer) function can be used to measure line lengths and trace sources of faults, such as bridged taps. Moreover, if required, an Advanced TDR function (Adv. TDR) can be integrated, with which line lengths and sources of faults can be detected even more accurately.If lines without a DSL receiver (e.g. in the case of a rewiring) need to be tested for their DSL suitability, the ARGUS 152 can optionally check this without any problem, even if there is no DSLAM. Regardless of line condition and length, the user can use two devices and an activated Line Qualification (LQ) function to determine data rates, even when systems consisting of a modem (xTU-R) and DSLAM (xTU-C) fail.Triple Play and Quality of Service (QoS)Easy Triple Play testing: The handheld tester also offers an optional Triple Play analysis for testing VoIP, IPTV and data services over xDSL and Ethernet. Thanks to its handset, the ARGUS 152 can simulate not only terminal equipment such as a telephone, PC or STB, but can also determine all relevant quality parameters. In this way, for example, voice quality can be evaluated according to the MOS method. Several of these IP tests can also optionally be performed using the new, more powerful IPv6 protocol.Easy operationThe large 320 x 240 pixel colour display and an intuitive menu structure, among other things, guarantee user-friendly opera-tion. A high-performance Li-Ion battery pack ensures long operating times in the field.intec Gesellschaft für InformationstechnikWith 25 years of experience, intec GmbH is one of the leading suppliers of xDSL, ISDN and IP measurement technology in Europe. With the ARGUS® range, intec is offering practical solutions for installation and troubleshooting of xDSL and ISDN connections.Developed specifically for the needs and daily use by technicians working for international network operators, service providers and installation companies.More than 70 000 ARGUS® testers are already in the field with companies such as Deutsche Telekom, Vodafone, Telefonica, KPN, British Telecom and Telekom Austria who are completely satisfied in the quality of “Made in Germany” intec products.VDSL2, ADSL2+, GigaBit Ethernet, ISDN, POTS, copper as well as VoIP and IPTV testerARGUS ®152 is a compact universal handheld tester for testing all current telecom interfaces.Broadband interfaces:- Synchronisation with the DSLAM (xTU-C) and evaluation of all relevant line parameters and error counters - Including bridge, router and PC replacement mode •ADSL2/2+modem simulation, ADSL tester, ATU-R- Supports ITU-T G.992.5 et alii; Annex A+B+J,+L+M; INP , SRA - Display of Bits, SNR, QLN and Hlog/tone graphs •VDSL2 modem simulation, VDSL tester, VTU-R- Supports ITU-T G.993.2 (8, 12, 17, 30 MHz + var. bandplans)- Supports ITU-T G.998.4, G.INP (Retransmission)- Supports ITU-T G.993.5, G.vector (Vectoring)*- Display of Bits, SNR, QLN and Hlog/tone and stream graphs •Ethernet interface for Triple Play and Ethernet tests - 1 GigaBit Ethernet test interface (10/100/1000 BT), RJ-45- Supports Ethernet terminal mode (PC replacement)Triple Play testing via ADSL, VDSL2 and Ethernet:•ATM layer tests when using ADSL and ADSL2/2+- ATM-OAM ping and ATM-OAM cell, VPI/VCI scan •Data: testing the data throughput (IPv4 and IPv6*)- IP ping and trace route tests (BRAS info, PPP trace, VLAN)- HTTP- and FTP download tests up to 200 Mbit/s- FTP server test, up-/download from ARGUS to ARGUS •Voice: testing VoIP connections based on SIP standard - VoIP terminal simulation, incl. acoustics (various codecs)- OK/FAIL evaluation and display of quality parameters- Evaluation of the VoIP speech quality (QoS) according to: - MOS CQE (ITU-T P .800) based on E model (ITU-T G.107)•Video: testing IPTV and VoD services (STB mode)- Stream request (set-top box mode), IPTV channel scan - OK/FAIL evaluation and display of quality parameters (QoS)- IPTV long-term analysis (WINanalyse)Ethernet tests*:•Cabling tests for checking the Ethernet wiring- Detecting shorts, opens and mismatches and lots more Circuit-switched interfaces:•ISDN: integrated comprehensive ISDN test set- BRI U interface (2B1Q or 4B3T*) acc. to ANSI T1.601- BRI S/T interface acc. to ITU-T I.430 in TE and NT modes - Testing of BRI S/T (S bus) leased lines- Automatic testing of services and supplementary services - Bit error rate testing (BERT) with various bit pattern and analysis according to ITU-T G.821 with OK evaluation - Evaluation of speech quality via the integrated acoustics (speaker, mic., headset) straight on BRI S/T/U interface •POTS: integrated comprehensive POTS test set (analog)- With DTMF and CLIP display, including pulse dial mode - Non-intrusive high-Z monitor, incl. voltage measurement - Evaluation of speech quality via the integrated acoustic Further highlights:•Brilliant QVGA colour display (LCD) with 320 x 240 pixels •Lightweight, compact and easy- to use•Intuitive menu navigation and instant readiness for operation •Free firmware and software updates from /enCopper testing:•RC measurement: resist., capacitance, continuity check - Including loop length calculation (distance to open / short)- DC voltage measurement: up to +200 V; res.: 0.1 V; acc.: ±2 %•Line Scope: high performance real time line monitor with display of frequency domain (FFT) and time domain - Input impedance: 2 k Ω || 10 pF, adjustable gain- Frequency range: 10 kHz to 30 MHz; res.: 0.5 kHz; acc.: ±0.1 %- Level range: -130 to -2 dBm/Hz, res.: 0.1 dB, ±2 dB (at 0 dB)- Voltage range in time domain, AC: 16.5 V pp ; resolution: 0.2 mV pp •ARGUS Active Probe II: high-impedance probe- Impedance: 70 k Ω || <1pF; range: 10 kHz to 30 MHz (±1.5 dB)- Switch between sym./asymmetric measurement mode - Power supplied by ARGUS USB host interface•TDR: Time Domain Reflectometry function for measuring line lengths and locating the faults- Measuring range: 1 up to >6,000 m; res.: 0.025 %/range; ±1 % - Pulse width (adjustable): 5 ns to 6 μs, amplitude: 7 V - Velocity of propagation (VoP): 30 % up to 99.9 % •Line Qualification: Qualifying local loops- DSL data rate estimation, idealized with slave + master - Bandwidth (ADSL, VDSL2) + bandplan (VDSL2) configurable - Sender, Tx power: 12 dBm, 6 dBm, 0 dBm, configurable - Receiver (Rx), sensitivity: up to -150 dBm/Hz- Frequency range: 4,3125 kHz up to 30 MHz (±2 dB)- Impedance: 100 Ω, 120 Ω and 135 Ω, configurable - Supports Bits, SNR, QLN and Hlog per tone diagrams - WB symmetry measurement•Copper Box: Field upgradeable box for expanding the copper tests (see ARGUS Copper Box data sheet - Determines all important electric variables- e.g. DC, AC, current DC, loop and isolation resistance, capacitance and symmetry at 1 MHz for the line - Automatic TRG measurements (Tip, Ring, Ground)Documentation and analysis:•Documentation of all the parameters recorded viaautomatic access tests in test reports (in device and on PC) •Update-Tool for updating the firmware at no charge•WINplus PC software for generating, saving, archiving and printing test reports and for configuring the ARGUS ® (opt.)•WINanalyse PC software for analysis (including WINplus)- Long-term analysis of ADSL and VDSL parameters (graphic)- Long-term analysis of IPTV parameters (graphic)Rahmedestraße 90D-58507 LüdenscheidTel:+49 2351 9070-0Fax:+49 2351 9070-70E-Mail:****************Internet: /enTechnical features:•Power supply by Li-Ion battery pack or mains adaptor•Hotkeys for quick start of various tests•Power management, user configurable•Keypad: 18 keys, 4 cursor keys, 3 context-specific softkeys•LCD colour display (QVGA - 320 x 240 pxs.), backlit•LEDs: 6 LEDs to indicate the status + Ethernet LEDs•Handset with integrated earpiece and microphone•CE marking: complies with CE directives•User safety: fulfils EN 60950-1:2006-11•RoHS conformance acording to WEEE directiveInterfaces:• 2 x RJ-45 jacks for xDSL, copper tests, POTS and ISDN• 1 x Ethernet (10/100 Base-T), RJ-45 management port• 1 x Ethernet (10/100/1000 Base-T), RJ-45 test port•USB client interface (type mini B)•USB host interface (type A)•Headset plug socket (TRS 2.5 mm, approx. 3/32‘‘)Environmental conditions:•Operating temperature: 0 °C (+32 °F) up to +50 °C (+122 °F)•Storing temperature: -20 °C (-4 °F) up to +60 °C (+140 °F)•Relative humidity: up to 95 %, non-condensingDimensions:•Size: H x W x D: 235 x 97 x 65 mm (9.25 x 3.8 x 2.56 in)•Weight: ca. 810 g (1.79 lbs) - incl. battery packStandard package:ARGUS®152 with Li-Ion battery pack, mains adaptor, minimumone DSL interface w/ test leads for this interface, mini USB cable,RC measurement, WINplus PC software (online) printed usermanual and carrying caseBasic packages:ARGUS 152 ADSL Annex A+L+MOrder number: 115202ARGUS 152 ADSL Annex B+JOrder number: 115232ARGUS 152 ADSL Annex A+B+J+L+MOrder number: 115252ARGUS 152 VDSL2Order number: 115272*Options:Additional interfaces:(Additional test leads included, if required)ADSL Annex A+L+M interfaceOrder number: 015205 (interface) or 015245 (extension)ADSL Annex B+J interfaceOrder number: 015206 (interface) or 015246 (extension)VDSL2 interfaceOrder number: 015208POTS interfaceOrder number: 015216ISDN BRI S/T TE interfaceOrder number: 015215ISDN BRI U (TE) interfaceOrder number: 015051 (2B1Q) or 015050 (4B3T*)ISDN BRI S/T TE and POTS interfaceOrder number: 015217ISDN BRI S/T NT (incl. Monitor, 128kBERT, X.31)Order number: 015219Additional test features:(depends on existing interface)ATM test (only ADSL)Order number: 015222IP Download package (via ADSL, VDSL, Ethernet)Order number: 015229VoIP test (via ADSL, VDSL, Ethernet)Order number: 015230IPTV / IPTV ext. (via ADSL, VDSL, Ethernet)Order number: 015237 / 015239TDR (Time Domain Reflectometer)Order number: 015052ARGUS Active Probe IIOrder number: 015091 (for Line Scope)ARGUS Copper Box (incl. protective cover)Order number: 015095Line qualification (LQ) / Adv. copper tests (incl. Adv. TDR)Order number: 015261 / 015262Line qualification + Advanced copper testsOrder number: 015260Additional PC software: (for Windows operating systems)WINplus (incl. CD and Manual)Order number: 010012WINanalyse online (only key, no CD and Manual)Order number: 015062WINanalyse (incl. CD and Manual)Order number: 015042* We would be glad to provide further details and informationabout additional accessories on request.。
CS5212中文规格书
一、CS5212AN功能概述CS5212是一款显示端口到VGA转换器，它结合了显示端口输入接口和模拟RGB DAC 输出接口。
嵌入式MCU基于工业标准8051核心单片机。
CS5212适用于多个细分市场和显示器应用程序，如笔记本电脑、主板、台式机、加密狗和对接系统。
图1-1CS5212方框图二、CS5212AN特性总速2通道VESA DisplayPort v1.1兼容接收机VGA输出接口，8位DAC速度高达210MHz分辨率高达1920x1200x60（RB，缩小消隐），24位色深，1920x1440x60（RB，缩小消隐），或2048x152x60（RB，缩小消隐），24位色深，2048x1536x60（RB，缩小消隐），18位色深。
内置振荡器，不需要外部晶体嵌入式线性压降调节器（LDO）嵌入式微控制器嵌入式EDID（如果终端设备没有，CS5212将响应EDID）嵌入式V-sync/H-sync 5V缓冲器使用内部预置ROM支持EEPROM自由模式内部通电复位（POR）QFN32 4x4封装1.DisplayPort数字输入特性支持2通道数字输入，速度为RBR（1.62-Gbps）/HBR（2.7-Gbps）符合VESA DisplayPort v1.1内置高性能自适应均衡器支持1兆赫辅助通道支持HPD2.VGA输出接口特性三重8位DAC（数模转换器），时钟高达210 MHz，支持高达1920x1200x60、1920x1440x60（缩减消隐）、2048x152x60（缩减消隐）和2048x1536x60（缩减消隐）嵌入式V-sync/H-sync 5V缓冲器用于VGA连接器引脚的HBM 4-KVVESA VSIS v1r2兼容3.嵌入式微控制器工业标准8051芯支持I2C主从，支持400kHz。
4.电力与技术单台3.3V电源V-sync/H-sync 5V缓冲器的5V选项超低待机功率<100uWHBM 8-KV，适用于所有引脚三、CS5212AN引脚定义1.引脚分配图2-1 CS5212引脚布局2.管脚说明表3-1 CS5212引脚定义四、CS5212AN接口和能力1.显示输入作为一个标准的显示端口接收机，CS5212由两个通道的主链路差分对、一个辅助信道差分对和一个HPD信号组成。
BU4525AL资料
Philips Semiconductors Objective specificationSilicon Diffused Power Transistor BU4525ALGENERAL DESCRIPTIONEnhanced performance, new generation, high-voltage, high-speed switching npn transistor in a plastic full-pack envelope intended for use in horizontal deflection circuits of colour television receivers an p.c monitors. Features exceptional tolerance to base drive and collector current load variations resulting in a very low worst case dissipation.QUICK REFERENCE DATASYMBOL PARAMETERCONDITIONS TYP.MAX.UNIT V CESM Collector-emitter voltage peak value V BE = 0 V-1500V V CEO Collector-emitter voltage (open base)-800V I C Collector current (DC)-12A I CM Collector current peak value -30A P tot Total power dissipationT mb ≤ 25 ˚C-125W V CEsat Collector-emitter saturation voltage I C = 9.0 A; I B = 2.25A - 3.0V I Csat Collector saturation current f= 16 kHz 8.0-A f= 70 kHz7.5-A t fFall timeI Csat = 9.0 A; f = 16 kHz t.b.f t.b.f µs I Csat = 7.5 A; f = 70 kHzt.b.ft.b.fµsPINNING - SOT430PIN CONFIGURATION SYMBOLLIMITING VALUESLimiting values in accordance with the Absolute Maximum Rating System (IEC 134)SYMBOL PARAMETERCONDITIONS MIN.MAX.UNIT V CESM Collector-emitter voltage peak value V BE = 0 V-1500V V CEO Collector-emitter voltage (open base)-800V I C Collector current (DC)-12A I CM Collector current peak value -30A I B Base current (DC)-8A I BM Base current peak value-12A -I BM Reverse base current peak value 1-7A P tot Total power dissipation T mb ≤ 25 ˚C-125W T stg Storage temperature -55150˚C T jJunction temperature-150˚C1 Turn-off current.Philips Semiconductors Objective specificationSilicon Diffused Power Transistor BU4525ALTHERMAL RESISTANCESSYMBOL PARAMETERCONDITIONS TYP.MAX.UNIT R th j-mb Junction to mounting base -- 1.0K/W R th j-aJunction to ambientin free air45-K/WSTATIC CHARACTERISTICST hs = 25 ˚C unless otherwise specified SYMBOL PARAMETERCONDITIONSMIN.TYP.MAX.UNIT I CES Collector cut-off current 2V BE = 0 V; V CE = V CESMmax -- 1.0mA I CES V BE = 0 V; V CE = V CESMmax ;-- 2.0mA T j = 125 ˚CI EBO Emitter cut-off currentV BE = 7.5 V; I C = 0 A -- 1.0mA BV EBO Emitter-base breakdown voltage I B = 1 mA7.513.5-V V CEOsust Collector-emitter sustaining voltage I B = 0 A; I C = 100 mA;800--V L = 25 mHV CEsat Collector-emitter saturation voltage I C = 9.0 A;I B = 2.25 A;-- 3.0V V BEsat Base-emitter saturation voltage I C = 9.0 A;I B = 2.25 A;t.b.f - 1.1Vh FE DC current gainI C = 1A; V CE = 5 V -t.b.f -h FEI C = 9 A; V CE = 5 V4.25.356.5DYNAMIC CHARACTERISTICST hs = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONSTYP.MAX.UNIT C c Collector capacitance I E = 0 A; V CB = 10 V; f = 1 MHz 145-pF Switching times (16 kHz line I Csat = 9.0 A;I B1 = 1.8 A;deflection circuit)(I B2 = -4.5 A)t s Turn-off storage time t.b.f t.b.f µs t fTurn-off fall timet.b.ft.b.fµsSwitching times (70kHz line I Csat = 7.5 A;I B1 = 1.5 A deflection circuit)(I B2 = -4.5 A)t s Turn-off storage time t.b.f t.b.f µs t fTurn-off fall timet.b.ft.b.fµs2 Measured with half sine-wave voltage (curve tracer).Philips Semiconductors Objective specification Silicon Diffused Power Transistor BU4525ALMECHANICAL DATAPhilips Semiconductors Objective specification Silicon Diffused Power Transistor BU4525ALDEFINITIONSData sheet statusObjective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.Limiting valuesLimiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections ofthis specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application informationWhere application information is given, it is advisory and does not form part of the specification.© Philips Electronics N.V. 1998All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.LIFE SUPPORT APPLICATIONSThese products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.。
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
– Multi-bit Delta Sigma Architecture
– Very Low 64Fs Oversampling Clock Reduces Power Consumption
Low Power Operation
Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved)
DECEMBER '06 DS680A1
System Features
12, 24, and 27 MHz Master Clock Support in Addition to Typical Audio Clock Rates
HPF ALC
Multi-bit
ΔΣ DAC
Control Port
Serial Audio 3; Stereo/Mono
- Full-Bridge
+ -
Speaker
Outputs
Class D Amps
Left HP/Line Output
Ground-Centered Amps
– 2 x 23 mW Into 16 Ω @ 1.8 V – 2 x 44 mW Into 16 Ω @ 2.5 V
(Features continued on page 2)
+1.65 V to +2.63 V Analog Supply
Summing Programmable Gain Amps
Shutdown Headphone/Speaker Detection Input Pop and Click Suppression
Applications
Digital Voice Recorders, Digital Cameras & Camcorders
PDA’s Personal Media Players Portable Game Consoles
Σ
Left
1 2
Inputs
3 4
Right
1 2
Inputs
3 4
Multi-bit
ΔΣ ADC
Σ
+16 to +32 dB Diff./ S.E. MIC Pre-Amps MIC Bias
+1.65 V to +2.63 V Digital Supply
+1.60 V to +5.25 V Battery
-VHP
+VHP
Charge Pump
Right HP/Line Output
Speaker/HP Switch
+1.65 V to +2.63 V Headphone Supply
Selectable Bias Voltage
+1.65 V to +3.47 V Interface Supply
I2C Control
Reset
Serial Audio Input/Output
+1.65 V to +2.63 V Analog Supply
Advance Product Information
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
– 4:1 Analog Input MUX – Analog Input Mixing – Analog Passthru with Volume Control – Analog Programmable Gain Amplifier (PGA)
Programmable Automatic Level Control (ALC)
Stereo Headphone Amplifier
Ground Centered Outputs
– No DC-Blocking Capacitors Required – Integrated Negative Voltage Regulator
High Power Output at -75 dB THD+N
Analog & Digital Routing/Mixes:
– Line/Headphone Out = Analog In (ADC Bypassed)
– Line/Headphone/Speaker Out = ADC + Digital In
– Digital Out = ADC + Digital In
Battery Level Monitoring & Compensation
Temperature Monitor ALC
Beep
Pulse-Width Modulator
(PWM)
Volume, Mono Swap, Mix
Mono mix, Limiter, Bass, Treble Adjust
– Stereo Analog Passthru: 10 mW @ 1.8 V
– Stereo Playback: 14 mW @ 1.8 V
– Stereo Rec. and Playback: 23 mW @ 1.8 V
Variable Power Supplies
– 1.8 V to 2.5 V Digital & Analog
The ADC input path allows independent channel control of a number of features. Input summing amplifiers mix and select line-level and/or microphone level inputs for each channel. The microphone input path includes a selectable programmable-gain pre-amplifier stage and a low noise MIC bias voltage supply. A PGA is available for line or microphone inputs and provides analog gain with soft ramp and zero cross transitions. The ADC also features a digital volume control with soft ramp transitions. A programmable ALC and Noise Gate monitor the input signals and adjust the volume levels appropriately. To conserve power, the ADC may be bypassed while still allowing full analog volume control.
The DAC output path includes a digital signal processing engine with various fixed function controls.Tone Control provides bass and treble adjustment of four selectable corner frequencies. The Digital Mixer provides independent volume control for both the ADC output and PCM input signal paths, as well as a master volume control. Digital Volume controls may be configured to change on soft ramp transitions while the analog controls can be configured to occur on every zero crossing. The DAC also includes de-emphasis, limiting functions and a BEEP generator delivering tones selectable across a range of two full octaves.
Amplifiers – Programmable, Low Noise MIC Bias Levels
Digital Signal Processing Engine
– Bass & Treble Tone Control, De-Emphasis
– Master Vol. and Independent PCM SDIN + ADC SDOUT Mix Volume Control
CS42L52
Low Power, Stereo CODEC w/Headphone & Speaker Amps
Stereo CODEC
High Performance Stereo ADC & DAC
– 98 dB Dynamic Range (A-wtd) – -88 dB THD+N
Flexible Stereo Analog Input Architecture
– Noise Gate for Noise Suppression – Programmable Threshold & Attack/Release