Verilog比较好的一篇教程
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Verilog
Matt Tsai
• Verilog Application • Introduction to Cadence Simulators • Sample Design • Lexical Conventions in Verilog • Verilog Data Type and Logic System • Structural Modeling • Modeling Delay • Using Compiler Controls • Verilog Operators • Behavioral Modeling • Support for Verification • Introduction to Using a Verilog Test Bench • Modeling Memories • High Level Constructs in Verilog • User Defined Primitives • Annotating SDF Timing
• Verilog-XL simulator:Interpretive
– 不會有暫存檔(1)(2)(3)一次完成
• NC Verilog simulator:compiled simulation
– ncviog(1) ncelab(2) ncsim(3) – 當project很大時,只針對要修改部分重新
• IEEE 1364-1995, IEEE 1364-2001 • Behavioral: 無法看出電路特性 • RTL:可以看出電路特性 (logic synthesis) • Structural: bulit-in primitives,UDPs
– RTL and structural 可混合描述
endmodule
Waveform database(SHM and VCD)
$shm_open(“lab.shm”); $shm_probe(); $shm_close; $shm_save;
$dumpfile(‘lab.dump”); $dumpvars(); $dumpflush; $dumpoff; $dumppon; $dumplinit(<file size>); $dumpall;
wire out•; Initial //Instantiat•e maolwdualeyss MUX2_1 mux(out,a,b,sel);
Template module testbench
//Data type declaration
//Instantiate modules
//Apply stimulus
initial begin $shm_open(“lab.shm”); $shm_probe(“AS”);
initial begin $dumpfile(“lab.dump”); $dumpvars();
end
end
mo•dulTe etessttbbeennchch----behavioral //Data type declaration r•egPa,rbo,scele;dural block
• Module path delay
– Specify
– (A=>O)=2;
– (A=>O)=3;
– (A=>O)=1;
– //state dependent path delay
– if(a)
–
(b=>x)=(5:6:7);
– //state dependent delay 無else的語法
– Endspecify
• Behavioral 和 RTL的區分要靠經驗
{Behavioral} for( ; ; )
for( ; ; ) ...
{RTL} always @(sl or a or b)
if(!sl) out=a;
else out=b;
• Compilation(1) Initialization(2) Simulation(3) 3-9
compile即可 – VHDL and Verilog可以作整合
• Simulation algorithms 3-3
– Time-based(SPICE) – Event-based(Verilog-XL and NC Verilog) – Cycle-based(依照clock,更大的time-based)
• verilog mux.v testbench.v • verilog –f run.f 3-17
run.f mux.v testbench.v
• The waveform display tool---signalscan
– Read data from database
3-27 • SHM database(非IEEE standard,only Cadence) 4-26 • VCD(Value Change Dump) database(IEEE standard)
initial begin
//Apply stimulus
a=0;b=0;sel=0; #5 b=0; #5 b=1;sel=1;
//Display results endmodule
#5a=1;
4-15
$finish;
end
//Display results
initial
$monitor($time,,”out=%b a=%b sel=%b”,out,a,b,sel);
• `include global.v
• verilog mux.v global.v
• Hale Waihona Puke Baiduimescale 1ns/100 ps
• Lumped delay 8-3
– nor n1(net1,a,b); – or #3 o1(out,c,net1);
• Distributed delay
– nor #2 n1(net1,a,b); – or #1 o1(out,c,net1);
Inside code Command line
8-16 specify block
Selecting simulation delay mode
• Command line
Matt Tsai
• Verilog Application • Introduction to Cadence Simulators • Sample Design • Lexical Conventions in Verilog • Verilog Data Type and Logic System • Structural Modeling • Modeling Delay • Using Compiler Controls • Verilog Operators • Behavioral Modeling • Support for Verification • Introduction to Using a Verilog Test Bench • Modeling Memories • High Level Constructs in Verilog • User Defined Primitives • Annotating SDF Timing
• Verilog-XL simulator:Interpretive
– 不會有暫存檔(1)(2)(3)一次完成
• NC Verilog simulator:compiled simulation
– ncviog(1) ncelab(2) ncsim(3) – 當project很大時,只針對要修改部分重新
• IEEE 1364-1995, IEEE 1364-2001 • Behavioral: 無法看出電路特性 • RTL:可以看出電路特性 (logic synthesis) • Structural: bulit-in primitives,UDPs
– RTL and structural 可混合描述
endmodule
Waveform database(SHM and VCD)
$shm_open(“lab.shm”); $shm_probe(); $shm_close; $shm_save;
$dumpfile(‘lab.dump”); $dumpvars(); $dumpflush; $dumpoff; $dumppon; $dumplinit(<file size>); $dumpall;
wire out•; Initial //Instantiat•e maolwdualeyss MUX2_1 mux(out,a,b,sel);
Template module testbench
//Data type declaration
//Instantiate modules
//Apply stimulus
initial begin $shm_open(“lab.shm”); $shm_probe(“AS”);
initial begin $dumpfile(“lab.dump”); $dumpvars();
end
end
mo•dulTe etessttbbeennchch----behavioral //Data type declaration r•egPa,rbo,scele;dural block
• Module path delay
– Specify
– (A=>O)=2;
– (A=>O)=3;
– (A=>O)=1;
– //state dependent path delay
– if(a)
–
(b=>x)=(5:6:7);
– //state dependent delay 無else的語法
– Endspecify
• Behavioral 和 RTL的區分要靠經驗
{Behavioral} for( ; ; )
for( ; ; ) ...
{RTL} always @(sl or a or b)
if(!sl) out=a;
else out=b;
• Compilation(1) Initialization(2) Simulation(3) 3-9
compile即可 – VHDL and Verilog可以作整合
• Simulation algorithms 3-3
– Time-based(SPICE) – Event-based(Verilog-XL and NC Verilog) – Cycle-based(依照clock,更大的time-based)
• verilog mux.v testbench.v • verilog –f run.f 3-17
run.f mux.v testbench.v
• The waveform display tool---signalscan
– Read data from database
3-27 • SHM database(非IEEE standard,only Cadence) 4-26 • VCD(Value Change Dump) database(IEEE standard)
initial begin
//Apply stimulus
a=0;b=0;sel=0; #5 b=0; #5 b=1;sel=1;
//Display results endmodule
#5a=1;
4-15
$finish;
end
//Display results
initial
$monitor($time,,”out=%b a=%b sel=%b”,out,a,b,sel);
• `include global.v
• verilog mux.v global.v
• Hale Waihona Puke Baiduimescale 1ns/100 ps
• Lumped delay 8-3
– nor n1(net1,a,b); – or #3 o1(out,c,net1);
• Distributed delay
– nor #2 n1(net1,a,b); – or #1 o1(out,c,net1);
Inside code Command line
8-16 specify block
Selecting simulation delay mode
• Command line