verilog FPGA 状态机描述

if ( rdy) next_state = idle ; else next_state = read; end write: begin {oe,we} = 2’b01; if ( rdy) next_state = idle ; //combinational block else always @(reset or present_state or rdy or r_w) next_state = write ; begin end case (present_state) default: begin idle: begin {oe,we} = 2’b00; {oe,we} = 2’b00; next_state = 4’bx ; if ( rdy) end next_state = decision ; endcase else end // end always begin3-2 next_state = idle ; endmodule; end
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3.5 状态机描述方法
Example: 一段式状态机 描述方法
module Mealy_state_machine (clock, reset, A, K2, K1 ); input clock, reset, A; output K2, K1; reg K2, K1; reg [1,0] state; parameter idle =2’b00, start =2’b01; ’ ’ stop: begin stop =2’b10, clear =2’11; if ( A ) begin always @(posedge clock or negedge reset) state <= clear; if (!reset) K2 <= 1; begin end state <= idle; {K2,K1} <= 2’b00; else state <= stop; end end else case (state) clear: begin idle: begin if ( !A) begin if ( A) begin state <= idle ; state <= start ; {K2,K1} <= 2’b01; K1 <= 0; end end else state <= clear ; else end state <= idle ; endcase end endmodule start: begin if ( !A) state <= stop ; else state <= start ; end
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Example: 两段式状态机 描述方法（推荐） 描述方法（推荐）
Outputs State idle decision write read oe 0来自百度文库0 0 1 we 0 0 1 0
write 01
Reset
idle 00
rdy r_w
rdy
decision 00
rdy r_w
read 10
rdy
rdy
decision: begin {oe,we} = 2’b00; if ( r_w) next_state = read ; else next_state = write ; end read: begin {oe,we} = 2’b10;
module state_machine (clock, reset, rdy, r_w, oe, we); input clock, reset; input rdy, r_w; output oe,we; reg oe,we; reg [3,0] present_state, next_state; parameter idle =4’b0001, decision=4’b0010; read=4’b0100, write=4’1000; // sequential state transition always @ (posedge clock or negedge reset ) if ( !reset ) present_state <= idle ; else present_state <= next_state ;
两段式状态机描述使用task 推荐编码） task（ Example: 两段式状态机描述使用task（推荐编码）
module state_machine (clock, reset, rdy, r_w, oe, we); input clock, reset; input rdy, r_w; output oe,we; reg oe,we; reg [3,0] present_state, next_state; parameter idle =4’b0001, decision=4’b0010; read=4’b0100, write=4’1000; // sequential state transition always @ (posedge clock or negedge reset ) if ( ! reset ) present_state <= idle ; else present_state <= next_state ; read: begin read_output;
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三段式状态机描述（推荐编码） Example: 三段式状态机描述（推荐编码）
module state_machine (clock, reset, rdy, r_w, oe, we); input clock, reset; input rdy, r_w; output oe,we; reg oe,we; reg [3,0] present_state, next_state; parameter idle =4’b0001, decision=4’b0010; read=4’b0100, write=4’1000; // sequential state transition always @ (posedge clock or negedge reset ) if ( ! reset ) present_state <= idle ; else present_state <= next_state ; read: begin if ( rdy) next_state = idle ; else next_state = read; end write: begin if ( rdy) next_state = idle ; else next_state = write ; end default: begin next_state = 4’bx ; end endcase //combinational block always @(reset or present_state or rdy or r_w) end //end always begin begin //Registered output case (present_state) always @ (posedge clock or idle: begin negedge reset ) if ( rdy) if ( ! reset ) next_state = decision ; {oe,we} <= 2’b00 else else next_state = idle ; begin end case(next_state) decision: begin idle: {oe,we} <= 2’b00 ; if ( r_w) decision: {oe,we} <= 2’b00; next_state = read ; read: {oe,we} <= 2’b10; else write: {oe,we} <= 2’b01; next_state = write ; endcase end end endmodule;
if ( rdy) next_state = idle ; else next_state = read; end write: begin write_output; if ( rdy) next_state = idle ; else next_state = write ; end default: begin idle_output; //combinational block next_state = 4’bx ; always @(reset or present_state or rdy or r_w) end begin endcase case(present_state) end //end always begin idle: begin idle_output; //output tasks if ( rdy) task idle_output; next_state = decision ; {oe,we} = 2’b00; else endtask next_state = idle ; task decision_output; end decision: begin {oe,we} = 2’b00; endtask decision_output; task read_output; if ( r_w) {oe,we} = 2’b10; next_state = read ; endtask else next_state = write ; task write_output; end {oe,we} = 2’b01; endtask endmodule;