systemverilog 实验

INTRODUCTIONIn this tutorial, we will verify the Switch RTL core. Following are the steps we follow to verify the Switch RTL core.1) Understand the specification2) Developing Verification Plan3) Building the Verification Environment. We will build the Environment in Multiple phases, so it will be easy for you to learn step by step.Phase 1) We will develop the testcase and interfaces, and integrate them in these with the DUT in top module.Phase 2) We will Develop the Environment class.Phase 3) We will develop reset and configuration methods in Environment class. Then using these methods, we will reset the DUT and configure the port address.Phase 4) We will develop a packet class based on the stimulus plan. We will also write a small code to test the packet class implementation.Phase 5) We will develop a driver class. Packets are generated and sent to DUT using driver.Phase 6) We will develop receiver class. Receiver collects the packets coming from the output port of the DUT.Phase 7) We will develop scoreboard class which does the comparison of the expected packet with the actual packet received from the DUT.Phase 8) We will develop coverage class based on the coverage plan.Phase 9) In this phase , we will write testcases and analyze the coverage report.SPECIFICATIONSwitch Specification:where the packet is driven out.Packet Format:Packet contains 3 parts. They are header, data and frame check sequence.Packet width is 8 bits and the length of the packet can be between 4 bytes to 259 bytes.Packet Header:Packet header contains three fields DA, SA and length.DA: Destination address of the packet is of 8 bits. The switch drives the packet to respective ports based on this destination address of the packets. Each output port has 8-bit unique port address. If the destination address of the packet matches the port address, then switch drives the packet to the output port.SA: Source address of the packet from where it originate. It is 8 bits.Length: Length of the data is of 8 bits and from 0 to 255. Length is measured in terms of bytes.If Length = 0, it means data length is 0 bytesIf Length = 1, it means data length is 1 bytesIf Length = 2, it means data length is 2 bytesIf Length = 255, it means data length is 255 bytesData: Data should be in terms of bytes and can take anything.FCS: Frame check sequenceThis field contains the security check of the packet. It is calculated over the header and data.Configuration:Switch has four output ports. These output ports address have to be configured to a unique address. Switch matches the DA field of the packet with this configured port address and sends the packet on to that port. Switch contains a memory. This memory has 4 locations, each can store 8 bits. To configure the switch port address, memory write operation has to be done using memory interface. Memory address (0,1,2,3) contains the address of port(0,1,2,3) respectively.Interface Specification:The Switch has one input Interface, from where the packet enters and 4 output interfaces from where the packet comes out and one memory interface, through the port address can be configured. Switch also has a clock and asynchronous reset signal.Memory Interface:Through memory interfaced output port address are configured. It accepts 8 bit data to be written to memory. It has 8 bit address inputs. Address 0,1,2,3 contains the address of the port 0,1,2,3 respectively.There are 4 input signals to memory interface. They areinput mem_en;input mem_rd_wr;input[1:0] mem_add;input[7:0] mem_data;All the signals are active high and are synchronous to the positive edge of clock signal. To configure a port address,1. Assert the mem_en signal.2. Asser the mem_rd_wr signal.3. Drive the port number (0 or 1 or 2 or 3) on the mem_add signal4. Drive the 8 bit port address on to mem_data signal.Input PortPackets are sent into the switch using input port.All the signals are active high and are synchronous to the positive edge of clock signal. input port has 2input signals. They areinput[7:0]data;input data_status;To send the packet in to switch,1. Assert the data_status signal.2. Send the packet on the data signal byte by byte.3. After sending all the data bytes, deassert the data_status signal.4. There should be at least 3 clock cycles difference between packets.Output Portport_* signal after one clock cycle.VERIFICATION PLANOverviewThis Document describes the Verification Plan for Switch. The Verification Plan is based on System Verilog Hardware Verification Language. The methodology used for Verification is Constraint random coverage driven verification.Feature ExtractionThis section contains list of all the features to be verified.1)ID: ConfigurationDescription: Configure all the 4 port address with unique values.2)ID: Packet DADescription: DA field of packet should be any of the port address. All the 4 port address should be used.3)ID : Packet payloadDescription: Length can be from 0 to 255. Send packets with all the lengths.4)ID: LengthDescription:Length field contains length of the payload.Send Packet with correct length field and incorrect length fields.5)ID: FCSDescription:Good FCS: Send packet with good FCS.Bad FCS: Send packet with corrupted FCS.Stimulus Generation Plan1) Packet DA: Generate packet DA with the configured address.2) Payload length: generate payload length ranging from 2 to 255.3) Correct or Incorrect Length field.4) Generate good and bad FCS.Coverage Plan1) Cover all the port address configurations.2) Cover all the packet lengths.3) Cover all correct and incorrect length fields.4) Cover good and bad FCS.5) Cover all the above combinations.Verification EnvironmentPHASE 1 TOPIn phase 1,1) We will write SystemVerilog Interfaces for input port, output port and memory port.2) We will write Top module where testcase and DUT instances are done.3) DUT and TestBench interfaces are connected in top module.4) Clock is generator in top module.NOTE: In every file you will see the syntax`ifndef GUARD_*`endif GUARD_*InterfacesIn the interface.sv file, declare the 3 interfaces in the following way.All the interfaces has clock as input.All the signals in interface are logic type.All the signals are synchronized to clock except reset in clocking block.Signal directional w.r.t TestBench is specified with modport.`ifndef GUARD_INTERFACE`define GUARD_INTERFACE//////////////////////////////////////////// Interface declaration for the memory/////////////////////////////////////////////interface mem_interface(input bit clock);logic[7:0] mem_data;logic[1:0] mem_add;logic mem_en;logic mem_rd_wr;clocking cb@(posedge clock);default input#1output#1;output mem_data;output mem_add;output mem_en;output mem_rd_wr;endclockingmodport MEM(clocking cb,input clock);endinterface////////////////////////////////////////////// Interface for the input side of switch.//// Reset signal is also passed hear. ////////////////////////////////////////////// interface input_interface(input bit clock);logic data_status;logic[7:0] data_in;logic reset;clocking cb@(posedge clock);default input#1output#1;output data_status;output data_in;endclockingmodport IP(clocking cb,output reset,input clock); endinterface///////////////////////////////////////////////// // Interface for the output side of the switch.//// output_interface is for only one output port/////////////////////////////////////////////////// interface output_interface(input bit clock);logic[7:0] data_out;logic ready;logic read;clocking cb@(posedge clock);default input#1output#1;input data_out;input ready;output read;endclockingmodport OP(clocking cb,input clock);endinterface//////////////////////////////////////////////////`endifTestcaseTestcase is a program block which provides an entry point for the test and creates a scope that encapsulates program-wide data. Currently this is an empty testcase which just ends the simulation after 100 time units. Program block contains all the above declared interfaces as arguments. This testcase has initial and final blocks.`ifndef GUARD_TESTCASE`define GUARD_TESTCASEprogram testcase(mem_interface.MEM mem_intf,input_interface.IP input_intf,output_i nterface.OP output_intf[4]);initialbegin$display(" ******************* Start of testcase ****************");#1000;endfinal$display(" ******************** End of testcase *****************");endprogram`endifTop ModuleThe modules that are included in the source text but are not instantiated are called top modules. This module is the highest scope of modules. Generally this module is named as "top" and referenced as "top module". Module name can be anything.Do the following in the top module:1)Generate the clock signal.bit Clock;initialforever#10 Clock =~Clock;2)Do the instances of memory interface.mem_interface mem_intf(Clock);3)Do the instances of input interface.input_interface input_intf(Clock);4)There are 4 output ports. So do 4 instances of output_interface.output_interface output_intf[4](Clock);5)Do the instance of testcase and pass all the above declared interfaces.testcase TC(mem_intf,input_intf,output_intf);6)Do the instance of DUT.switch DUT7)Connect all the interfaces and DUT. The design which we have taken is in verilog. So Verilog DUT instance is connected signal by signal.switch DUT(.clk(Clock),.reset(input_intf.reset),.data_status(input_intf.data_status),.data(input_intf.data_in),.port0(output_intf[0].data_out),.port1(output_intf[1].data_out),.port2(output_intf[2].data_out),.port3(output_intf[3].data_out),.ready_0(output_intf[0].ready),.ready_1(output_intf[1].ready),.ready_2(output_intf[2].ready),.ready_3(output_intf[3].ready),.read_0(output_intf[0].read),.read_1(output_intf[1].read),.read_2(output_intf[2].read),.read_3(output_intf[3].read),.mem_en(mem_intf.mem_en),.mem_rd_wr(mem_intf.mem_rd_wr),.mem_add(mem_intf.mem_add),.mem_data(mem_intf.mem_data));Top Module Source Code:`ifndef GUARD_TOP`define GUARD_TOPmodule top();///////////////////////////////////////////////////// // Clock Declaration and Generation /////////////////////////////////////////////////////// bit Clock;initialforever#10 Clock =~Clock;///////////////////////////////////////////////////// // Memory interface instance /////////////////////////////////////////////////////// mem_interface mem_intf(Clock);///////////////////////////////////////////////////// // Input interface instance /////////////////////////////////////////////////////// input_interface input_intf(Clock);///////////////////////////////////////////////////// // output interface instance /////////////////////////////////////////////////////// output_interface output_intf[4](Clock);///////////////////////////////////////////////////// // Program block Testcase instance /////////////////////////////////////////////////////// testcase TC(mem_intf,input_intf,output_intf);///////////////////////////////////////////////////// // DUT instance and signal connection ///////////////////////////////////////////////////////switch DUT(.clk(Clock),.reset(input_intf.reset),.data_status(input_intf.data_status),.data(input_intf.data_in),.port0(output_intf[0].data_out),.port1(output_intf[1].data_out),.port2(output_intf[2].data_out),.port3(output_intf[3].data_out),.ready_0(output_intf[0].ready),.ready_1(output_intf[1].ready),.ready_2(output_intf[2].ready),.ready_3(output_intf[3].ready),.read_0(output_intf[0].read),.read_1(output_intf[1].read),.read_2(output_intf[2].read),.read_3(output_intf[3].read),.mem_en(mem_intf.mem_en),.mem_rd_wr(mem_intf.mem_rd_wr), .mem_add(mem_intf.mem_add),.mem_data(mem_intf.mem_data)); endmodule`endif(S)Run the simulation:PHASE 2 ENVIRONMENTIn this phase, we will writeEnvironment class.Virtual interface declaration.Defining Environment class constructor.Defining required methods for execution. Currently these methods will not be implemented in this phase.All the above are done in Environment.sv file.We will write a testcase using the above define environment class in testcase.sv file.Environment Class:The class is a base class used to implement verification environments. Testcase contains the instance of the environment class and has access to all the public declaration of environment class.All methods are declared as virtual methods. In environment class, we will formalize the simulation steps using virtual methods. The methods are used to control the execution of the simulation.Following are the methods which are going to be defined in environment class.1) new() : In constructor method, we will connect the virtual interfaces which are passed as argument to the virtual interfaces to those which are declared in environment class.2) build(): In this method , all the objects like driver, monitor etc are constructed. Currently this method is empty as we did not develop any other component.3) reset(): in this method we will reset the DUT.4) cfg_dut(): In this method, we will configure the DUT output port address.5) start(): in this method, we will call the methods which are declared in the othercomponents like driver and monitor.6) wait_for_end(): this method is used to wait for the end of the simulation. Waits until all the required operations in other components are done.7) report(): This method is used to print the TestPass and TestFail status of the simulation, based on the error count..8) run(): This method calls all the above declared methods in a sequence order. The testcase calls this method, to start the simulation.We are not implementing build(), reset(), cfg_dut() , strat() and report() methods in this phase.Connecting the virtual interfaces of Environment class to the physical interfaces of top module.Verification environment contains the declarations of the virtual interfaces. Virtual interfaces are just a handles(like pointers). When a virtual interface is declared, it only creats a handle. It doesnot creat a real interface.Constructor method should be declared with virtual interface as arguments, so that when the object is created in testcase, new() method can pass the interfaces in to environment class where they are assigned to the local virtual interface handle. With this, the Environment class virtual interfaces are pointed to the physical interfaces which are declared in the top module.Declare virtual interfaces in Environment class.virtual mem_interface.MEM mem_intf ;virtual input_interface.IP input_intf ;virtual output_interface.OP output_intf[4];The construction of Environment class is declared with virtual interface as arguments.function new(virtual mem_interface.MEM mem_intf_new ,virtual input_interface.IP input_intf_new ,virtual output_interface.OP output_intf_new[4]);In constructor methods, the interfaces which are arguments are connected to the virtual interfaces of environment class.this.mem_intf = mem_intf_new ;this.input_intf = input_intf_new ;this.output_intf = output_intf_new ;Run :The run() method is called from the testcase to start the simulation. run() method calls all the methods which are defined in the Environment class.task run();$display(" %0d : Environment : start of run() method",$time); build();reset();cfg_dut();start();wait_for_end();report();$display(" %0d : Environment : end of run() method",$time); endtask: runEnvironment Class Source Code:`ifndef GUARD_ENV`define GUARD_ENVclass Environment ;virtual mem_interface.MEM mem_intf ;virtual input_interface.IP input_intf ;virtual output_interface.OP output_intf[4];function new(virtual mem_interface.MEM mem_intf_new ,virtual input_interface.IP input_intf_new ,virtual output_interface.OP output_intf_new[4]);this.mem_intf = mem_intf_new ;this.input_intf = input_intf_new ;this.output_intf = output_intf_new ;$display(" %0d : Environment : created env object",$time); endfunction:newfunction void build();$display(" %0d : Environment : start of build() method",$time); $display(" %0d : Environment : end of build() method",$time); endfunction:buildtask reset();$display(" %0d : Environment : start of reset() method",$time); $display(" %0d : Environment : end of reset() method",$time); endtask: resettask cfg_dut();$display(" %0d : Environment : start of cfg_dut() method",$time); $display(" %0d : Environment : end of cfg_dut() method",$time); endtask: cfg_duttask start();$display(" %0d : Environment : start of start() method",$time); $display(" %0d : Environment : end of start() method",$time); endtask:starttask wait_for_end();$display(" %0d : Environment : start of wait_for_end() method",$time); $display(" %0d : Environment : end of wait_for_end() method",$time); endtask: wait_for_endtask run();$display(" %0d : Environment : start of run() method",$time);build();reset();cfg_dut();start();wait_for_end();report();$display(" %0d : Environment : end of run() method",$time);endtask: runtask report();endtask: reportendclass`endifWe will create a file Global.sv for global requirement. In this file, define all the port address as macros in this file. Define a variable error as integer to keep track the number of errors occurred during the simulation.`ifndef GUARD_GLOBALS`define GUARD_GLOBALS`define P08'h00`define P18'h11`define P28'h22`define P38'h33int error =0;int num_of_pkts =10;`endifNow we will update the testcase. Take an instance of the Environment class and call the run method of the Environment class.`ifndef GUARD_TESTCASE`define GUARD_TESTCASEprogram testcase(mem_interface.MEM mem_intf,input_interface.IP input_intf,output_interface.OP output_intf[4]);Environment env;initialbegin$display(" ******************* Start of testcase ****************");env =new(mem_intf,input_intf,output_intf);env.run();#1000;endfinal$display(" ******************** End of testcase *****************");endprogram`endif(S)Run the simulation:(S)Log report after the simulation:******************* Start of testcase ****************0 : Environemnt : created env object0 : Environemnt : start of run() method0 : Environemnt : start of build() method0 : Environemnt : end of build() method0 : Environemnt : start of reset() method0 : Environemnt : end of reset() method0 : Environemnt : start of cfg_dut() method0 : Environemnt : end of cfg_dut() method0 : Environemnt : start of start() method0 : Environemnt : end of start() method0 : Environemnt : start of wait_for_end() method 0 : Environemnt : end of wait_for_end() method 0 : Environemnt : end of run() method******************** End of testcase *****************PHASE 3 RESETIn this phase we will reset and configure the DUT.The Environment class has reset() method which contains the logic to reset the DUT and cfg_dut() method which contains the logic to configure the DUT port address.NOTE: Clocking block signals can be driven only using a non-blocking assignment.Define the reset() method.1) Set all the DUT input signals to a known state.mem_intf.cb.mem_data <=0;mem_intf.cb.mem_add <=0;mem_intf.cb.mem_en <=0;mem_intf.cb.mem_rd_wr <=0;input_intf.cb.data_in <=0;input_intf.cb.data_status <=0;output_intf[0].cb.read <=0;output_intf[1].cb.read <=0;output_intf[2].cb.read <=0;output_intf[3].cb.read <=0;2) Reset the DUT.// Reset the DUTinput_intf.reset <=1;repeat(4)@ input_intf.clock;input_intf.reset <=0;3) Updated the cfg_dut method.task cfg_dut();$display(" %0d : Environment : start of cfg_dut() method",$time);mem_intf.cb.mem_en <=1;@(posedge mem_intf.clock);mem_intf.cb.mem_rd_wr <=1;@(posedge mem_intf.clock);mem_intf.cb.mem_add <=8'h0;mem_intf.cb.mem_data <=`P0;$display(" %0d : Environment : Port 0 Address %h ",$time,`P0);@(posedge mem_intf.clock);mem_intf.cb.mem_add <=8'h1;mem_intf.cb.mem_data <=`P1;$display(" %0d : Environment : Port 1 Address %h ",$time,`P1);@(posedge mem_intf.clock);mem_intf.cb.mem_add <=8'h2;mem_intf.cb.mem_data <=`P2;$display(" %0d : Environment : Port 2 Address %h ",$time,`P2);@(posedge mem_intf.clock);mem_intf.cb.mem_add <=8'h3;mem_intf.cb.mem_data <=`P3;$display(" %0d : Environment : Port 3 Address %h ",$time,`P3);@(posedge mem_intf.clock);mem_intf.cb.mem_en <=0;mem_intf.cb.mem_rd_wr <=0;mem_intf.cb.mem_add <=0;mem_intf.cb.mem_data <=0;$display(" %0d : Environment : end of cfg_dut() method",$time); endtask: cfg_dut(4) In wait_for_end method, wait for some clock cycles.task wait_for_end();$display(" %0d : Environment : start of wait_for_end() method",$time); repeat(10000)@(input_intf.clock);$display(" %0d : Environment : end of wait_for_end() method",$time); endtask: wait_for_end(S)Run the simulation:(S)Log File report******************* Start of testcase ****************0 : Environment : created env object0 : Environment : start of run() method0 : Environment : start of build() method0 : Environment : end of build() method0 : Environment : start of reset() method40 : Environment : end of reset() method40 : Environment : start of cfg_dut() method70 : Environment : Port 0 Address 0090 : Environment : Port 1 Address 11110 : Environment : Port 2 Address 22130 : Environment : Port 3 Address 33150 : Environment : end of cfg_dut() method150 : Environment : start of start() method150 : Environment : end of start() method150 : Environment : start of wait_for_end() method100150 : Environment : end of wait_for_end() method100150 : Environment : end of run() method******************** End of testcase *****************PHASE 4 PACKETIn this Phase, We will define a packet and then test it whether it is generating as expected.Packet is modeled using class. Packet class should be able to generate all possible packet types randomly. Packet class should also implement required methods like packing(), unpacking(), compare() and display() methods.We will write the packet class in packet.sv file. Packet class variables and constraints have been derived from stimulus generation plan.Revisit Stimulus Generation Plan1) Packet DA: Generate packet DA with the configured address.2) Payload length: generate payload length ranging from 2 to 255.3) Correct or Incorrect Length field.4) Generate good and bad FCS.1) Declare FCS types as enumerated data types. Name members as GOOD_FCS and BAD_FCS.typedef enum{GOOD_FCS,BAD_FCS} fcs_kind_t;2) Declare the length type as enumerated data type. Name members as GOOD_LENGTH and BAD_LENGTH.typedef enum{GOOD_LENGTH,BAD_LENGTH} length_kind_t;3) Declare the length type and fcs type variables as rand.rand fcs_kind_t fcs_kind;rand length_kind_t length_kind;4) Declare the packet field as rand. All fields are bit data types. All fields are 8 bit packet array. Declare the payload as dynamic array.rand bit[7:0] length;rand bit[7:0] da;rand bit[7:0] sa;rand byte data[];//Payload using Dynamic array,size is generated on the flyrand byte fcs;5) Constraint the DA field to be any one of the configured address.constraint address_c { da inside{`P0,`P1,`P2,`P3};}6) Constrain the payload dynamic array size to between 1 to 255.constraint payload_size_c {data.size inside{[1:255]};}7) Constrain the payload length to the length field based on the length type.constraint length_kind_c {(length_kind ==GOOD_LENGTH)-> length ==data.size;(length_kind ==BAD_LENGTH)-> length ==data.size+2;}Use solve before to direct the randomization to generate first the payload dynamic array size and then randomize length field.constraint solve_size_length {solve data.size before length;}8) Constrain the FCS field initial value based on the fcs kind field.constraint fcs_kind_c {(fcs_kind ==GOOD_FCS)-> fcs ==8'b0;(fcs_kind ==BAD_FCS)-> fcs ==8'b1;}9) Define the FCS method.function byte cal_fcs;integer i;byte result ;result =0;result = result ^ da;result = result ^ sa;result = result ^ length;for(i =0;i<data.size;i++)result = result ^data[i];result = fcs ^ result;return result;endfunction: cal_fcs10) Define display methods:Display method displays the current value of the packet fields to standard output.virtual function void display();$display("\n---------------------- PACKET KIND ------------------------- ");$display(" fcs_kind : %s ",fcs_());$display(" length_kind : %s ",length_());$display("-------- PACKET ---------- ");$display(" 0 : %h ",da);$display(" 1 : %h ",sa);$display(" 2 : %h ",length);foreach(data[i])$write("%3d : %0h ",i +3,data[i]);$display("\n %2d : %h ",data.size()+3, cal_fcs);$display("----------------------------------------------------------- \n");endfunction: display11) Define pack method:Packing is commonly used to convert the high level data to low level data that can be applied to DUT. In packet class various fields are generated. Required fields are concatenated to form a stream of bytes which can be driven conveniently to DUTinterface by the driver.virtual function int unsigned byte_pack(ref logic[7:0] bytes[]);bytes =new[data.size+4];bytes[0]= da;bytes[1]= sa;bytes[2]= length;foreach(data[i])bytes[3+ i]=data[i];bytes[data.size()+3]= cal_fcs;byte_pack = bytes.size;endfunction: byte_pack12) Define unpack method:The unpack() method does exactly the opposite of pack method. Unpacking is commonly used to convert a data stream coming from DUT to high level data packet object.virtual function void byte_unpack(const ref logic[7:0] bytes[]);this.da = bytes[0];this.sa = bytes[1];this.length = bytes[2];this.fcs = bytes[bytes.size-1];this.data=new[bytes.size-4];foreach(data[i])data[i]= bytes[i +3];this.fcs =0;if(bytes[bytes.size-1]!= cal_fcs)this.fcs =1;endfunction: byte_unpack14) Define a compare method.Compares the current value of the object instance with the current value of the specified object instance.If the value is different, FALSE is returned.virtual function bit compare(packet pkt);compare=1;if(pkt ==null)begin$display(" ** ERROR ** : pkt : received a null object ");compare=0;endelsebeginif(pkt.da !==this.da)begin$display(" ** ERROR **: pkt : Da field did not match");compare=0;endif(pkt.sa !==this.sa)begin$display(" ** ERROR **: pkt : Sa field did not match");compare=0;endif(pkt.length !==this.length)begin$display(" ** ERROR **: pkt : Length field did not match");compare=0;endforeach(this.data[i])if(pkt.data[i]!==this.data[i])begin。