Cadence SI信号完整性仿真技术

合集下载

CADENCE 仿真流程

第一章进行SI仿真的PCB板图的准备仿真前的准备工作主要包括以下几点：1、仿真板的准备●原理图设计；●PCB封装设计；●PCB板外型边框（Outline）设计，PCB板禁止布线区划分（Keepouts）；●输出网表（如果是用CADENCE的Concept HDL设计的原理图，可将网表直接Expot 到BRD文件中；如果是用PowerPCB设计的板图，转换到allegro中的板图，其操作见附录一的说明）；●器件预布局（Placement）：将其中的关键器件进行合理的预布局，主要涉及相对距离、抗干扰、散热、高频电路与低频电路、数字电路与模拟电路等方面；●PCB板布线分区（Rooms）：主要用来区分高频电路与低频电路、数字电路与模拟电路以及相对独立的电路。

元器件的布局以及电源和地线的处理将直接影响到电路性能和电磁兼容性能；2、器件模型的准备●收集器件的IBIS模型（网上下载、向代理申请、修改同类型器件的IBIS模型等）●收集器件的关键参数，如Tco、Tsetup、Tholdup等及系统有关的时间参数Tclock、Tskew、Tjitter●对IBIS模型进行整理、检查、纠错和验证。

3、确定需要仿真的电路部分，一般包括频率较高，负载较多，拓扑结构比较复杂（点到多点、多点到多点），时钟电路等关键信号线第二章IBIS模型的转化和加载CADENCE中的信号完整性仿真是建立在IBIS模型的基础上的，但又不是直接应用IBIS 模型，CADECE的软件自带一个将IBIS模型转换为自己可用的DML（Device Model Library）模型的功能模块，本章主要就IBIS模型的转换及加载进行讲解。

1、IBIS模型到DML模型的转换在Allegro窗口中选择Analyse\SI/EMI SIM\Library，打开“signal analyze library browser”窗口，在该窗口的右下方点击“Translate →”按钮，在出现的下拉菜单中选择“ibis2signois”项，出现“Select IBIS Source File”窗口（图1），选择想要进行转换的源IBIS文件，按下“打开”按钮，出现转换后文件名及路径设置窗口（缺省设置为和源IBIS文件同名并同路径放置，但此处文件名后缀为dml），设置后按下“保存”按钮，出现保存确定窗口（图2）,点击OK按钮即可，随后会出现一个“messages”窗口，该窗口中的报告文件说明在模型转换过程中出现的问题，对其中的“warning”可不用在意，但如果出现“error”则必须进行修改后重新进行模型格式转化直到没有“error”出现为止，此时转换得到的dml文件才是有效的。

五款信号完整性仿真分析工具

SI五款信号完整性仿真工具介绍(一)Ansoft公司的仿真工具现在的高速电路设计已经达到GHz的水平，高速PCB设计要求从三维设计理论出发对过孔、封装和布线进行综合设计来解决信号完整性问题。

高速PCB设计要求中国工程师必须具备电磁场的理论基础，必须懂得利用麦克斯韦尔方程来分析PCB设计过程中遇到的电磁场问题。

目前，Ansoft公司的仿真工具能够从三维场求解的角度出发，对PCB设计的信号完整性问题进行动态仿真。

Ansoft的信号完整性工具采用一个仿真可解决全部设计问题：SIwave是一种创新的工具，它尤其适于解决现在高速PCB和复杂IC封装中普遍存在的电源输送和信号完整性问题。

该工具采用基于混合、全波及有限元技术的新颖方法，它允许工程师们特性化同步开关噪声、电源散射和地散射、谐振、反射以及引线条和电源/地平面之间的耦合。

该工具采用一个仿真方案解决整个设计问题，缩短了设计时间。

它可分析复杂的线路设计，该设计由多重、任意形状的电源和接地层，以及任何数量的过孔和信号引线条构成。

仿真结果采用先进的3D图形方式显示，它还可产生等效电路模型，使商业用户能够长期采用全波技术，而不必一定使用专有仿真器。

(二)SPECCTRAQuestCadence的工具采用Sun的电源层分析模块：Cadence Design Systems的SpecctraQuest PCB信号完整性套件中的电源完整性模块据称能让工程师在高速PCB设计中更好地控制电源层分析和共模EMI。

该产品是由一份与Sun Microsystems公司签署的开发协议而来的，Sun最初研制该项技术是为了解决母板上的电源问题。

有了这种新模块，用户就可根据系统要求来算出电源层的目标阻抗；然后基于板上的器件考虑去耦合要求，Shah表示，向导程序能帮助用户确定其设计所要求的去耦合电容的数目和类型；选择一组去耦合电容并放置在板上之后，用户就可运行一个仿真程序，通过分析结果来发现问题所在。

cadence信号完整性仿真步骤

IntroductionConsider the proverb, “It takes a village to raise a child.” Similarly, multiple design team members participate in assuring PCB power integrity (PI) as a design moves from the early concept phase to becoming a mature product. On the front end, there’s the electrical design engineer who is responsible for the schematic. On the back end, the layout designer handles physical implemen-tation. Typically, a PI analysis expert is responsible for overall PCB PI and steps in early on to guide the contributions of others. How quickly a team can assure PCB PI relates to the effectiveness of that team. In this paper, we will take a look at currently popular analysis approaches to PCB PI. We will also introduce a team-based approach to PCB PI that yieldsadvantages in resource utilization and analysis results.Common Power Integrity Analysis MethodsThere are two distinct facets of PCB PI – DC and AC. DC PI guarantees thatadequate DC voltage is delivered to all active devices mounted on a PCB (oftenusing IR drop analysis). This helps to assure that constraints are met for currentdensity in planar metals and total current of vias and also that temperatureconstraints are met for metals and substrate materials. AC PI concerns thedelivery of AC current to mounted devices to support their switching activitywhile meeting constraints for transient noise voltage levels within the powerdelivery network (PDN). The PDN noise margin (variation from nominalvoltage) is a sum of both DC IR drop and AC noise.DC PI is governed by resistance of the metals and the current pulled from thePDN by each mounted device. Engineers have, for many years, applied resistivenetwork models for approximate DC PI analysis. Now that computer speedsare faster and larger addressable memory is available, the industry is seeingmuch more application of layout-driven detailed numerical analysis techniquesfor DC PI. Approximation occurs less, accuracy is higher, and automation ofHow a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsBy Brad Brim, Sr. Staff Product Engineer, Cadence Design SystemsAssuring power integrity of a PCB requires the contributions of multiple design team members. Traditionally, such an effort has involved a time-consuming process for a back-end-focused expert at the front end of a design. This paper examines a collaborative team-based approach that makes more efficient use of resources and provides more impact at critical points in the design process.ContentsIntroduction (1)Common Power IntegrityAnalysis Methods (1)Applying a Team-Based Approachto Power Integrity Analysis (3)Summary (6)For Further Information (7)whole-design analysis and postprocessing results are commonly available commercially. In fact, DC PI analysis for PCB designs has become a “signoff” requirement for many OEMs. See Figure 1 (left) for typical results for current density.Since metal conductivity is temperature-dependent, DC IR drop is a nonlinear analysis. IR drop results can vary by more than 20% when temperature effects are considered, according to case studies for high-power designs. There is, however, a way to accurately characterize PCB IR drop while assuring that the PDN noise margin isn’twasted. Using a DC analysis tool that provides capabilities such as electrical/thermal co-simulation, perform a linear electrical analysis at ambient temperature; take the resulting power loss and apply it to perform a linear thermal analysis. Then, perform another linear electrical analysis with consideration of the localized temperature-dependent conductivity. This process converges in just a few iterations to yield a desired result. See Figure 1 for an illustration of this solution, as implemented in the Cadence ® Sigrity ™ PowerDC ™DC analysis tool.TemperatureLoss DensityPlane Current Surface TemperatureElectrical Analysis Thermal AnalysisFigure 1: Current density (left) and temperature distribution (right) for a PCB design due to DC powerdelivery as two linear solutions are iteratively linked to address nonlinear electro-thermal analysis.AC PI is governed by voltage regulator modules, loop inductances, decoupling capacitors (decaps), and plane capacitance. AC PI effects tend to be global in nature due to plane resonances, plane-to-plane coupling, and shared reference planes. As such, this calls for full-board analysis, as well as more resource-intensive analysis algorithms. A hybrid of circuit theory and electromagnetic (EM) analyses is the most commonly applied AC PI analysis for PCBs. This type of analysis is available in the frequency domain to extract S-parameters, using a tool such as Cadence Sigrity PowerSI ™ frequency-domain electrical analysis solution. It’s also available in the time domain to directly generate transient waveforms, using a tool such as Cadence Sigrity Speed2000™ time-domain analysis solution. With the proper tools, an engineer can, in tens of minutes, accurately characterize the PDNbehavior of even the largest and most complex PCBs from DC to multi-gigahertz using single- to low double-digit gigabytes of memory.Transient PI analysis may seem attractive because it directly yields noise waveforms; however, in reality, it is less commonly applied than frequency-domain impedance analysis. “Target impedance” profiles are applied as PIconstraints. Lower impedance corresponds to lower transient noise. Without direct vendor specification, reasonable target impedance may be estimated based on device specifications for voltage ripple and AC switching current. See Figure 2 for a comparison of frequency-domain and time-domain results. In this comparison, the Cadence Sigrity OptimizePI ™ tool was used to significantly reduce an impedance peak near 800MHz by applying an alternate set of decaps to mount for a DIMM module. This solution reduced peak-to-peak PDN noise for the optimized design by 12% and the component and manufacturing cost of the decap implementation by 21%.Figure 2: Impedance profile and transient PDN noise of a DIMM before and after thedecap implementation was optimized.Applying a Team-Based Approach to Power Integrity AnalysisTraditionally, PI experts have performed pre-layout decap selections and initial IR drop analyses. This is a substantial time investment at the front end of a design for a back-end-focused expert. By applying a more collaborative approach, a design team can make better use of its resources and expertise, and generate more impactful results.A team could set up simple analyses that yield actionable results and that could be performed by other members of the PI team. This PCB PI team would ideally consist of three key members: design engineer, layout designer, and PI analysis expert, as shown in Figure 3.Design Engineer•Can start with either BOM or schematic•Apply Power Feasibility Editor for DeCap selection and PIconstraint definitionLayout Designer•Can start as early asfloorplanning stage•First order analysis directlyon layout•Analyze, edit, re-analyze•DeCap placement guidanceand DRCPI Analysis Expert•Can start at any stage•Leverages setup and datafrom rest of team•Signoff capable detailedanalysisFigure 3: Roles and responsibilities of the PCB PI design team.There is now a tool available on the market that supports team-based PCB PI analysis. Cadence Allegro® SigrityPI is the industry’s first front-to-back, constraint-based PI approach for PCB and IC package designs. This tool differs from other solutions in the way that it accesses existing analysis algorithms and how the analysis resultsare applied. In addition, the tool also provides PI-focused infrastructure support of non-analysis tasks. As a result, design engineers and layout designers can contribute earlier and more effectively to PCB PI. The DC and AC PI analysis capabilities described in the previous section are available in the associated Power Integrity Signoff and Optimization Option.PCB design engineers are responsible for front-end tasks. They must generate an initial Bill of Materials (BOM)to set in motion cost feasibility studies and assure electrical design intent by generating circuit schematics. They typically work independently of DC PI concerns. However, to support AC PI, design engineers must add decaps and include them in the BOM and the schematic. Some device vendors provide datasheet guidance for decap selection (type and/or quantity), but many do not. Even with datasheet guidance, it is tedious for design engineers to assemble and interpret the specifications for each device, instantiate all the unique components, assure they appear logically in the schematic, etc. No mechanism has existed for physical placement guidance to be communicated for back-end application.With constraint-based design methods, engineers gain a uniform interface for design-intent information and for automating a broad class of tasks across front-to-back flows. PI [electrical] constraint sets (PI Csets) have been added to save all component-level PI information. Design engineers may apply PI Csets to quickly and completely define PI design intent for all mounted components. PI Csets also automate instantiation of components and inclusion in the BOM.Refer to Figure 4 for an example of a PI Cset in Allegro Sigrity PI. PI Csets contain information for each power rail, including decap component names, quantity of each component, package type, and physical placement guidance.Figure 4: PI constraint set contents viewed from the constraint manager.PI Cset creation is automated by the tool’s Power Feasibility Editor, which provides a mechanism to enter datasheet decap selection and physical placement guidance. Figure 5 shows a view of the tool’s Power Feasibility Editor. In addition to placement guidance, a PI Cset communicates to the layout designer component and power rail associ-ation for decaps, helping the designer perform more reliable placement.Figure 5: Single-point analysis results in the Power Feasibility Editor.The Power Feasibility Editor also provides access to approximate and detailed pre-layout analysis for selectionand placement of decaps. High-level specifications are made to generate target impedance profiles when device vendors do not provide them. An approximate PI analysis called “single-point” is provided for interactive decap selection. For more detailed pre-layout, the tool provides access to the data in the Cadence Sigrity OptimizePI tool. The engineer simply clicks a button within the Power Feasibility Editor to generate PI Csets.Figure 6: Split-screen view of layout (left) and IR drop analysis results (right).Unlike design engineers, layout designers are concerned with DC PI issues. Layout designers control metal shapes and vias and these, in turn, control PI behaviors for DC IR drop and current flow. Layout designers can intuitively understand and act upon analysis results for these DC PI effects. The Allegro Sigrity PI tool provides access within the layout environment to the setup and results display for DC IR drop and current constraint analyses. DC analysis is fast, though not conducted in real time in order to enable dynamic updating of analysis results as layout updates are made.The tool provides a split-screen view, as shown in Figure 6, to support a fixed view of analysis results as layout designers dynamically make updates to address IR drop or current constraint issues. The two views are synchro-nized for operations that affect the display, such as layer changes, zoom, and pan. Layout designers can apply this split-screen view of DC analysis results as they craft an initial layout, before the PI analysis expert gets involved.As a more effective method to communicate where PI issues exist in the design, the split-screen view can also be applied with detailed analysis results performed separately by PI analysis experts. In fact, to more quickly verify improved PI performance, the layout designer can launch the same detailed analysis performed by the PI analyst. Layout designers strongly influence AC PI success with their placement of decaps. Decaps placed close to a device generally benefit PI, but restrict routing channels due to decap mounting vias. Decaps placed too far from a device will be ineffective at providing switching current to the device and will negatively affect PI. Present design methods do not typically provide decap placement guidance, including information as simple as which device is associated with a decap. By conveying design intent, previously described PI Csets enable more effective placement of decaps by layout designers. The associated device and power rail and placement guidance are all specified in the PI Cset.A decap placement mode is implemented to support layout designers, as shown in Figure 7. Simply select a mounted component and a power rail, and then cycle through a point-and-click placement process. The selected device is highlighted and three optional visual placement guidance displays are available: device to decap distance for top layer, device to decap distance for bottom layer, and decap effective radius. The first two are defined in the PI Cset and are conceptually familiar. The decap effective radius is the maximum distance at which the decap will be maximally effective. It is a function of the stack-up and decap mounting parasitics as well as the decap value and its intrinsic parasitics. It is dynamically computed as the cursor moves due to local availability of metal shapes on the associated power and ground layers.Decap Placement GuidanceTop-sideSetbackDistance*DecapEffectiveRadiusBottom-sideSetbackDistanceFigure 7: Layout view during decap placement for device U0501 with top (yellow) and bottom (blue)setback distances and decap effective radius (white circle) displayedTo ease the setup for detailed PI analysis, design intent and analysis setup information specified by design engineers and layout designers is available to PI analysis. PI Csets serve as a convenient mechanism to communicate updated placement guidance or requirements for updates on decap selection (either type or quantity) for a specific device instance or all devices to which a PI Cset is applied. Changes to PI Csets also convey information back to the design engineer and enable automated update of the schematic and BOM.SummaryWhile current PCB PI analysis tools are continuing to serve the design community well, they are even more effective when combined with a front-to-back, constraint-based approach. Under this type of methodology, each design team member can more efficiently accomplish his or her individual tasks and communicate design intent infor-mation to colleagues for increased efficiency of the overall PCB design flow. This approach provides access toactionable analysis results where they are most impactful. It also leverages earlier defined analysis setup infor-mation for the PI expert, and eases communication of design changes from his or her back-end role to front-end colleagues.For Further InformationTo learn more about Cadence Allegro Sigrity PI solution, visit: /products/sigrity/Pages/ solution.aspxCadence Design Systems enables global electronic design innovation and plays an essential role in thecreation of today’s electronics. Customers use Cadence software, hardware, IP, and expertise to designand verify today’s mobile, cloud and connectivity applications. © 2014 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and Allegro are registered trademarks and OptimizePI,PowerDC, PowerSI, Sigrity, and Speed2000 are trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders.。

cadence信号完整性仿真步骤.

IntroductionConsider the proverb, “It takes a village to raise a child.” Similarly, multiple design team members participate in assuring PCB power integrity (PI as a design moves from the early concept phase to becoming a mature product. On the front end, there’s the electrical design engineer who is responsible for the schematic. On the back end, the layout designer handles physical implemen-tation. Typically, a PI analysis expert is responsible for overall PCB PI and steps in early on to guide the contributions of others. How quickly a team can assure PCB PI relates to the effectiveness of that team. In this paper, we will take a look at currently popular analysis approaches to PCB PI. We will also introduce a team-based approach to PCB PI that yieldsadvantages in resource utilization and analysis results.Common Power Integrity Analysis MethodsThere are two distinct facets of PCB PI – DC and AC. DC PI guarantees thatadequate DC voltage is delivered to all active devices mounted on a PCB (oftenusing IR drop analysis. This helps to assure that constraints are met for currentdensity in planar metals and total current of vias and also that temperatureconstraints are met for metals and substrate materials. AC PI concerns thedelivery of AC current to mounted devices to support their switching activitywhile meeting constraints for transient noise voltage levels within the powerdelivery network (PDN. The PDN noise margin (variation from nominalvoltage is a sum of both DC IR drop and AC noise.DC PI is governed by resistance of the metals and the current pulled from thePDN by each mounted device. Engineers have, for many years, applied resistivenetwork models for approximate DC PI analysis. Now that computer speedsare faster and larger addressable memory is available, the industry is seeingmuch more application of layout-driven detailed numerical analysis techniquesfor DC PI. Approximation occurs less, accuracy is higher, and automation ofHow a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsBy Brad Brim, Sr. Staff Product Engineer, Cadence Design SystemsAssuring power integrity of a PCB requires the contributions of multiple design team members. Traditionally, such an effort has involved a time-consuming process for a back-end-focused expert at the front end of a design. This paper examines a collaborative team-based approach that makes more efficient use of resources and provides more impact at critical points in the design process.ContentsIntroduction . (1)Common Power IntegrityAnalysis Methods . (1)Applying a Team-Based Approachto Power Integrity Analysis . (3)Summary (6)For Further Information . (7)whole-design analysis and postprocessing results are commonly available commercially. In fact, DC PI analysis for PCB designs has become a “signoff” requirement for many OEMs. See Figure 1 (left for typical results for current density.Since metal conductivity is temperature-dependent, DC IR drop is a nonlinear analysis. IR drop results can vary by more than 20% when temperature effects are considered, according to case studies for high-power designs. There is, however, a way to accurately characterize PCB IR drop wh ile assuring that the PDN noise margin isn’twasted. Using a DC analysis tool that provides capabilities such as electrical/thermal co-simulation, perform a linear electrical analysis at ambient temperature; take the resulting power loss and apply it to perform a linear thermal analysis. Then, perform another linear electrical analysis with consideration of the localized temperature-dependent conductivity. This process converges in just a few iterations to yield a desired result. See Figure 1 for an illustration of this solution, as implemented in the Cadence® Sigrity™ PowerDC™DC analysis tool.TemperatureLoss DensityPlane CurrentSurface TemperatureElectrical AnalysisThermal AnalysisFigure 1: Current density (left and temperature distribution (right for a PCB design due to DC powerdelivery as two linear solutions are iteratively linked to address nonlinear electro-thermal analysis.AC PI is governed by voltage regulator modules, loop inductances, decoupling capacitors (decaps, and plane capacitance. AC PI effects tend to be global in nature dueto plane resonances, plane-to-plane coupling, and shared reference planes. As such, this calls for full-board analysis, as well as more resource-intensive analysis algorithms. A hybrid of circuit theory and electromagnetic (EM analyses is the most commonly applied AC PI analysis for PCBs. This type of analysis is available in the frequency domain to extract S-parameters, using a tool such as Cadence Sigrity PowerSI™ frequency-domain electrical analysis solution. It’s also available in the time domain to directly generate transient waveforms, using a tool such as Cadence Sigrity Speed2000™ time-domain analysis solution. With the proper tools, an engineer can, in tens of minutes, accurately characterize the PDNbehavior of even the largest and most complex PCBs from DC to multi-gigahertz using single- to low double-digit gigabytes of memory.Transient PI analysis may seem attractive because it directly yields noise waveforms; however, in reality, it is less commonly applied than frequency-domain impedance analysis. “Target impedance” profiles are applied as PIconstraints. Lower impedance corresponds to lower transient noise. Without direct vendor specification, reasonable target impedance may be estimated based on device specifications for voltage ripple and AC switching current. See Figure 2 for a comparison of frequency-domain and time-domain results. In this comparison, the Cadence Sigrity OptimizePI ™ tool was used to significantly reduce an impedance peak near 800MHz by applying an alternate set of decaps to mount for a DIMM module. This solution reduced peak-to-peak PDN noise for the optimized design by 12% and the component and manufacturing cost of the decap implementation by 21%. 2How a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsFigure 2: Impedance profile and transient PDN noise of a DIMM before and after thedecap implementation was optimized.Applying a Team-Based Approach to Power Integrity AnalysisTraditionally, PI experts have performed pre-layout decap selections and initial IR drop analyses. This is a substantial time investment at the front end of a design for a back-end-focused expert. By applying a more collaborativeapproach, a design team can make better use of its resources and expertise, and generate more impactful results.A team could set up simple analyses that yield actionable results and that could be performed by other members of the PI team. This PCB PI team would ideally consist ofthree key members: design engineer, layout designer, and PI analysis expert, as shown in Figure 3.Design Engineer•Can start with either BOM or schematic•Apply Power Feasibility Editor for DeCapselection and PIconstraint definitionLayout Designer•Can start as early as floorplanning stage •First order analysis directly on layout•Analyze, edit, re-analyze•DeCap placement guidanceand DRCPI Analysis Expert•Can start at any stage•Leverages setup and data from rest of team•Signoff capable detailed analysis Figure 3: Roles and responsibilities of the PCB PI design team. 3How a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsThere is now a tool available on the market that supports team-based PCB PI analysis. Cadence A llegro® Sigrity PI is the industry’s first front-to-back, constraint-based PI approach for PCB and IC package designs. This tool differs from other solutions in the way that it accesses existing analysis algorithms and how the analysis results are applied. In addition, the tool also provides PI-focused infrastructure support of non-analysis tasks. As a result, design engineers and layout designers can contribute earlierand more effectively to PCB PI. The DC and AC PI analysis capabilities described in the previous section are available in the associated Power Integrity Signoff and Optimization Option.PCB design engineers are responsible for front-end tasks. They must generate an initial Bill of Materials (BOM to set in motion cost feasibility studies and assure electrical design intent by generating circuit schematics. They typically work independently of DC PI concerns. However, to support AC PI, design engineers must add decaps and include them in the BOM and the schematic. Some device vendors provide datasheet guidance for decap selection (type and/or quantity, but many do not. Even with datasheet guidance, it is tedious for design engineers toassemble and interpret the specifications for each device, instantiate all the unique components, assure they appear logically in the schematic, etc. No mechanism has existed for physical placement guidance to be communicated for back-end application.With constraint-based design methods, engineers gain a uniform interface for design-intent information and for automating a broad class of tasks across front-to-back flows. PI [electrical] constraint sets (PI Csets have been added to save all component-level PI information. Design engineers may apply PI Csets to quickly and completely define PI design intent for all mounted components. PI Csets also automate instantiation of components and inclusion in the BOM.Refer to Figure 4 for an example of a PI Cset in Allegro Sigrity PI. PI Csets contain information for each power rail,including decap component names, quantity of each component, package type, and physical placement guidance.Figure 4: PI constraint set contents viewed from the constraint manager.PI Cset creation is automated by the tool’s Power Feasibility Editor, which providesa mechanism to enter datasheet decap selection and physical placement guidance. Figure5 shows a view of the tool’s Power Feasibility Editor. In addition to placement guidance,a PI Cset communicates to the layout designer component and power rail associ-ation for decaps, helping the designer perform more reliable placement. 4How a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsFigure 5: Single-point analysis results in the Power Feasibility Editor.The Power Feasibility Editor also provides access to approximate and detailed pre-layout analysis for selection and placement of decaps. High-level specifications are made to generate target impedance profiles when device vendors do not provide them. An approximate PI analysis called “single-point” is provided for interactive decap selection. For more detailed pre-layout, the tool provides access to the data in the Cadence Sigrity OptimizePI tool.The engineer simply clicks a button within the Power Feasibility Editor to generate PI Csets.Figure 6: Split-screen view of layout (left and IR drop analysis results (right.Unlike design engineers, layout designers are concerned with DC PI issues. Layout designers control metal shapes and vias and these, in turn, control PI behaviors for DC IR drop and current flow. Layout designers can intuitively understand and act upon analysis results for these DC PI effects. The Allegro Sigrity PI tool provides access within the layout environment to the setup and results display for DC IR drop and current constraint analyses. DC analysis is fast, though not conducted in real time in order to enable dynamic updating of analysis results as layout updates are made. 5How a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsHow a Team-Based Approach to PCB Power Integrity Analysis Yields Better Results The tool provides a split-screen view, as shown in Figure 6, to support a fixedview of analysis results as layout designers dynamically make updates to address IR drop or current constraint issues. The two views are synchronized for operations that affect the display, such as layer changes, zoom, and pan. Layout designers can apply this split-screen view of DC analysis results as they craft an initial layout, before the PI analysis expert gets involved. As a more effective method to communicate where PI issues exist in the design, the split-screen view can also be applied with detailed analysis results performed separately by PI analysis experts. In fact, to more quickly verify improved PI performance, the layout designer can launch the same detailed analysis performed by the PI analyst. Layout designers strongly influence AC PI success with their placement of decaps. Decaps placed close to a device generally benefit PI, but restrict routing channels due to decap mounting vias. Decaps placed too far from a device will be ineffective at providing switching current to the device and will negatively affect PI. Present design methods do not typically provide decap placement guidance, including information as simple as which device is associated with a decap. By conveying design intent, previously described PI Csets enable more effective placement of decaps by layout designers. The associated device and power rail and placement guidance are all specified in the PI Cset. A decap placement mode is implemented to support layout designers, as shown in Figure 7. Simply select a mounted component and a power rail, and then cycle through a point-and-click placement process. The selected device is highlighted and three optional visual placement guidance displays are available: device to decap distance for top layer, device to decap distance for bottom layer, and decap effective radius. The first two are defined in the PI Cset and are conceptually familiar. The decap effective radius is the maximum distance at which the decap will be maximally effective. It is a function of the stack-up and decap mounting parasitics as well as the decap value and its intrinsic parasitics. It is dynamically computed as the cursor moves due to local availability of metal shapes on the associated power and ground layers. Decap Placement Guidance Top-side Setback Distance * Decap Effective Radius Bottom-side Setback Distance Figure 7: Layout view during decap placement for device U0501 with top (yellow andbottom (blue setback distances and decap effective radius (white circle displayed To ease the setup for detailed PI analysis, design intent and analysis setup information specified by design engineers and layout designers is available to PI analysis. PI Csets serve as a convenient mechanism to communicate updated placement guidance or requirements for updates on decap selection (either type or quantity for a specific device instance or all devices to which a PI Cset is applied. Changes to PI Csets also convey information back to the design engineer and enable automated update of the schematic and BOM. Summary While current PCB PI analysis tools are continuing to serve the design community well, they are even more effective when combined with a front-to-back, constraint-based approach. Under this type of methodology, each design team member can more efficiently accomplish his or her individual tasks and communicate design intent information to colleagues for increased efficiency of the overall PCB design flow. This approach provides access to 6How a Team-Based Approach to PCB Power Integrity Analysis Yields Better Results actionable analysis results where they are most impactful. It also leverages earlier defined analysis setup information for the PI expert, and eases communication of design changes from his or her back-end role to front-end colleagues. For Further Information To learn more about Cadence Allegro Sigrity PI solution, visit:/products/sigrity/Pages/ solution.aspx Cadence Design Systems enables global electronic design innovation and plays an essential role in the creation of today’s electronics. Customers use Cadence software, hardware, IP, and expertise to design and verify to day’s mobile, cloud and connectivity applications. © 2014 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and Allegro are registered trademarks and OptimizePI, PowerDC, PowerSI, Sigrity, and Speed2000 are trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 1932 01/14 CY/DM/PDF。

基于Cadence_Allegro的高速PCB设计信号完整性分析与仿真

基于Cadence_Allegro的高速PCB设计信号完整性分析与仿真覃婕;阎波;林水生【摘要】信号完整性问题已成为当今高速PCB设计的一大挑战,传统的设计方法无法实现较高的一次设计成功率,急需基于EDA软件进行SI仿真辅助设计的方法以解决此问题.在此主要研究了常见反射、串扰、时序等信号完整性问题的基础理论及解决方法,并基于IBIS模型,采用Cadence_Allegro软件的Specctraquest和Sigxp组件工具对设计的高速14位ADC/DAC应用系统实例进行了SI仿真与分析,验证了常见SI问题解决方法的正确性.%Signal Integrity (SI) problem has became one of the greatest challenge in high-speed PCB design area, the traditional design method is hard to realize high once-through design success, SI simulation aided design method based on EDA software is demanded to solve this problem. The basic theory and solutions of some normal SI problems such as reflection,crosstalk and timing are researched. SI analysis and simulation of a high-speed 14bits ADC/DAC application system based on Specctraquest and Sigxp in Cadence_Allegrospb 16. 0 are designed, the validity of the solutions to the SI problems is verified.【期刊名称】《现代电子技术》【年(卷),期】2011(034)010【总页数】4页(P169-171,178)【关键词】高速PCB设计;信号完整性;反射;串扰;时序;SI分析及仿真【作者】覃婕;阎波;林水生【作者单位】电子科技大学通信与信息工程学院,四川成都,611731;电子科技大学通信与信息工程学院,四川成都,611731;电子科技大学通信与信息工程学院,四川成都,611731【正文语种】中文【中图分类】TN919-340 引言随着半导体工艺的迅猛发展以及人们对信息高速化、宽带化的需求，高速PCB 设计已经成为电子产品研制的一个重要环节，信号完整性( Signal Integrity，SI)问题(包括反射、串扰、定时等)也逐渐发展成为高速PCB设计中难以避免的难题，若不能较好地解决信号完整性设计问题，将有可能造成高速PCB设计的致命错误，浪费财力物力，延长开发周期，降低生产效率。

五款信号完整性仿真分析工具

SI 五款信号完整性仿真工具介绍（一）Ansoft公司的仿真工具现在的高速电路设计已经达到GHz的水平，高速PCB设计要求从三维设计理论出发对过孔、封装和布线进行综合设计来解决信号完整性问题。

高速PCB 设计要求中国工程师必须具备电磁场的理论基础，必须懂得利用麦克斯韦尔方程来分析PCB设计过程中遇到的电磁场问题。

目前，An soft公司的仿真工具能够从三维场求解的角度出发，对PCB 设计的信号完整性问题进行动态仿真。

Ansoft 的信号完整性工具采用一个仿真可解决全部设计问题：Slwave是一种创新的工具，它尤其适于解决现在高速PCB和复杂IC封装中普遍存在的电源输送和信号完整性问题。

该工具采用一个仿真方案解决整个设计问题，缩短了设计时间。

它可分析复杂的线路设计，该设计由多重、任意形状的电源和接地层，以及任何数量的过孔和信号引线条构成。

仿真结果采用先进的3D 图形方式显示，它还可产生等效电路模型，使商业用户能够长期采用全波技术，而不必一定使用专有仿（二）SPECCTRAQuestCade nee的工具采用Sun的电源层分析模块:Cade nee Design System 的SpeeetraQuest PCB信号完整性套件中的电源完整性模块据称能让工程师在高速PCB设计中更好地控制电源层分析和共模EMI 。

该产品是由一份与Sun Microsystems公司签署的开发协议而来的，Sun最初研制该项技术是为了解决母板上的电源问题。

Cadence Allegro Sigrity介绍

高科技企业开发复杂的芯片，封装和单板努力克服由于飞速增长的IC速度和数据传输速率联合引起的供电电压的降低，更高密度，越来越小型化的结构引起的电源完整性和信号完整性问题。

同时，更高的I/O数目，多堆叠的芯片和封装以及更高的电气性能约束都使得IC封装物理设计更加复杂。

Cadence具有突破型进展的解决方案，基于Sigrity专利技术，解决这些设计挑战。

该解决方案致力于完整的电源供电系统分析跨越了芯片，封装和单板；系统级的信号完整性（SI）分析，包含高速信号传输同步反转噪声和单个和多个芯片封装，最先进的3D封装以及系统级封装（SiPs）的高级物理设计。

Power Integrity电源完整性Cadence 电源完整性（PI）解决方案，基于Sigrity技术，提供signoff级别精度的PCB和IC封装的AC和DC电源分析。

每个工具都能与Cadence Allegro® PCB 和IC封装物理设计解决方案无缝集成。

Sigrity PowerSIIC封装和PCB设计快速准确的全波电磁场分析作为专业的频域分析工具，为当前高速电路设计中面临的各种信号完整性(SI)、电源完整性(PI)和电磁兼容(EMI/EMC)分析提供快速准确的全波电磁场分析，并提供宽带S参数提取以及频域仿真。

Sigrity™ PowerSI®可以为IC封装和PCB设计提供快速准确的全波电磁场分析，从而解决高速电路设计中日益突出的各种PI和SI问题：如同步切换噪声（SSN）问题，电磁耦合问题，信号回流路径不连续问题，电源谐振问题，去耦电容放置不当问题以及电压超标等问题，从而帮助用户发现或改善潜在的设计风险。

PowerSI可以方便的提取封装和PCB的各种网络参数(S/Y/Z)，并对复杂的空间电磁谐振问题产生可视化的输出。

PowerSI能与当前主流的物理设计数据库如PCB, IC封装和系统级封装(SiP)进行无缝连接。

主要功能• 为IC封装和PCB的电源分配网络(PDN)的可靠设计提供指导• 可以分析板上任意结构的电磁耦合特性，为器件/去耦电容的放置位置以及过孔的排布提供依据• 可以提取IC封装电源网络与信号网络的阻抗（Z）参数及散射（S）参数，研究电源的谐振频率以及输入阻抗，或研究信号的插入损耗及反射系数，为精确分析电源和信号的性能提供依据; 为时域SSN仿真提供可靠的宽带网络参数模型• 分析整板远场和近场的EMI/EMC性能，全三维显示复杂的近场辐射水平，为解决板级的EMI/EMC问题提供依据• 分析板上任意位置的谐振特性，找出系统在实际工作时电源平面上的谐振及波动特性，为电源的覆铜方式及去耦电容的放置位置提供依据• 支持叠层以及其他物理设计参数的假定(What-if)分析，快速评估设计参数对系统性能的影响• 基于专利算法的精确直流求解引擎(PowerDC)，可支持从直流(DC)到宽频段的精确模型提取• 与三维(3D)IC封装设计和板级设计工具无缝集成优势与特点• 专业的频域分析工具，致力于Package/PCB全面的信号完整性、电源完整性、EMI/EMC的分析，有10年的历史，经过数以千计的设计产品验证，成熟可靠• 算法稳定可靠，即使对不规则的平面结构也能精确求解• 提供智能的多CPU、多任务分布式计算能力，可以把一个大型的复杂任务分配给多个CPU或多台计算机同步完成，从而大大提高了仿真效率。

Cadence Allegro Sigrity介绍

Cadence Allegro Sigrity介绍高科技企业开发复杂的芯片，封装和单板努力克服由于飞速增长的IC速度和数据传输速率联合引起的供电电压的降低，更高密度，越来越小型化的结构引起的电源完整性和信号完整性问题。

同时，更高的I/O数目，多堆叠的芯片和封装以及更高的电气性能约束都使得IC 封装物理设计更加复杂。

Cadence具有突破型进展的解决方案，基于Sigrity专利技术，解决这些设计挑战。

Power Integrity电源完整性Cadence 电源完整性（PI）解决方案，基于Sigrity技术，提供signoff 级别精度的PCB和IC封装的AC和DC电源分析。

每个工具都能与Cadence Allegro® PCB 和IC封装物理设计解决方案无缝集成。

PowerSI可以方便的提取封装和PCB的各种网络参数(S/Y/Z)，并对复杂的空间电磁谐振问题产生可视化的输出。

PowerSI能与当前主流的物理设计数据库如PCB, IC封装和系统级封装(SiP)进行无缝连接。

Allegro_PCB_SI 一步一步学会前仿真

Allegro PCB SI：一步一步学会前仿真Learn Allegro PCB SI Pre-simulation Step by StepDoc Scope : Cadence 16.5Doc Number : SFTEC12007Author : Daniel ZhongCreate Date : 2012-04-10Rev : 1.00目录1Cadence Allegro PCB SI简介 (7)1.1高速PCB设计流程 (7)2Allegro PCB SI的前仿真 (8)2.1准备仿真模型和其他需求 (8)2.1.1获取所使用元器件的仿真模型 (9)2.1.2获取所使用连接器的仿真模型 (10)2.1.3获取所使用元器件和连接器的器件手册和用户指南等相关资料 (10)2.1.4获取所需的规范文档 (10)2.1.5了解相关电路和接口工作原理 (10)2.1.6提取与信号完整性相关的要求 (10)2.1.7预先创建拓扑样本 (11)2.1.8预先创建相对于不同阈值电压的眼图模板 (11)2.1.9预先创建自定义测量 (12)2.2仿真前的规划 (12)2.3关键器件预布局 (13)2.4模型加载和仿真配置 (13)2.4.1模型的转化 (14)2.4.2使用SI Design Setup配置 (15)2.4.3选择需要配置的信号线 (16)2.4.4设置仿真库 (18)2.4.5设置电源和地网络 (20)2.4.6设置叠层 (24)2.4.7设置元器件类别 (27)2.4.8为元器件分配和创建模型 (28)2.4.9设置差分对 (37)2.4.10设置仿真参数 (42)2.4.11SI Design Audit相关 (50)2.4.12提取拓扑 (52)2.4.13在SigXP中设置仿真库和仿真参数 (54)2.4.14在SigXP中绘制拓扑 (58)2.5方案空间分析 (68)2.5.1输出驱动力扫描分析 (71)2.5.2Stub长度扫描分析 (73)2.5.3线宽线间距扫描分析 (74)2.6方案到约束规则的转化 (76)2.6.1传输线延迟规则的设置 (77)2.6.2拓扑结构等传输线特性规则的设置 (80)2.6.3传输线耦合规则的设置 (80)2.6.4拓扑规则在约束管理器中的应用 (81)3Allegro PCB SI的后仿真 (84)表格表格 1：Routed Interconnect Models参数 (45)表格 2：Simulation栏眉仿真参数 (47)表格 3：IO Cell Stimulus Edit窗口中的选项 (68)图图 1：传统的PCB设计流程图 (7)图 2：Allegro PCB SI高速PCB设计流程图 (8)图 3：眼图模式下的眼图模板 (11)图 4：地址、命令和控制信号传输线拓扑 (12)图 5：RDIMM的布局示意图 (13)图 6：Model Integrity界面 (14)图 7：使用Model Integrity将IBIS文件转换至DML格式 (15)图 8：Cadence Product Choices产品选择器窗口 (16)图 9：Allegro PCB SI GXL界面 (17)图 10：Setup Category Selection窗口 (17)图 11：Setup Xnet Selection窗口 (17)图 12：Allegro PCB SI GXL关于网络设置的提醒框 (18)图 13：Setup Library Search Directories窗口 (19)图 14：Setup Library File Extensions窗口 (19)图 15：Setup Working Libraries窗口 (19)图 16：Setup Power and Ground Nets窗口 (20)图 17：Allegro PCB SI GXL电压赋值窗口 (21)图 18：选择“Edit Voltage On Any Net In Design” (21)图 19：Identify DC Nets窗口。

五款信号完整性仿真分析工具

五款信号完整性仿真分析工具1. HyperLynx Signal Integrity (SI) - HyperLynx SI是一款强大的信号完整性仿真工具，可用于设计和分析高速电路板中的信号完整性问题。

它可以对电路板进行仿真，包括信号传输、阻抗匹配、信号的波形、抖动、时钟信号和纹波等方面的分析。

HyperLynx SI还具有强大的分析和优化功能，可以帮助用户更好地理解和解决信号完整性问题。

2. Cadence Sigrity PowerSI - Cadence Sigrity PowerSI是一款专注于高速电路板的信号完整性仿真分析工具。

它可以对电路板中的电源和接地网络进行建模和仿真，以帮助设计人员识别和解决电源噪声和接地回路问题。

PowerSI还可以对信号传输线进行建模和仿真，以分析信号的波形、纹波和抖动等方面的问题。

3. Keysight Advanced Design System (ADS) - ADS是一套综合性的电子设计自动化(EDA)工具，其中包含了强大的信号完整性仿真分析功能。

ADS可以对高速电路板进行信号传输线建模和仿真分析，包括传输线的传输特性、阻抗匹配、波形纹波和互连信号完整性等方面。

它还提供了多种信号完整性分析工具，帮助用户进行电路设计和优化。

4. Ansys SIwave - Ansys SIwave是一款专注于电路板和芯片封装的信号完整性仿真工具。

它可以对高速信号传输线进行建模和仿真，包括分析信号的波形、纹波、抖动和互连信号完整性等方面的问题。

SIwave 还具备电源和地线分析功能，以帮助设计人员解决电源噪声和接地回路问题。

5. Mentor Graphics HyperLynx DRC - HyperLynx DRC是一款专注于检测和解决高速电路板信号完整性问题的仿真工具。

它可以对电路板进行布线规则检查，并自动识别和修复可能引起信号完整性问题的布线错误。

HyperLynx DRC还可以进行交叉耦合分析、时钟分析和时域电压纹波分析等方面的仿真。

Cadence-SI-Simulation

Cadence仿真介绍第一部分：仿真流程第二部分：IBIS模型IBIS模型和SPICE模型比较：SPICE模型：（1）电压/电流/时间等关系从器件图形、材料特性得来，建立在低级数据的基础上（2）每个buffer中的器件分别描述/仿真（3）仿真速度很慢（4）包含芯片制造工艺信息IBIS模型：（1）电压/电流/时间关系建立在IV/VT数据曲线上（2）没有包括电路细节（3）仿真速度快，是SPICE模型的25倍以上（4）不包含芯片内部制造工艺信息基于上述原因，对于在系统级的设计，我们更倾向于使用IBIS模型。

目前IBIS主要使用的有V1.1，V2.1，V3.2及V4.0等版本。

模型结构如下图：C_pkg，R_pkg，L_pkg为封装参数；C_comp为晶片pad电容；Power_Clamp，GND_Clamp 为ESD结构的V/I曲线。

输出模型比输入模型多一个pull-up，pull-down的V/T曲线。

Cadence的model integrity工具负责对IBIS模型进行语法检查、编辑以及进行DML格式转换。

Cadence仿真不直接使用IBIS模型，而必须先把IBIS转换成DML。

<实例操作演示>第三部分：电路板设置电路板设置包括：（1）叠层设置；（2）DC电压设置；（3）器件设置；（4）模型分配；上述步骤可以通过setup advisor向导设置。

1，叠层设置2，DC电压设置3，器件设置4，模型分配电阻、电容、电感等无源器件的模型可以通过建立ESPICE模型来获得。

<实例操作演示>第四部分：设置仿真参数模型分配完成后，就可以进行仿真了。

在进行仿真之前，需要对仿真的参数进行设置。

Pulse cycle count：通过指定系统传输的脉冲数目来确定仿真的持续时间。

Pulse Clock Frequency：确定仿真中用来激励驱动器的脉冲电压源的频率。

Pulse Duty cycle：脉冲占空比。

利用Cadence Allegro PCB SI进行SI仿真分析

利用Cadence Allegro PCB SI进行SI仿真分析摘要本文主要针对高速电路中的信号完整性分析，利用Cadence Allegro PCB SI 工具进行信号完整性（SI）分析。

说明：本手册中的实例均采用Cadence SPB 16_2操作实现。

目录一、高速数字电路的基本知识 (3)1.1高速电路的定义 (3)1.2高速PCB的设计方法 (3)1.3微带线与带状线 (4)1.4常见的高速数字电路 (5)1.4.1 ECL(Emitter Coupled Logic)射级耦合电路 (5)1.4.2 CML(Current Mode Logic)电流模式电路 (6)1.4.3 GTL(Gunning Transceiver Logic)电路 (6)1.4.4 TTL(Transistor Transistor Logic)电路 (7)1.4.5 BTL(BackPlane Transceiver Logic)电路 (7)1.5信号完整性 (8)1.4.1 反射（Reflection） (8)1.4.2 串扰（Crosstalk） (8)1.4.3 过冲（Overshoot）与下冲（Undershoot） (9)1.4.4 振铃（Ringring） (9)1.4.5 信号延迟(Delay) (9)二、信号完整性分析和仿真流程 (11)2.1 SpecctraQuest interconnect Designer的性能简介 (11)2.2 SpectraQuest(PCB SI)仿真流程 (11)三、仿真前的准备 (13)3.1 IBIS模型 (13)3.1.1 IBIS模型介绍 (13)3.1.2 IBIS模型的获取方法 (14)3.1.2 验证IBIS模型 (14)3.2 预布局 (20)3.3 电路板设置要求（Setup Advisor） (23)3.3.1 叠层设置（Edit Cross-section） (24)3.3.2 设置DC电压值（Identify DC Nets） (25)3.3.3 器件设置（Device Setup） (26)3.3.4 SI模型分配（SI Model Assignment） (27)四、约束驱动布局 (35)4.1 预布局提取和仿真 (35)4.1.2 预布局拓扑提取分析 (37)4.1.3 执行反射仿真 (40)4.1.4 反射仿真测量 (42)4.2 设置和添加约束 (43)4.2.1 运行参数扫描 (43)4.2.2 为拓扑添加约束 (47)4.2.3 分析拓扑约束 (52)五、布线后仿真 (53)5.1 后仿真 (53)5.2反射仿真 (53)5.2.1 设置参数 (53)5.2.2指定要仿真的网络 (53)5.2.3 执行仿真 (55)5.3综合仿真 (57)5.4 串扰仿真 (57)5.5 Simultaneous Switching Noisie仿真 (57)5.6 多析仿真 (57)六、参考文献 (57)说明：本手册中的实例均采用Cadence SPB 16_2操作实现。

Cadence Allegro Sigrity介绍

同时，更高的I/O数目，多堆叠的芯片和封装以及更高的电气性能约束都使得IC 封装物理设计更加复杂。

Cadence具有突破型进展的解决方案，基于Sigrity专利技术，解决这些设计挑战。

Power Integrity电源完整性Cadence 电源完整性（PI）解决方案，基于Sigrity技术，提供signoff 级别精度的PCB和IC封装的AC和DC电源分析。

每个工具都能与Cadence Allegro® PCB 和IC封装物理设计解决方案无缝集成。

PowerSI可以方便的提取封装和PCB的各种网络参数(S/Y/Z)，并对复杂的空间电磁谐振问题产生可视化的输出。

PowerSI能与当前主流的物理设计数据库如PCB, IC封装和系统级封装(SiP)进行无缝连接。

allegro SI 信号完整性仿真

基于Cadence Allegro SI 16.3的信号完整性仿真信号完整性是指信号在信号线上的质量。

信号具有良好的信号完整性是指当在需要的时候，具有所必需达到的电压电平数值。

差的信号完整性不是由某一因素导致的，而是由板级设计中多种因素共同引起的。

特别是在高速电路中，所使用的芯片的切换速度过快、端接元件布设不合理、电路的互联不合理等都会引起信号的完整性问题。

具体主要包括串扰、反射、过冲与下冲、振荡、信号延迟等。

信号完整性问题由多种因素引起，归结起来有反射、串扰、过冲和下冲、振铃、信号延迟等，其中反射和串扰是引发信号完整性问题的两大主要因素。

反射和我们所熟悉的光经过不连续的介质时都会有部分能量反射回来一样，就是信号在传输线上的回波现象。

此时信号功率没有全部传输到负载处，有一部分被反射回来了。

在高速的PCB中导线必须等效为传输线，按照传输线理论，如果源端与负载端具有相同的阻抗，反射就不会发生了。

如果二者阻抗不匹配就会引起反射，负载会将一部分电压反射回源端。

根据负载阻抗和源阻抗的关系大小不同，反射电压可能为正，也可能为负。

如果反射信号很强，叠加在原信号上，很可能改变逻辑状态，导致接收数据错误。

如果在时钟信号上可能引起时钟沿不单调，进而引起误触发。

一般布线的几何形状、不正确的线端接、经过连接器的传输及电源平面的不连续等因素均会导致此类反射。

另外常有一个输出多个接收，这时不同的布线策略产生的反射对每个接收端的影响也不相同，所以布线策略也是影响反射的一个不可忽视的因素。

串扰是相邻两条信号线之间的不必要的耦合，信号线之间的互感和互容引起线上的噪声。

因此也就把它分为感性串扰和容性串扰，分别引发耦合电流和耦合电压。

当信号的边沿速率低于1ns时，串扰问题就应该考虑了。

如果信号线上有交变的信号电流通过时，会产生交变的磁场，处于磁场中的相邻的信号线会感应出信号电压。

一般PCB板层的参数、信号线间距、驱动端和接收端的电气特性及信号线的端接方式对串扰都有一定的影响。

Cadence-SI-Simulation

目前IBIS主要使用的有V1.1，V2.1，V3.2及V4.0等版本。

模型结构如下图：C_pkg，R_pkg，L_pkg为封装参数；C_comp为晶片pad电容；Power_Clamp，GND_Clamp 为ESD结构的V/I曲线。

输出模型比输入模型多一个pull-up，pull-down的V/T曲线。

Cadence的model integrity工具负责对IBIS模型进行语法检查、编辑以及进行DML格式转换。

Cadence仿真不直接使用IBIS模型，而必须先把IBIS转换成DML。

1，叠层设置2，DC电压设置3，器件设置4，模型分配电阻、电容、电感等无源器件的模型可以通过建立ESPICE模型来获得。

<实例操作演示>第四部分：设置仿真参数模型分配完成后，就可以进行仿真了。

在进行仿真之前，需要对仿真的参数进行设置。

Pulse cycle count：通过指定系统传输的脉冲数目来确定仿真的持续时间。

Pulse Clock Frequency：确定仿真中用来激励驱动器的脉冲电压源的频率。

Pulse Duty cycle：脉冲占空比。

基于Cadence的信号完整性仿真步骤

目录1.仿真前的准备工作 (2)1.1找到需要仿真的芯片的IBIS模型 (2)1.2模型转换（IBIS→DML） (2)1.3添加模型到Cadence的模型库中 (5)2. 对电路板进行设置（Setup Advisor） (7)2.1准备好要仿真的电路板 (7)2.2调用参数设置向导 (7)2.3叠层设置 (8)2.4设置DC电压值 (9)2.5器件设置（Device Setup） (10)2.6 SI模型分配 (12)2.7 SI检查（SI Audit） (16)2.8完成参数设置 (18)3.进行信号完整性仿真（反射） (19)3.1开始仿真 (19)3.2选择所要仿真的网络 (19)3.3提取网络的拓扑结构 (20)3.4给驱动端U8添加激励信号 (21)3.5设置激励信号的参数 (22)3.6执行反射仿真 (22)3.7仿真结果 (22)1.仿真前的准备工作1.1找到需要仿真的芯片的IBIS模型一般可以从芯片制造商网站上找到，如果没有，可能要通过其它途径获得如从SPICE模型中提取。

1.2模型转换（IBIS→DML）将IBIS模型转换为DML模型，运用Cadence的Model Integrity工具将IBIS模型转化为Cadence能识别的DML模型，并验证仿真模型。

（1）单击“开始”按钮→“所有程序”→“Allegro SPB 15.5”→“Model Integrity”，如图1-1所示：图1-1 Model Integrity工具窗口（2）选择“File”→“Open”，打开一个IBIS模型如图1-2所示：图1-2 打开一个IBIS模型（3）在“Physical View”栏中，单击IBIS文件“sn74avca16245”→选择菜单栏里的“Options”→“Translation Options Editor”→弹出“Translation Options”窗口，如图1-3所示：图1-3 Translation Options窗口（4）默认选择“Make model names unique”，这个设置为每个IOCell模型名附加IBIS文件名。

cadence allegro规则详解

Cadence Allegro是一款广泛应用于电路设计和布局的软件工具，具有丰富的功能和强大的性能。

在使用Allegro进行电路设计和布局时，遵循一系列规则是非常重要的。

本文将详细介绍Allegro 的规则，并为您提供关于如何正确使用这些规则的指导。

1. 设计规则检查（Design Rule Check，简称DRC）：设计规则检查是在布局之前进行的一项重要步骤。

它可以检查电路设计是否符合一系列预定义的规则。

在Allegro中，DRC可以帮助您检查布线的间距、最小宽度、层间隔等方面是否满足要求。

通过进行DRC，可以及早发现潜在问题并进行修复，从而提高设计的可靠性和性能。

2. 信号完整性规则（Signal Integrity Rules）：信号完整性是电路设计中一个非常重要的方面。

Allegro提供了一系列信号完整性规则，用于检查信号线的阻抗匹配、信号耦合、功耗分析等。

通过遵循信号完整性规则，可以减少信号干扰、提高信号质量，并确保电路的正常运行。

3. 电源和接地规则（Power and Ground Rules）：在电路设计中，电源和接地是至关重要的。

Allegro提供了一些规则，用于检查电源和接地连线的质量和稳定性。

例如，您可以设置规则来检查电源和接地的间距、宽度、连通性等。

通过正确遵循这些规则，可以确保电路具有良好的电源和接地特性，减少功耗和噪声问题。

4. 信号完整性仿真（Signal Integrity Simulation）：除了规则检查外，Allegro还提供了信号完整性仿真工具。

通过仿真，可以模拟电路中信号的传输和干扰情况。

仿真结果可以帮助您评估信号的质量、时钟分析、串扰等，并及时做出必要的调整和改进。

5. 热分析规则（Thermal Analysis Rules）：热分析是电路设计中一个重要的环节，尤其对于高功率电路而言。

Allegro提供了一些规则用于检查电路板的热效应和散热设计。

您可以设置规则来检查器件之间的散热间距、电源和散热器之间的连接等。

allegro_PCB_SI仿真

allegro_PCB_SI仿真IntroductionAllegro PCB SI仿真可以帮助人们在设计PCB 电路板时进行信号完整性仿真，以验证电路设计的有效性和稳定性。

这个工具是Cadence 公司的Allegro 系列产品中的一个，它可以让我们对PCB 电路板进行模拟分析，发现布线中的信号完整性问题，并接下来进行优化，从而得到更好的结果。

下面我们来详细讲解一下Allegro PCB SI仿真的使用。

功能与特点Allegro PCB SI仿真工具主要有以下功能和特点：1. 电路适配性：根据实际电路接口，自动生成仿真模型，无须手工绘制，可节省大量时间和精力。

2. 建模精度：采用仿真模型进行仿真分析，模型的建立过程和仿真数据的处理过程均达到高精度的要求。

3. 可视化展示：提供直观、易于理解的仿真结果图像，用户可对仿真结果进行直观的分析和判断。

4. 高效优化：在分析结果的基础上，提供了一系列可行性方案，以便优化布局和电路设计，提高设计质量和效率。

5. 多维度仿真：支持多种仿真方式，可以分析不同工作频率、物理层、仿真类型等多种因素的影响。

6. 构建模块化：支持多种最新技术，如DDR、PCIe等，可实现模块化的仿真分析。

使用步骤Allegro PCB SI仿真的使用步骤如下：1. 在Allegro 设计工具中添加SI 仿真属性：在Allegro 中进行PCB 设计工作的人员首先需要添加SI 仿真属性。

这时需要使用Allegro constraint manager 工具，在其中添加SI 属性和控制器约束等信息。

Allegro SI 分析扫描过程会依据这些信息实现电路仿真。

2. 运行Allegro SI 分析：电路设计人员在完成电路布线后，需要使用Allegro SI 分析来分析信号完整性情况，以发现和解决可能存在的电路问题。

执行步骤为：首先选择si_analysis 工具，在其菜单中选择指定布线仿真设置；然后在仿真window 中选择仿真起点、仿真长度等参数，然后点击Run。

手册大全--candence使用手册仿真分册

Candence使用手册_仿真分册前言PCB仿真Cadence软件是我们公司统一使用的原理图设计、PCB设计、高速仿真的EDA工具。

进行仿真工作需要有很多方面的知识，须对高速设计的理论有较全面的认识，并对具体的单板原理有一定的了解，还需具备仿真库的相关知识等。

在这个分册中仅对仿真软件的使用进行较详细的阐述，还介绍高速设计的一些相关理论，仿真过程是基于Allegro SPB 15.7的PCB SI模块进行的。

其他知识，如仿真库的知识、约束管理器等请参阅专门的使用手册。

在此非常感谢网络南研 EDA和本部 EDA对此手册的支持。

第一章高速设计与PCB仿真流程本章介绍高速PCB仿真设计的基础知识和重要意义，并介绍基于Cadence 的Allegro SPB15.7的PCB仿真流程。

1.1高速信号与高速设计随着通信系统中逻辑及系统时钟频率的迅速提高和信号边沿不断变陡，PCB的走线和板层特性对系统电气性能的影响也越发显著。

对于低频设计,走线和板层的影响要求不高甚至可以完全忽略不计。

当频率超过 50MHz时，PCB走线则必须以传输线考虑，而在评定系统性能时也必须考虑 PCB 板材的电参数影响。

当系统时钟频率达到120MHz及更高时，就只能使用高速电路设计方法，否则基于传统方法设计的PCB将无法工作。

因此，高速电路设计技术已经成为电子系统设计师必须采取的设计手段，只有通过使用高速电路设计师的设计技术，才能实现设计过程的可控性。

高速系统的设计必须面对互连延迟引起的时序问题以及串扰、传输线效应等信号完整性问题。

通常认为如果数字逻辑电路的频率达到或者超过45MHZ~50MHZ，而且工作在这个频率之上的电路占整个电子系统的一定份量（比如说１／３），就称为高速电路。

实际上，信号边沿的谐波频率比信号本身的频率高，是信号快速变化的上升沿与下降沿（或称信号的跳变）引发了信号传输的非预期结果。

因此，通常约定如果线传播延时大于1/2数字信号驱动端的上升时间，则认为此类信号是高速信号并产生传输线效应，见图1－1所示。

1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。

Cadence PCB SI仿真流程——孙海峰高速高密度多层PCB板的SI/EMC(信号完整性/电磁兼容)问题长久以来一直是设计者所面对的最大挑战。

然而，随着主流的MCU、DSP和处理器大多工作在100MHz以上(有些甚至工作于GHz级以上)，以及越来越多的高速I/O埠和RF前端也都工作在GHz级以上，再加上应用系统的小型化趋势导致的PCB 空间缩小问题，使得目前的高速高密度PCB板设计已经变得越来越普遍。

许多产业分析师指出，在进入21世纪以后，80%以上的多层PCB设计都将会针对高速电路。

高速讯号会导致PCB板上的长互连走线产生传输线效应，它使得PCB设计者必须考虑传输线的延迟和阻抗搭配问题，因为接收端和驱动端的阻抗不搭配都会在传输在线产生反射讯号，而严重影响到讯号的完整性。

另一方面，高密度PCB板上的高速讯号或频率走线则会对间距越来越小的相邻走线产生很难准确量化的串扰与EMC问题。

SI和EMC的问题将会导致PCB设计过程的反复，而使得产品的开发周期一再延误。

一般来说，高速高密度PCB需要复杂的阻抗受控布线策略才能确保电路正常工作。

随着新型组件的电压越来越低、PCB板密度越来越大、边缘转换速率越来越快，以及开发周期越来越短，SI/EMC挑战便日趋严峻。

为了达到这个挑战的要求，目前的PCB设计者必须采用新的方法来确保其PCB设计的可行性与可制造性。

过去的传统设计规则已经无法满足今日的时序和讯号完整性要求，而必须采取包含仿真功能的新款工具才足以确保设计成功。

Cadence的Allegro PCB SI提供了一种弹性化且整合的信号完整性问题解决方案，它是一种完整的SI/PI(功率完整性)/EMI问题的协同解决方案，适用于高速PCB设计周期的每个阶段，并解决与电气性能相关的问题。

Allegro PCB SI信号完整性分析的操作步骤，就是接下来将要介绍的。

一、Allegro PCB SI分析前准备：1、准备需要分析的PCB，如下图；2、SI分析前的相关设置，执行T ools/Setup Advisor,进入Database Setup Advisor 对话框，进行SI分析前的设置；（1）设置PCB叠层的材料、阻抗等，点击Edit Cross section，进入叠层阻抗等设置界面。

（2）设置直流电压网络的参考值，点击Identify DC Nets ，进入直流电压参考值的设置界面。

（3）零件默认设置，点击Device Setup 进入设置界面。

（4）信号完整性分析需要PCB 上的零件都有自己的电气模型，在这一步里，进入SI Model Assignment 界面，进行零件的模型赋予。

在Signal Model Assignment 模型赋予的界面中，对于集总元件R 、C 、L 而言，可以直接点击Create Model 来创建元件电气模型。

对于有源器件和其他芯片，可以点击Find Model，进入SI Model Browser 界面，寻找器件对应的SI仿真模型，然后点击Assign命令，赋予元件对应的DML信号完整性分析模型。

其中元件的IBIS模型通常芯片生产厂家都会提供，在其网上下载即可。

（5）零件的SI模型审核，点击SI Audit进入Net Audit界面，选择相应网络进行审核。

（6）点击Finish 命令，弹出SigNoise Setup Report 窗口，这里是信号完整性分析的设置报告。

二、SI信号完整性分析：SI分析的前期准备完成之后，就可以进行信号完整性分析了，执行Analyze/SI EMI Sim/Probe命令，然后选择需要进行SI分析的网络或者差分对（模型分配中必须设置好差分对），如下图所示：取出来，如下图：网络拓扑结构提取成功之后，接下来就是设置仿真默认参数，设置驱动端激励源信号，然后就是分析得到网络信号完整性分析波形，具体流程如下。

1、仿真默认参数设置在提取的网络拓扑结构中，执行Analyze/Preferences…命令，弹出AnalysisPreferences对话框，设置信号完整性分析的默认参数。

有以下几点：（1）Pulse Stimulus栏，用以设置默认激励源，Measurement Cycle设置仿真分析的周期数；Switching Frequency设置默认脉冲激励的频率；Duty Cycle 设置脉冲激励的占空比；Offset设置激励源相位。

（2）仿真参数（Simulation Parameters）设置，Fixed Duration设置脉冲激励的持续时间；Waveform Resolution设置输出波形的分辨时间；Default Cutoff Frequency设置分析截止时间；Simulator和Solver设置仿真分析的解算器和分析算法。

（3）仿真模式（Simulation Modes）设置，FTS Modes（s）设置仿真类型，有典型分析，还有两种最坏情况分析，即Fast、Slow两种模式.(4)测量模式（Measurement Modes）设置，Measure Delay At脉冲延时设置；Receiver Selection接收端选择；Custom Simulation设置用户分析类型，Reflection信号反射分析，Crosstalk串扰分析，EMI电磁干扰分析；Drvr Measurement Location设置驱动端位置，Pin表示驱动端在芯片外部封装引脚处，Die则表示驱动端信号在芯片内部的裸片引脚处；Rcvr Measurement Location设置接收端信号位置，也是Pin和Die两种选择，意义相同。

结束以上的设置，即完成了SI分析的默认参数设置，接下来就需要设置驱动端的激励源设置。

2、驱动端激励源设置SI仿真分析，都需要设置好驱动端的激励源，然后才能进行分析。

在驱动端点击TRISTATE，弹出Stimulus Edit激励源编辑窗口，在这里进行激励源的编辑，如下图。

Stimulus State选择激励源状态；T erminal Info设置激励源输出信息；Stimulus Editing设置激励源的频率，初始值，转换边沿，激励信号输出波形。

3、 SI信号完整性分析驱动端激励源设置完成后，就可以进行SI分析了，在SigXlorer界面中，执行Analyze/Simulate命令，即可进入SigWave窗口，输出该网络SI分析的波形。

这就是输出波形，是对相应网络进行SI分析的结果。

其中ROUTED-0 U2003是驱动端芯片U200的外部封装引脚3处的波形，ROUTED-0 U200 3i则表示驱动端芯片U200的内部裸片引脚3处的波形。

三、IBIS模型IBIS（Input/Output Buffer Informational Specifation）是用来描述IC 器件的输入、输出和I/O Buffer行为特性的文件，并且用来模拟Buffer和PCB上电路系统的相互作用。

在IBIS模型里核心内容就是Buffer的模型，因为这些Buffer 产生一些模拟的波形，仿真器利用这些波形仿真出传输线、对PCB的影响和一些高速现象（如串扰，EMI 等）。

具体而言IBIS 描述了一个Buffer 的输入和输出阻抗（通过I/V曲线的形式）、上升和下降时间以及对于不同情况下的上拉和下拉，那么工程人员可以利用这个模型对PCB 板上的电路系统进行SI、串扰、EMC 以及时序的分析。

IBIS 模型中包含的是一些可读的ASCII 格式的列表数据。

IBIS 有特定的语法和书写格式。

IBIS模型中还包括一些电气说明如V inh 、V inl 、V meas 以及管脚的寄生参数（如管脚的引线R、L、C等）。

有一点需要注意的是IBIS 模型并不提供IC 器件：功能信息、逻辑信息、输入到输出的时间延迟等。

也就是说，IBIS 模型只是提供了器件的输入、输出以及I/O Buffer 的行为特性，而不是在IC 器件给定不同的输入，测量对应不同的输出波形；而是在描述器件有一个输入时，我们看不同情况下输出的特性（具体的说我们可以在输出端接一个电压源，这样我们在确保器件输出高电平或者是低电平时，调整电压源的数值，可以测出不同的电流，这样我们就可以在确保输出管脚输出某一个状态时得出一些I/V 的数值，至于电压源具体的变化范围后面的内容会涉及到）。

所以对于器件商家而言IBIS模型不会泄漏器件的内部逻辑电路的结构。

要实现上面提到的对系统的SI和时序的仿真，那么需要的基本的信息就是Buffer的I/V曲线和转换特性。

IBIS模型中Buffer的数据信息可以通过测量器件得出也可以通过器件的SPICE模型转换得到。

IBIS是一个简单的模型，当做简单的带负载仿真时，比相应的全Spice三极管级模型仿真要节省10～15倍的计算量。

IBIS 模型是基于器件的，就是说一个IBIS 模型是对于整个器件的管脚而言的，而不是几个特殊的输入、输出或者是I/O 管脚的Buffer。

因此IBIS 模型中除了一些器件Buffer的电气特性，还包括引脚pin与buffer 的映射关系（除了电源、地和没有连接的管脚，每个管脚都有一个特定的Buffer），以及器件的封装参数。

IBIS提供两条完整的V－I曲线，分别代表驱动器为高电平和低电平状态，以及在确定的转换速度下状态转换的曲线。

V－I曲线的作用在于为IBIS提供保护二极管、TTL推拉驱动源以及射极跟随输出等非线性效应的建模能力。

一般而言，IC器件的输入、输出和I/O 管脚的Buffer的行为特性是通过一定的形式描述的。

下面分别对于输入、输出和I/O 管脚Buffer 的表述形式作一个介绍。

对于一个输出或者是I/O 管脚的Buffer需要下列的相关数据：1、输出为逻辑低时，输出管脚Buffer 的I/V 特性；2、输出为逻辑高时，输出管脚Buffer 的I/V 特性；3、输出电平强制在Vcc以上和GND以下时，输出管脚Buffer的I/V 特性；4、Buffer由一个状态转换为另一个状态的转换时间；5、Buffer的输出电容。

对于一个输入管脚的Buffer 需要以下的数据：1、输入Buffer 的I/V 曲线（包括电平高于V cc 或者是低于GND）；2、Buffer的输入电容一般情况，IBIS 模型包含以下一些信息，IBIS 模型的结构如下图1 所示。

1、关于文件本身和器件名字的信息。

这些信息用以下的关键词描述：[IBIS Ver] IBIS的版本号, [File Name]文件的名称，[File Rev]文件的版号，[Component]器件的名称，[Manufacturer]器件制造商；2、关于器件的封装电气特性和管脚与Buffer模型的映射关系。